1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_math.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
36 #include "freedreno_program.h"
38 #include "fd3_program.h"
40 #include "fd3_texture.h"
41 #include "fd3_format.h"
43 static struct ir3_shader
*
44 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
47 struct fd_context
*ctx
= fd_context(pctx
);
48 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
49 return ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
);
53 fd3_fp_state_create(struct pipe_context
*pctx
,
54 const struct pipe_shader_state
*cso
)
56 return create_shader_stateobj(pctx
, cso
, SHADER_FRAGMENT
);
60 fd3_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
62 struct ir3_shader
*so
= hwcso
;
63 ir3_shader_destroy(so
);
67 fd3_vp_state_create(struct pipe_context
*pctx
,
68 const struct pipe_shader_state
*cso
)
70 return create_shader_stateobj(pctx
, cso
, SHADER_VERTEX
);
74 fd3_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
76 struct ir3_shader
*so
= hwcso
;
77 ir3_shader_destroy(so
);
81 fd3_needs_manual_clipping(const struct ir3_shader
*shader
,
82 const struct pipe_rasterizer_state
*rast
)
84 uint64_t outputs
= ir3_shader_outputs(shader
);
86 return (!rast
->depth_clip
||
87 util_bitcount(rast
->clip_plane_enable
) > 6 ||
88 outputs
& ((1ULL << VARYING_SLOT_CLIP_VERTEX
) |
89 (1ULL << VARYING_SLOT_CLIP_DIST0
) |
90 (1ULL << VARYING_SLOT_CLIP_DIST1
)));
95 emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
97 const struct ir3_info
*si
= &so
->info
;
98 enum adreno_state_block sb
;
99 enum adreno_state_src src
;
100 uint32_t i
, sz
, *bin
;
102 if (so
->type
== SHADER_VERTEX
) {
108 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
111 bin
= fd_bo_map(so
->bo
);
118 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
119 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
120 CP_LOAD_STATE_0_STATE_SRC(src
) |
121 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
122 CP_LOAD_STATE_0_NUM_UNIT(so
->instrlen
));
124 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
125 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
));
127 OUT_RELOC(ring
, so
->bo
, 0,
128 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
), 0);
130 for (i
= 0; i
< sz
; i
++) {
131 OUT_RING(ring
, bin
[i
]);
136 fd3_program_emit(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
,
137 int nr
, struct pipe_surface
**bufs
)
139 const struct ir3_shader_variant
*vp
, *fp
;
140 const struct ir3_info
*vsi
, *fsi
;
141 enum a3xx_instrbuffermode fpbuffer
, vpbuffer
;
142 uint32_t fpbuffersz
, vpbuffersz
, fsoff
;
143 uint32_t pos_regid
, posz_regid
, psize_regid
, color_regid
[4] = {0};
147 debug_assert(nr
<= ARRAY_SIZE(color_regid
));
149 vp
= fd3_emit_get_vp(emit
);
150 fp
= fd3_emit_get_fp(emit
);
157 fpbuffersz
= fp
->instrlen
;
158 vpbuffersz
= vp
->instrlen
;
161 * Decide whether to use BUFFER or CACHE mode for VS and FS. It
162 * appears like 256 is the hard limit, but when the combined size
163 * exceeds 128 then blob will try to keep FS in BUFFER mode and
164 * switch to CACHE for VS until VS is too large. The blob seems
165 * to switch FS out of BUFFER mode at slightly under 128. But
166 * a bit fuzzy on the decision tree, so use slightly conservative
169 * TODO check if these thresholds for BUFFER vs CACHE mode are the
170 * same for all a3xx or whether we need to consider the gpuid
173 if ((fpbuffersz
+ vpbuffersz
) > 128) {
174 if (fpbuffersz
< 112) {
175 /* FP:BUFFER VP:CACHE */
177 vpbuffersz
= 256 - fpbuffersz
;
178 } else if (vpbuffersz
< 112) {
179 /* FP:CACHE VP:BUFFER */
181 fpbuffersz
= 256 - vpbuffersz
;
183 /* FP:CACHE VP:CACHE */
184 vpbuffer
= fpbuffer
= CACHE
;
185 vpbuffersz
= fpbuffersz
= 192;
189 if (fpbuffer
== BUFFER
) {
190 fsoff
= 128 - fpbuffersz
;
192 fsoff
= 256 - fpbuffersz
;
195 /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
196 constmode
= ((vp
->constlen
+ fp
->constlen
) > 256) ? 1 : 0;
198 pos_regid
= ir3_find_output_regid(vp
, VARYING_SLOT_POS
);
199 posz_regid
= ir3_find_output_regid(fp
, FRAG_RESULT_DEPTH
);
200 psize_regid
= ir3_find_output_regid(vp
, VARYING_SLOT_PSIZ
);
201 if (fp
->color0_mrt
) {
202 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
203 ir3_find_output_regid(fp
, FRAG_RESULT_COLOR
);
205 color_regid
[0] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA0
);
206 color_regid
[1] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA1
);
207 color_regid
[2] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA2
);
208 color_regid
[3] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA3
);
211 /* adjust regids for alpha output formats. there is no alpha render
212 * format, so it's just treated like red
214 for (i
= 0; i
< nr
; i
++)
215 if (util_format_is_alpha(pipe_surface_format(bufs
[i
])))
218 /* we could probably divide this up into things that need to be
219 * emitted if frag-prog is dirty vs if vert-prog is dirty..
222 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 6);
223 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
224 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode
) |
225 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
226 * flush some caches? I think we only need to set those
227 * bits if we have updated const or shader..
229 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
|
230 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
231 OUT_RING(ring
, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
232 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
|
233 COND(fp
->frag_coord
, A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(regid(0,0)) |
234 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(regid(0,2))));
235 OUT_RING(ring
, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
236 OUT_RING(ring
, A3XX_HLSQ_CONTROL_3_REG_REGID(fp
->pos_regid
));
237 OUT_RING(ring
, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp
->constlen
) |
238 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
239 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz
));
240 OUT_RING(ring
, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp
->constlen
) |
241 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
242 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz
));
244 OUT_PKT0(ring
, REG_A3XX_SP_SP_CTRL_REG
, 1);
245 OUT_RING(ring
, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode
) |
246 COND(emit
->key
.binning_pass
, A3XX_SP_SP_CTRL_REG_BINNING
) |
247 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
248 A3XX_SP_SP_CTRL_REG_L0MODE(0));
250 OUT_PKT0(ring
, REG_A3XX_SP_VS_LENGTH_REG
, 1);
251 OUT_RING(ring
, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp
->instrlen
));
253 OUT_PKT0(ring
, REG_A3XX_SP_VS_CTRL_REG0
, 3);
254 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI
) |
255 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer
) |
256 COND(vpbuffer
== CACHE
, A3XX_SP_VS_CTRL_REG0_CACHEINVALID
) |
257 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi
->max_half_reg
+ 1) |
258 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi
->max_reg
+ 1) |
259 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
260 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
|
261 A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz
));
262 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp
->constlen
) |
263 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp
->total_in
) |
264 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp
->constlen
+ 1, 0)));
265 OUT_RING(ring
, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid
) |
266 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid
) |
267 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp
->varying_in
));
269 struct ir3_shader_linkage l
= {0};
270 ir3_link_shaders(&l
, vp
, fp
);
272 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
275 OUT_PKT0(ring
, REG_A3XX_SP_VS_OUT_REG(i
), 1);
277 reg
|= A3XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
278 reg
|= A3XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
281 reg
|= A3XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
282 reg
|= A3XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
288 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
291 OUT_PKT0(ring
, REG_A3XX_SP_VS_VPC_DST_REG(i
), 1);
293 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
+ 8);
294 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
+ 8);
295 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
+ 8);
296 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
+ 8);
301 OUT_PKT0(ring
, REG_A3XX_SP_VS_OBJ_OFFSET_REG
, 2);
302 OUT_RING(ring
, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
303 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
304 OUT_RELOC(ring
, vp
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_REG */
306 if (emit
->key
.binning_pass
) {
307 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
308 OUT_RING(ring
, 0x00000000);
310 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
311 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
312 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER
));
313 OUT_RING(ring
, 0x00000000);
315 OUT_PKT0(ring
, REG_A3XX_SP_FS_OBJ_OFFSET_REG
, 1);
316 OUT_RING(ring
, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
317 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
319 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
320 OUT_RING(ring
, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp
->instrlen
));
322 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
323 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
324 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer
) |
325 COND(fpbuffer
== CACHE
, A3XX_SP_FS_CTRL_REG0_CACHEINVALID
) |
326 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi
->max_half_reg
+ 1) |
327 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi
->max_reg
+ 1) |
328 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP
|
329 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
330 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
|
331 COND(fp
->has_samp
> 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE
) |
332 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz
));
333 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp
->constlen
) |
334 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp
->total_in
) |
335 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp
->constlen
+ 1, 0)) |
336 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
338 OUT_PKT0(ring
, REG_A3XX_SP_FS_OBJ_OFFSET_REG
, 2);
339 OUT_RING(ring
, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
340 MAX2(128, vp
->constlen
)) |
341 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff
));
342 OUT_RELOC(ring
, fp
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_REG */
345 OUT_PKT0(ring
, REG_A3XX_SP_FS_OUTPUT_REG
, 1);
347 COND(fp
->writes_pos
, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
) |
348 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid
) |
349 A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr
) - 1));
351 OUT_PKT0(ring
, REG_A3XX_SP_FS_MRT_REG(0), 4);
352 for (i
= 0; i
< 4; i
++) {
353 uint32_t mrt_reg
= A3XX_SP_FS_MRT_REG_REGID(color_regid
[i
]) |
354 COND(fp
->key
.half_precision
, A3XX_SP_FS_MRT_REG_HALF_PRECISION
);
357 enum pipe_format fmt
= pipe_surface_format(bufs
[i
]);
358 mrt_reg
|= COND(util_format_is_pure_uint(fmt
), A3XX_SP_FS_MRT_REG_UINT
) |
359 COND(util_format_is_pure_sint(fmt
), A3XX_SP_FS_MRT_REG_SINT
);
361 OUT_RING(ring
, mrt_reg
);
364 if (emit
->key
.binning_pass
) {
365 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
366 OUT_RING(ring
, A3XX_VPC_ATTR_THRDASSIGN(1) |
367 A3XX_VPC_ATTR_LMSIZE(1) |
368 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
369 OUT_RING(ring
, 0x00000000);
371 uint32_t vinterp
[4], flatshade
[2], vpsrepl
[4];
373 memset(vinterp
, 0, sizeof(vinterp
));
374 memset(flatshade
, 0, sizeof(flatshade
));
375 memset(vpsrepl
, 0, sizeof(vpsrepl
));
377 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
378 for (j
= -1; (j
= ir3_next_varying(fp
, j
)) < (int)fp
->inputs_count
; ) {
379 /* NOTE: varyings are packed, so if compmask is 0xb
380 * then first, third, and fourth component occupy
381 * three consecutive varying slots:
383 unsigned compmask
= fp
->inputs
[j
].compmask
;
385 uint32_t inloc
= fp
->inputs
[j
].inloc
;
387 if ((fp
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
388 (fp
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
389 uint32_t loc
= inloc
;
391 for (i
= 0; i
< 4; i
++) {
392 if (compmask
& (1 << i
)) {
393 vinterp
[loc
/ 16] |= FLAT
<< ((loc
% 16) * 2);
394 flatshade
[loc
/ 32] |= 1 << (loc
% 32);
400 gl_varying_slot slot
= fp
->inputs
[j
].slot
;
402 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
403 if (slot
>= VARYING_SLOT_VAR0
) {
404 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
405 /* Replace the .xy coordinates with S/T from the point sprite. Set
406 * interpolation bits for .zw such that they become .01
408 if (emit
->sprite_coord_enable
& texmask
) {
409 /* mask is two 2-bit fields, where:
412 * '11' -> 1 - T (flip mode)
414 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
415 uint32_t loc
= inloc
;
416 if (compmask
& 0x1) {
417 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
420 if (compmask
& 0x2) {
421 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
424 if (compmask
& 0x4) {
426 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
429 if (compmask
& 0x8) {
431 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
438 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
439 OUT_RING(ring
, A3XX_VPC_ATTR_TOTALATTR(fp
->total_in
) |
440 A3XX_VPC_ATTR_THRDASSIGN(1) |
441 A3XX_VPC_ATTR_LMSIZE(1) |
442 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
443 OUT_RING(ring
, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp
->total_in
) |
444 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp
->total_in
));
446 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
447 OUT_RING(ring
, vinterp
[0]); /* VPC_VARYING_INTERP[0].MODE */
448 OUT_RING(ring
, vinterp
[1]); /* VPC_VARYING_INTERP[1].MODE */
449 OUT_RING(ring
, vinterp
[2]); /* VPC_VARYING_INTERP[2].MODE */
450 OUT_RING(ring
, vinterp
[3]); /* VPC_VARYING_INTERP[3].MODE */
452 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
453 OUT_RING(ring
, vpsrepl
[0]); /* VPC_VARYING_PS_REPL[0].MODE */
454 OUT_RING(ring
, vpsrepl
[1]); /* VPC_VARYING_PS_REPL[1].MODE */
455 OUT_RING(ring
, vpsrepl
[2]); /* VPC_VARYING_PS_REPL[2].MODE */
456 OUT_RING(ring
, vpsrepl
[3]); /* VPC_VARYING_PS_REPL[3].MODE */
458 OUT_PKT0(ring
, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0
, 2);
459 OUT_RING(ring
, flatshade
[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
460 OUT_RING(ring
, flatshade
[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
463 if (vpbuffer
== BUFFER
)
464 emit_shader(ring
, vp
);
466 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
467 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
469 if (!emit
->key
.binning_pass
) {
470 if (fpbuffer
== BUFFER
)
471 emit_shader(ring
, fp
);
473 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
474 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
479 fd3_prog_init(struct pipe_context
*pctx
)
481 pctx
->create_fs_state
= fd3_fp_state_create
;
482 pctx
->delete_fs_state
= fd3_fp_state_delete
;
484 pctx
->create_vs_state
= fd3_vp_state_create
;
485 pctx
->delete_vs_state
= fd3_vp_state_delete
;