1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_math.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
36 #include "freedreno_program.h"
38 #include "fd3_program.h"
40 #include "fd3_texture.h"
41 #include "fd3_format.h"
43 static struct ir3_shader
*
44 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
47 struct fd_context
*ctx
= fd_context(pctx
);
48 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
49 return ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
);
53 fd3_fp_state_create(struct pipe_context
*pctx
,
54 const struct pipe_shader_state
*cso
)
56 return create_shader_stateobj(pctx
, cso
, SHADER_FRAGMENT
);
60 fd3_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
62 struct ir3_shader
*so
= hwcso
;
63 ir3_shader_destroy(so
);
67 fd3_vp_state_create(struct pipe_context
*pctx
,
68 const struct pipe_shader_state
*cso
)
70 return create_shader_stateobj(pctx
, cso
, SHADER_VERTEX
);
74 fd3_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
76 struct ir3_shader
*so
= hwcso
;
77 ir3_shader_destroy(so
);
81 fd3_needs_manual_clipping(const struct ir3_shader
*shader
,
82 const struct pipe_rasterizer_state
*rast
)
84 uint64_t outputs
= ir3_shader_outputs(shader
);
86 return (!rast
->depth_clip_near
||
87 util_bitcount(rast
->clip_plane_enable
) > 6 ||
88 outputs
& ((1ULL << VARYING_SLOT_CLIP_VERTEX
) |
89 (1ULL << VARYING_SLOT_CLIP_DIST0
) |
90 (1ULL << VARYING_SLOT_CLIP_DIST1
)));
95 emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
97 const struct ir3_info
*si
= &so
->info
;
98 enum adreno_state_block sb
;
99 enum adreno_state_src src
;
100 uint32_t i
, sz
, *bin
;
102 if (so
->type
== SHADER_VERTEX
) {
108 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
111 bin
= fd_bo_map(so
->bo
);
118 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
119 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
120 CP_LOAD_STATE_0_STATE_SRC(src
) |
121 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
122 CP_LOAD_STATE_0_NUM_UNIT(so
->instrlen
));
124 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
125 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
));
127 OUT_RELOC(ring
, so
->bo
, 0,
128 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
), 0);
130 for (i
= 0; i
< sz
; i
++) {
131 OUT_RING(ring
, bin
[i
]);
136 fd3_program_emit(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
,
137 int nr
, struct pipe_surface
**bufs
)
139 const struct ir3_shader_variant
*vp
, *fp
;
140 const struct ir3_info
*vsi
, *fsi
;
141 enum a3xx_instrbuffermode fpbuffer
, vpbuffer
;
142 uint32_t fpbuffersz
, vpbuffersz
, fsoff
;
143 uint32_t pos_regid
, posz_regid
, psize_regid
;
144 uint32_t vcoord_regid
, face_regid
, coord_regid
, zwcoord_regid
;
145 uint32_t color_regid
[4] = {0};
149 debug_assert(nr
<= ARRAY_SIZE(color_regid
));
151 vp
= fd3_emit_get_vp(emit
);
152 fp
= fd3_emit_get_fp(emit
);
159 fpbuffersz
= fp
->instrlen
;
160 vpbuffersz
= vp
->instrlen
;
163 * Decide whether to use BUFFER or CACHE mode for VS and FS. It
164 * appears like 256 is the hard limit, but when the combined size
165 * exceeds 128 then blob will try to keep FS in BUFFER mode and
166 * switch to CACHE for VS until VS is too large. The blob seems
167 * to switch FS out of BUFFER mode at slightly under 128. But
168 * a bit fuzzy on the decision tree, so use slightly conservative
171 * TODO check if these thresholds for BUFFER vs CACHE mode are the
172 * same for all a3xx or whether we need to consider the gpuid
175 if ((fpbuffersz
+ vpbuffersz
) > 128) {
176 if (fpbuffersz
< 112) {
177 /* FP:BUFFER VP:CACHE */
179 vpbuffersz
= 256 - fpbuffersz
;
180 } else if (vpbuffersz
< 112) {
181 /* FP:CACHE VP:BUFFER */
183 fpbuffersz
= 256 - vpbuffersz
;
185 /* FP:CACHE VP:CACHE */
186 vpbuffer
= fpbuffer
= CACHE
;
187 vpbuffersz
= fpbuffersz
= 192;
191 if (fpbuffer
== BUFFER
) {
192 fsoff
= 128 - fpbuffersz
;
194 fsoff
= 256 - fpbuffersz
;
197 /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
198 constmode
= ((vp
->constlen
+ fp
->constlen
) > 256) ? 1 : 0;
200 pos_regid
= ir3_find_output_regid(vp
, VARYING_SLOT_POS
);
201 posz_regid
= ir3_find_output_regid(fp
, FRAG_RESULT_DEPTH
);
202 psize_regid
= ir3_find_output_regid(vp
, VARYING_SLOT_PSIZ
);
203 if (fp
->color0_mrt
) {
204 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
205 ir3_find_output_regid(fp
, FRAG_RESULT_COLOR
);
207 color_regid
[0] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA0
);
208 color_regid
[1] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA1
);
209 color_regid
[2] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA2
);
210 color_regid
[3] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA3
);
213 face_regid
= ir3_find_sysval_regid(fp
, SYSTEM_VALUE_FRONT_FACE
);
214 coord_regid
= ir3_find_sysval_regid(fp
, SYSTEM_VALUE_FRAG_COORD
);
215 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
216 vcoord_regid
= ir3_find_sysval_regid(fp
, SYSTEM_VALUE_VARYING_COORD
);
218 /* adjust regids for alpha output formats. there is no alpha render
219 * format, so it's just treated like red
221 for (i
= 0; i
< nr
; i
++)
222 if (util_format_is_alpha(pipe_surface_format(bufs
[i
])))
225 /* we could probably divide this up into things that need to be
226 * emitted if frag-prog is dirty vs if vert-prog is dirty..
229 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 6);
230 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
231 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode
) |
232 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
233 * flush some caches? I think we only need to set those
234 * bits if we have updated const or shader..
236 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
|
237 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
238 OUT_RING(ring
, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
239 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
|
240 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(coord_regid
) |
241 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(zwcoord_regid
));
242 OUT_RING(ring
, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31) |
243 A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(face_regid
));
244 OUT_RING(ring
, A3XX_HLSQ_CONTROL_3_REG_REGID(vcoord_regid
));
245 OUT_RING(ring
, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp
->constlen
) |
246 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
247 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz
));
248 OUT_RING(ring
, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp
->constlen
) |
249 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
250 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz
));
252 OUT_PKT0(ring
, REG_A3XX_SP_SP_CTRL_REG
, 1);
253 OUT_RING(ring
, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode
) |
254 COND(emit
->key
.binning_pass
, A3XX_SP_SP_CTRL_REG_BINNING
) |
255 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
256 A3XX_SP_SP_CTRL_REG_L0MODE(0));
258 OUT_PKT0(ring
, REG_A3XX_SP_VS_LENGTH_REG
, 1);
259 OUT_RING(ring
, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp
->instrlen
));
261 OUT_PKT0(ring
, REG_A3XX_SP_VS_CTRL_REG0
, 3);
262 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI
) |
263 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer
) |
264 COND(vpbuffer
== CACHE
, A3XX_SP_VS_CTRL_REG0_CACHEINVALID
) |
265 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi
->max_half_reg
+ 1) |
266 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi
->max_reg
+ 1) |
267 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
268 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
|
269 A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz
));
270 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp
->constlen
) |
271 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp
->total_in
) |
272 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp
->constlen
+ 1, 0)));
273 OUT_RING(ring
, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid
) |
274 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid
) |
275 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp
->varying_in
));
277 struct ir3_shader_linkage l
= {0};
278 ir3_link_shaders(&l
, vp
, fp
);
280 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
283 OUT_PKT0(ring
, REG_A3XX_SP_VS_OUT_REG(i
), 1);
285 reg
|= A3XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
286 reg
|= A3XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
289 reg
|= A3XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
290 reg
|= A3XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
296 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
299 OUT_PKT0(ring
, REG_A3XX_SP_VS_VPC_DST_REG(i
), 1);
301 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
+ 8);
302 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
+ 8);
303 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
+ 8);
304 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
+ 8);
309 OUT_PKT0(ring
, REG_A3XX_SP_VS_OBJ_OFFSET_REG
, 2);
310 OUT_RING(ring
, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
311 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
312 OUT_RELOC(ring
, vp
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_REG */
314 if (emit
->key
.binning_pass
) {
315 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
316 OUT_RING(ring
, 0x00000000);
318 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
319 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
320 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER
));
321 OUT_RING(ring
, 0x00000000);
323 OUT_PKT0(ring
, REG_A3XX_SP_FS_OBJ_OFFSET_REG
, 1);
324 OUT_RING(ring
, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
325 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
327 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
328 OUT_RING(ring
, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp
->instrlen
));
330 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
331 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
332 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer
) |
333 COND(fpbuffer
== CACHE
, A3XX_SP_FS_CTRL_REG0_CACHEINVALID
) |
334 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi
->max_half_reg
+ 1) |
335 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi
->max_reg
+ 1) |
336 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP
|
337 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
338 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
|
339 COND(fp
->has_samp
> 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE
) |
340 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz
));
341 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp
->constlen
) |
342 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp
->total_in
) |
343 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp
->constlen
+ 1, 0)) |
344 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
346 OUT_PKT0(ring
, REG_A3XX_SP_FS_OBJ_OFFSET_REG
, 2);
347 OUT_RING(ring
, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
348 MAX2(128, vp
->constlen
)) |
349 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff
));
350 OUT_RELOC(ring
, fp
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_REG */
353 OUT_PKT0(ring
, REG_A3XX_SP_FS_OUTPUT_REG
, 1);
355 COND(fp
->writes_pos
, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
) |
356 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid
) |
357 A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr
) - 1));
359 OUT_PKT0(ring
, REG_A3XX_SP_FS_MRT_REG(0), 4);
360 for (i
= 0; i
< 4; i
++) {
361 uint32_t mrt_reg
= A3XX_SP_FS_MRT_REG_REGID(color_regid
[i
]) |
362 COND(fp
->key
.half_precision
, A3XX_SP_FS_MRT_REG_HALF_PRECISION
);
365 enum pipe_format fmt
= pipe_surface_format(bufs
[i
]);
366 mrt_reg
|= COND(util_format_is_pure_uint(fmt
), A3XX_SP_FS_MRT_REG_UINT
) |
367 COND(util_format_is_pure_sint(fmt
), A3XX_SP_FS_MRT_REG_SINT
);
369 OUT_RING(ring
, mrt_reg
);
372 if (emit
->key
.binning_pass
) {
373 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
374 OUT_RING(ring
, A3XX_VPC_ATTR_THRDASSIGN(1) |
375 A3XX_VPC_ATTR_LMSIZE(1) |
376 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
377 OUT_RING(ring
, 0x00000000);
379 uint32_t vinterp
[4], flatshade
[2], vpsrepl
[4];
381 memset(vinterp
, 0, sizeof(vinterp
));
382 memset(flatshade
, 0, sizeof(flatshade
));
383 memset(vpsrepl
, 0, sizeof(vpsrepl
));
385 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
386 for (j
= -1; (j
= ir3_next_varying(fp
, j
)) < (int)fp
->inputs_count
; ) {
387 /* NOTE: varyings are packed, so if compmask is 0xb
388 * then first, third, and fourth component occupy
389 * three consecutive varying slots:
391 unsigned compmask
= fp
->inputs
[j
].compmask
;
393 uint32_t inloc
= fp
->inputs
[j
].inloc
;
395 if ((fp
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
396 (fp
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
397 uint32_t loc
= inloc
;
399 for (i
= 0; i
< 4; i
++) {
400 if (compmask
& (1 << i
)) {
401 vinterp
[loc
/ 16] |= FLAT
<< ((loc
% 16) * 2);
402 flatshade
[loc
/ 32] |= 1 << (loc
% 32);
408 gl_varying_slot slot
= fp
->inputs
[j
].slot
;
410 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
411 if (slot
>= VARYING_SLOT_VAR0
) {
412 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
413 /* Replace the .xy coordinates with S/T from the point sprite. Set
414 * interpolation bits for .zw such that they become .01
416 if (emit
->sprite_coord_enable
& texmask
) {
417 /* mask is two 2-bit fields, where:
420 * '11' -> 1 - T (flip mode)
422 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
423 uint32_t loc
= inloc
;
424 if (compmask
& 0x1) {
425 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
428 if (compmask
& 0x2) {
429 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
432 if (compmask
& 0x4) {
434 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
437 if (compmask
& 0x8) {
439 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
446 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
447 OUT_RING(ring
, A3XX_VPC_ATTR_TOTALATTR(fp
->total_in
) |
448 A3XX_VPC_ATTR_THRDASSIGN(1) |
449 A3XX_VPC_ATTR_LMSIZE(1) |
450 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
451 OUT_RING(ring
, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp
->total_in
) |
452 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp
->total_in
));
454 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
455 OUT_RING(ring
, vinterp
[0]); /* VPC_VARYING_INTERP[0].MODE */
456 OUT_RING(ring
, vinterp
[1]); /* VPC_VARYING_INTERP[1].MODE */
457 OUT_RING(ring
, vinterp
[2]); /* VPC_VARYING_INTERP[2].MODE */
458 OUT_RING(ring
, vinterp
[3]); /* VPC_VARYING_INTERP[3].MODE */
460 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
461 OUT_RING(ring
, vpsrepl
[0]); /* VPC_VARYING_PS_REPL[0].MODE */
462 OUT_RING(ring
, vpsrepl
[1]); /* VPC_VARYING_PS_REPL[1].MODE */
463 OUT_RING(ring
, vpsrepl
[2]); /* VPC_VARYING_PS_REPL[2].MODE */
464 OUT_RING(ring
, vpsrepl
[3]); /* VPC_VARYING_PS_REPL[3].MODE */
466 OUT_PKT0(ring
, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0
, 2);
467 OUT_RING(ring
, flatshade
[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
468 OUT_RING(ring
, flatshade
[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
471 if (vpbuffer
== BUFFER
)
472 emit_shader(ring
, vp
);
474 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
475 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
477 if (!emit
->key
.binning_pass
) {
478 if (fpbuffer
== BUFFER
)
479 emit_shader(ring
, fp
);
481 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
482 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
487 fd3_prog_init(struct pipe_context
*pctx
)
489 pctx
->create_fs_state
= fd3_fp_state_create
;
490 pctx
->delete_fs_state
= fd3_fp_state_delete
;
492 pctx
->create_vs_state
= fd3_vp_state_create
;
493 pctx
->delete_vs_state
= fd3_vp_state_delete
;