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[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_program.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd3_program.h"
38 #include "fd3_emit.h"
39 #include "fd3_texture.h"
40 #include "fd3_format.h"
41
42 static void
43 delete_shader_stateobj(struct fd3_shader_stateobj *so)
44 {
45 ir3_shader_destroy(so->shader);
46 free(so);
47 }
48
49 static struct fd3_shader_stateobj *
50 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
51 enum shader_t type)
52 {
53 struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
54 struct ir3_compiler *compiler = fd_context(pctx)->screen->compiler;
55 so->shader = ir3_shader_create(compiler, cso, type);
56 return so;
57 }
58
59 static void *
60 fd3_fp_state_create(struct pipe_context *pctx,
61 const struct pipe_shader_state *cso)
62 {
63 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
64 }
65
66 static void
67 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
68 {
69 struct fd3_shader_stateobj *so = hwcso;
70 delete_shader_stateobj(so);
71 }
72
73 static void *
74 fd3_vp_state_create(struct pipe_context *pctx,
75 const struct pipe_shader_state *cso)
76 {
77 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
78 }
79
80 static void
81 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
82 {
83 struct fd3_shader_stateobj *so = hwcso;
84 delete_shader_stateobj(so);
85 }
86
87 static void
88 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
89 {
90 const struct ir3_info *si = &so->info;
91 enum adreno_state_block sb;
92 enum adreno_state_src src;
93 uint32_t i, sz, *bin;
94
95 if (so->type == SHADER_VERTEX) {
96 sb = SB_VERT_SHADER;
97 } else {
98 sb = SB_FRAG_SHADER;
99 }
100
101 if (fd_mesa_debug & FD_DBG_DIRECT) {
102 sz = si->sizedwords;
103 src = SS_DIRECT;
104 bin = fd_bo_map(so->bo);
105 } else {
106 sz = 0;
107 src = SS_INDIRECT;
108 bin = NULL;
109 }
110
111 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
113 CP_LOAD_STATE_0_STATE_SRC(src) |
114 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
115 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
116 if (bin) {
117 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
118 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
119 } else {
120 OUT_RELOC(ring, so->bo, 0,
121 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
122 }
123 for (i = 0; i < sz; i++) {
124 OUT_RING(ring, bin[i]);
125 }
126 }
127
128 void
129 fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
130 int nr, struct pipe_surface **bufs)
131 {
132 const struct ir3_shader_variant *vp, *fp;
133 const struct ir3_info *vsi, *fsi;
134 enum a3xx_instrbuffermode fpbuffer, vpbuffer;
135 uint32_t fpbuffersz, vpbuffersz, fsoff;
136 uint32_t pos_regid, posz_regid, psize_regid, color_regid[4] = {0};
137 int constmode;
138 int i, j, k;
139
140 debug_assert(nr <= ARRAY_SIZE(color_regid));
141
142 vp = fd3_emit_get_vp(emit);
143
144 if (emit->key.binning_pass) {
145 /* use dummy stateobj to simplify binning vs non-binning: */
146 static const struct ir3_shader_variant binning_fp = {};
147 fp = &binning_fp;
148 } else {
149 fp = fd3_emit_get_fp(emit);
150 }
151
152 vsi = &vp->info;
153 fsi = &fp->info;
154
155 fpbuffer = BUFFER;
156 vpbuffer = BUFFER;
157 fpbuffersz = fp->instrlen;
158 vpbuffersz = vp->instrlen;
159
160 /*
161 * Decide whether to use BUFFER or CACHE mode for VS and FS. It
162 * appears like 256 is the hard limit, but when the combined size
163 * exceeds 128 then blob will try to keep FS in BUFFER mode and
164 * switch to CACHE for VS until VS is too large. The blob seems
165 * to switch FS out of BUFFER mode at slightly under 128. But
166 * a bit fuzzy on the decision tree, so use slightly conservative
167 * limits.
168 *
169 * TODO check if these thresholds for BUFFER vs CACHE mode are the
170 * same for all a3xx or whether we need to consider the gpuid
171 */
172
173 if ((fpbuffersz + vpbuffersz) > 128) {
174 if (fpbuffersz < 112) {
175 /* FP:BUFFER VP:CACHE */
176 vpbuffer = CACHE;
177 vpbuffersz = 256 - fpbuffersz;
178 } else if (vpbuffersz < 112) {
179 /* FP:CACHE VP:BUFFER */
180 fpbuffer = CACHE;
181 fpbuffersz = 256 - vpbuffersz;
182 } else {
183 /* FP:CACHE VP:CACHE */
184 vpbuffer = fpbuffer = CACHE;
185 vpbuffersz = fpbuffersz = 192;
186 }
187 }
188
189 if (fpbuffer == BUFFER) {
190 fsoff = 128 - fpbuffersz;
191 } else {
192 fsoff = 256 - fpbuffersz;
193 }
194
195 /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
196 constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
197
198 pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
199 posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
200 psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
201 if (fp->color0_mrt) {
202 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
203 ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
204 } else {
205 color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
206 color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
207 color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
208 color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
209 }
210
211 /* adjust regids for alpha output formats. there is no alpha render
212 * format, so it's just treated like red
213 */
214 for (i = 0; i < nr; i++)
215 if (util_format_is_alpha(pipe_surface_format(bufs[i])))
216 color_regid[i] += 3;
217
218 /* we could probably divide this up into things that need to be
219 * emitted if frag-prog is dirty vs if vert-prog is dirty..
220 */
221
222 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
223 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
224 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
225 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
226 * flush some caches? I think we only need to set those
227 * bits if we have updated const or shader..
228 */
229 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
230 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
231 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
232 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
233 COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(regid(0,0)) |
234 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(regid(0,2))));
235 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
236 OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
237 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
238 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
239 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
240 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
241 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
242 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
243
244 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
245 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
246 COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
247 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
248 A3XX_SP_SP_CTRL_REG_L0MODE(0));
249
250 OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
251 OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
252
253 OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
254 OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
255 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
256 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
257 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
258 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
259 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
260 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
261 A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
262 OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
263 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
264 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
265 OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
266 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
267 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->varying_in));
268
269 for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
270 uint32_t reg = 0;
271
272 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
273
274 j = ir3_next_varying(fp, j);
275 if (j < fp->inputs_count) {
276 k = ir3_find_output(vp, fp->inputs[j].slot);
277 reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
278 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
279 }
280
281 j = ir3_next_varying(fp, j);
282 if (j < fp->inputs_count) {
283 k = ir3_find_output(vp, fp->inputs[j].slot);
284 reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
285 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
286 }
287
288 OUT_RING(ring, reg);
289 }
290
291 for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
292 uint32_t reg = 0;
293
294 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
295
296 j = ir3_next_varying(fp, j);
297 if (j < fp->inputs_count)
298 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[j].inloc);
299 j = ir3_next_varying(fp, j);
300 if (j < fp->inputs_count)
301 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[j].inloc);
302 j = ir3_next_varying(fp, j);
303 if (j < fp->inputs_count)
304 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[j].inloc);
305 j = ir3_next_varying(fp, j);
306 if (j < fp->inputs_count)
307 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[j].inloc);
308
309 OUT_RING(ring, reg);
310 }
311
312 OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
313 OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
314 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
315 OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
316
317 if (emit->key.binning_pass) {
318 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
319 OUT_RING(ring, 0x00000000);
320
321 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
322 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
323 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
324 OUT_RING(ring, 0x00000000);
325
326 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
327 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
328 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
329 } else {
330 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
331 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
332
333 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
334 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
335 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
336 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
337 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
338 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
339 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP |
340 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
341 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
342 COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
343 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
344 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
345 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
346 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
347 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
348
349 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
350 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
351 MAX2(128, vp->constlen)) |
352 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
353 OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
354 }
355
356 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
357 OUT_RING(ring,
358 COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
359 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
360 A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
361
362 OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
363 for (i = 0; i < 4; i++) {
364 uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
365 COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
366
367 if (i < nr) {
368 enum pipe_format fmt = pipe_surface_format(bufs[i]);
369 mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
370 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
371 }
372 OUT_RING(ring, mrt_reg);
373 }
374
375 if (emit->key.binning_pass) {
376 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
377 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
378 A3XX_VPC_ATTR_LMSIZE(1) |
379 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
380 OUT_RING(ring, 0x00000000);
381 } else {
382 uint32_t vinterp[4], flatshade[2], vpsrepl[4];
383
384 memset(vinterp, 0, sizeof(vinterp));
385 memset(flatshade, 0, sizeof(flatshade));
386 memset(vpsrepl, 0, sizeof(vpsrepl));
387
388 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
389 for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
390 /* NOTE: varyings are packed, so if compmask is 0xb
391 * then first, third, and fourth component occupy
392 * three consecutive varying slots:
393 */
394 unsigned compmask = fp->inputs[j].compmask;
395
396 /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
397 * instead.. rather than -8 everywhere else..
398 */
399 uint32_t inloc = fp->inputs[j].inloc - 8;
400
401 if ((fp->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
402 (fp->inputs[j].rasterflat && emit->rasterflat)) {
403 uint32_t loc = inloc;
404
405 for (i = 0; i < 4; i++) {
406 if (compmask & (1 << i)) {
407 vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
408 flatshade[loc / 32] |= 1 << (loc % 32);
409 loc++;
410 }
411 }
412 }
413
414 gl_varying_slot slot = fp->inputs[j].slot;
415
416 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
417 if (slot >= VARYING_SLOT_VAR0) {
418 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
419 /* Replace the .xy coordinates with S/T from the point sprite. Set
420 * interpolation bits for .zw such that they become .01
421 */
422 if (emit->sprite_coord_enable & texmask) {
423 /* mask is two 2-bit fields, where:
424 * '01' -> S
425 * '10' -> T
426 * '11' -> 1 - T (flip mode)
427 */
428 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
429 uint32_t loc = inloc;
430 if (compmask & 0x1) {
431 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
432 loc++;
433 }
434 if (compmask & 0x2) {
435 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
436 loc++;
437 }
438 if (compmask & 0x4) {
439 /* .z <- 0.0f */
440 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
441 loc++;
442 }
443 if (compmask & 0x8) {
444 /* .w <- 1.0f */
445 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
446 loc++;
447 }
448 }
449 }
450 }
451
452 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
453 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
454 A3XX_VPC_ATTR_THRDASSIGN(1) |
455 A3XX_VPC_ATTR_LMSIZE(1) |
456 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
457 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
458 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
459
460 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
461 OUT_RING(ring, vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
462 OUT_RING(ring, vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
463 OUT_RING(ring, vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
464 OUT_RING(ring, vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
465
466 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
467 OUT_RING(ring, vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
468 OUT_RING(ring, vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
469 OUT_RING(ring, vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
470 OUT_RING(ring, vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
471
472 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
473 OUT_RING(ring, flatshade[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
474 OUT_RING(ring, flatshade[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
475 }
476
477 if (vpbuffer == BUFFER)
478 emit_shader(ring, vp);
479
480 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
481 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
482
483 if (!emit->key.binning_pass) {
484 if (fpbuffer == BUFFER)
485 emit_shader(ring, fp);
486
487 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
488 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
489 }
490 }
491
492 void
493 fd3_prog_init(struct pipe_context *pctx)
494 {
495 pctx->create_fs_state = fd3_fp_state_create;
496 pctx->delete_fs_state = fd3_fp_state_delete;
497
498 pctx->create_vs_state = fd3_vp_state_create;
499 pctx->delete_vs_state = fd3_vp_state_delete;
500
501 fd_prog_init(pctx);
502 }