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freedreno/all: move more emit helpers to screen
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_program.c
1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd3_program.h"
37 #include "fd3_emit.h"
38 #include "fd3_texture.h"
39 #include "fd3_format.h"
40
41 static struct ir3_shader *
42 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
43 gl_shader_stage type)
44 {
45 struct fd_context *ctx = fd_context(pctx);
46 struct ir3_compiler *compiler = ctx->screen->compiler;
47 return ir3_shader_create(compiler, cso, type, &ctx->debug, pctx->screen);
48 }
49
50 static void *
51 fd3_fp_state_create(struct pipe_context *pctx,
52 const struct pipe_shader_state *cso)
53 {
54 return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
55 }
56
57 static void
58 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
59 {
60 struct ir3_shader *so = hwcso;
61 ir3_shader_destroy(so);
62 }
63
64 static void *
65 fd3_vp_state_create(struct pipe_context *pctx,
66 const struct pipe_shader_state *cso)
67 {
68 return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
69 }
70
71 static void
72 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
73 {
74 struct ir3_shader *so = hwcso;
75 ir3_shader_destroy(so);
76 }
77
78 bool
79 fd3_needs_manual_clipping(const struct ir3_shader *shader,
80 const struct pipe_rasterizer_state *rast)
81 {
82 uint64_t outputs = ir3_shader_outputs(shader);
83
84 return (!rast->depth_clip_near ||
85 util_bitcount(rast->clip_plane_enable) > 6 ||
86 outputs & ((1ULL << VARYING_SLOT_CLIP_VERTEX) |
87 (1ULL << VARYING_SLOT_CLIP_DIST0) |
88 (1ULL << VARYING_SLOT_CLIP_DIST1)));
89 }
90
91
92 static void
93 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
94 {
95 const struct ir3_info *si = &so->info;
96 enum adreno_state_block sb;
97 enum adreno_state_src src;
98 uint32_t i, sz, *bin;
99
100 if (so->type == MESA_SHADER_VERTEX) {
101 sb = SB_VERT_SHADER;
102 } else {
103 sb = SB_FRAG_SHADER;
104 }
105
106 if (fd_mesa_debug & FD_DBG_DIRECT) {
107 sz = si->sizedwords;
108 src = SS_DIRECT;
109 bin = fd_bo_map(so->bo);
110 } else {
111 sz = 0;
112 src = SS_INDIRECT;
113 bin = NULL;
114 }
115
116 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
117 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
118 CP_LOAD_STATE_0_STATE_SRC(src) |
119 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
120 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
121 if (bin) {
122 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
123 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
124 } else {
125 OUT_RELOCD(ring, so->bo, 0,
126 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
127 }
128 for (i = 0; i < sz; i++) {
129 OUT_RING(ring, bin[i]);
130 }
131 }
132
133 void
134 fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
135 int nr, struct pipe_surface **bufs)
136 {
137 const struct ir3_shader_variant *vp, *fp;
138 const struct ir3_info *vsi, *fsi;
139 enum a3xx_instrbuffermode fpbuffer, vpbuffer;
140 uint32_t fpbuffersz, vpbuffersz, fsoff;
141 uint32_t pos_regid, posz_regid, psize_regid;
142 uint32_t vcoord_regid, face_regid, coord_regid, zwcoord_regid;
143 uint32_t color_regid[4] = {0};
144 int constmode;
145 int i, j;
146
147 debug_assert(nr <= ARRAY_SIZE(color_regid));
148
149 vp = fd3_emit_get_vp(emit);
150 fp = fd3_emit_get_fp(emit);
151
152 vsi = &vp->info;
153 fsi = &fp->info;
154
155 fpbuffer = BUFFER;
156 vpbuffer = BUFFER;
157 fpbuffersz = fp->instrlen;
158 vpbuffersz = vp->instrlen;
159
160 /*
161 * Decide whether to use BUFFER or CACHE mode for VS and FS. It
162 * appears like 256 is the hard limit, but when the combined size
163 * exceeds 128 then blob will try to keep FS in BUFFER mode and
164 * switch to CACHE for VS until VS is too large. The blob seems
165 * to switch FS out of BUFFER mode at slightly under 128. But
166 * a bit fuzzy on the decision tree, so use slightly conservative
167 * limits.
168 *
169 * TODO check if these thresholds for BUFFER vs CACHE mode are the
170 * same for all a3xx or whether we need to consider the gpuid
171 */
172
173 if ((fpbuffersz + vpbuffersz) > 128) {
174 if (fpbuffersz < 112) {
175 /* FP:BUFFER VP:CACHE */
176 vpbuffer = CACHE;
177 vpbuffersz = 256 - fpbuffersz;
178 } else if (vpbuffersz < 112) {
179 /* FP:CACHE VP:BUFFER */
180 fpbuffer = CACHE;
181 fpbuffersz = 256 - vpbuffersz;
182 } else {
183 /* FP:CACHE VP:CACHE */
184 vpbuffer = fpbuffer = CACHE;
185 vpbuffersz = fpbuffersz = 192;
186 }
187 }
188
189 if (fpbuffer == BUFFER) {
190 fsoff = 128 - fpbuffersz;
191 } else {
192 fsoff = 256 - fpbuffersz;
193 }
194
195 /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
196 constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
197
198 pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
199 posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
200 psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
201 if (fp->color0_mrt) {
202 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
203 ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
204 } else {
205 color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
206 color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
207 color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
208 color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
209 }
210
211 face_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRONT_FACE);
212 coord_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD);
213 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
214 vcoord_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
215
216 /* adjust regids for alpha output formats. there is no alpha render
217 * format, so it's just treated like red
218 */
219 for (i = 0; i < nr; i++)
220 if (util_format_is_alpha(pipe_surface_format(bufs[i])))
221 color_regid[i] += 3;
222
223 /* we could probably divide this up into things that need to be
224 * emitted if frag-prog is dirty vs if vert-prog is dirty..
225 */
226
227 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
228 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
229 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
230 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
231 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
232 * flush some caches? I think we only need to set those
233 * bits if we have updated const or shader..
234 */
235 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
236 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
237 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
238 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
239 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(coord_regid) |
240 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(zwcoord_regid));
241 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31) |
242 A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(face_regid));
243 OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(vcoord_regid));
244 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
245 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
246 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
247 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
248 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
249 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
250
251 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
252 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
253 COND(emit->binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
254 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
255 A3XX_SP_SP_CTRL_REG_L0MODE(0));
256
257 OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
258 OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
259
260 OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
261 OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
262 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
263 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
264 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
265 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
266 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
267 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
268 A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
269 OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
270 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
271 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
272 OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
273 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
274 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->varying_in));
275
276 struct ir3_shader_linkage l = {0};
277 ir3_link_shaders(&l, vp, fp);
278
279 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
280 uint32_t reg = 0;
281
282 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
283
284 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
285 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
286 j++;
287
288 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
289 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
290 j++;
291
292 OUT_RING(ring, reg);
293 }
294
295 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
296 uint32_t reg = 0;
297
298 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
299
300 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
301 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
302 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
303 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
304
305 OUT_RING(ring, reg);
306 }
307
308 OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
309 OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
310 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
311 OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
312
313 if (emit->binning_pass) {
314 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
315 OUT_RING(ring, 0x00000000);
316
317 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
318 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
319 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
320 OUT_RING(ring, 0x00000000);
321
322 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
323 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
324 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
325 } else {
326 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
327 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
328
329 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
330 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
331 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
332 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
333 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
334 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
335 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP |
336 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
337 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
338 COND(fp->num_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
339 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
340 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
341 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
342 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
343 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
344
345 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
346 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
347 MAX2(128, vp->constlen)) |
348 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
349 OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
350 }
351
352 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
353 OUT_RING(ring,
354 COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
355 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
356 A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
357
358 OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
359 for (i = 0; i < 4; i++) {
360 uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
361 COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
362
363 if (i < nr) {
364 enum pipe_format fmt = pipe_surface_format(bufs[i]);
365 mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
366 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
367 }
368 OUT_RING(ring, mrt_reg);
369 }
370
371 if (emit->binning_pass) {
372 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
373 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
374 A3XX_VPC_ATTR_LMSIZE(1) |
375 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
376 OUT_RING(ring, 0x00000000);
377 } else {
378 uint32_t vinterp[4], flatshade[2], vpsrepl[4];
379
380 memset(vinterp, 0, sizeof(vinterp));
381 memset(flatshade, 0, sizeof(flatshade));
382 memset(vpsrepl, 0, sizeof(vpsrepl));
383
384 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
385 for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
386 /* NOTE: varyings are packed, so if compmask is 0xb
387 * then first, third, and fourth component occupy
388 * three consecutive varying slots:
389 */
390 unsigned compmask = fp->inputs[j].compmask;
391
392 uint32_t inloc = fp->inputs[j].inloc;
393
394 if ((fp->inputs[j].interpolate == INTERP_MODE_FLAT) ||
395 (fp->inputs[j].rasterflat && emit->rasterflat)) {
396 uint32_t loc = inloc;
397
398 for (i = 0; i < 4; i++) {
399 if (compmask & (1 << i)) {
400 vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
401 flatshade[loc / 32] |= 1 << (loc % 32);
402 loc++;
403 }
404 }
405 }
406
407 gl_varying_slot slot = fp->inputs[j].slot;
408
409 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
410 if (slot >= VARYING_SLOT_VAR0) {
411 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
412 /* Replace the .xy coordinates with S/T from the point sprite. Set
413 * interpolation bits for .zw such that they become .01
414 */
415 if (emit->sprite_coord_enable & texmask) {
416 /* mask is two 2-bit fields, where:
417 * '01' -> S
418 * '10' -> T
419 * '11' -> 1 - T (flip mode)
420 */
421 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
422 uint32_t loc = inloc;
423 if (compmask & 0x1) {
424 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
425 loc++;
426 }
427 if (compmask & 0x2) {
428 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
429 loc++;
430 }
431 if (compmask & 0x4) {
432 /* .z <- 0.0f */
433 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
434 loc++;
435 }
436 if (compmask & 0x8) {
437 /* .w <- 1.0f */
438 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
439 loc++;
440 }
441 }
442 }
443 }
444
445 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
446 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
447 A3XX_VPC_ATTR_THRDASSIGN(1) |
448 A3XX_VPC_ATTR_LMSIZE(1) |
449 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
450 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
451 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
452
453 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
454 OUT_RING(ring, vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
455 OUT_RING(ring, vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
456 OUT_RING(ring, vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
457 OUT_RING(ring, vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
458
459 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
460 OUT_RING(ring, vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
461 OUT_RING(ring, vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
462 OUT_RING(ring, vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
463 OUT_RING(ring, vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
464
465 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
466 OUT_RING(ring, flatshade[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
467 OUT_RING(ring, flatshade[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
468 }
469
470 if (vpbuffer == BUFFER)
471 emit_shader(ring, vp);
472
473 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
474 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
475
476 if (!emit->binning_pass) {
477 if (fpbuffer == BUFFER)
478 emit_shader(ring, fp);
479
480 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
481 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
482 }
483 }
484
485 void
486 fd3_prog_init(struct pipe_context *pctx)
487 {
488 pctx->create_fs_state = fd3_fp_state_create;
489 pctx->delete_fs_state = fd3_fp_state_delete;
490
491 pctx->create_vs_state = fd3_vp_state_create;
492 pctx->delete_vs_state = fd3_vp_state_delete;
493
494 fd_prog_init(pctx);
495 }