src/gallium/drivers/freedreno/a3xx/fd3_program.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34 #include "tgsi/tgsi_dump.h"
  35 #include "tgsi/tgsi_parse.h"
  36
  37 #include "freedreno_program.h"
  38
  39 #include "fd3_program.h"
  40 #include "fd3_emit.h"
  41 #include "fd3_texture.h"
  42 #include "fd3_format.h"
  43
  44 static void
  45 delete_shader_stateobj(struct fd3_shader_stateobj *so)
  46 {
  47         ir3_shader_destroy(so->shader);
  48         free(so);
  49 }
  50
  51 static struct fd3_shader_stateobj *
  52 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
  53                 enum shader_t type)
  54 {
  55         struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
  56         so->shader = ir3_shader_create(pctx, cso->tokens, type);
  57         return so;
  58 }
  59
  60 static void *
  61 fd3_fp_state_create(struct pipe_context *pctx,
  62                 const struct pipe_shader_state *cso)
  63 {
  64         return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
  65 }
  66
  67 static void
  68 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
  69 {
  70         struct fd3_shader_stateobj *so = hwcso;
  71         delete_shader_stateobj(so);
  72 }
  73
  74 static void *
  75 fd3_vp_state_create(struct pipe_context *pctx,
  76                 const struct pipe_shader_state *cso)
  77 {
  78         return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
  79 }
  80
  81 static void
  82 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
  83 {
  84         struct fd3_shader_stateobj *so = hwcso;
  85         delete_shader_stateobj(so);
  86 }
  87
  88 static void
  89 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
  90 {
  91         const struct ir3_info *si = &so->info;
  92         enum adreno_state_block sb;
  93         enum adreno_state_src src;
  94         uint32_t i, sz, *bin;
  95
  96         if (so->type == SHADER_VERTEX) {
  97                 sb = SB_VERT_SHADER;
  98         } else {
  99                 sb = SB_FRAG_SHADER;
 100         }
 101
 102         if (fd_mesa_debug & FD_DBG_DIRECT) {
 103                 sz = si->sizedwords;
 104                 src = SS_DIRECT;
 105                 bin = fd_bo_map(so->bo);
 106         } else {
 107                 sz = 0;
 108                 src = SS_INDIRECT;
 109                 bin = NULL;
 110         }
 111
 112         OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
 113         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
 114                         CP_LOAD_STATE_0_STATE_SRC(src) |
 115                         CP_LOAD_STATE_0_STATE_BLOCK(sb) |
 116                         CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
 117         if (bin) {
 118                 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
 119                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
 120         } else {
 121                 OUT_RELOC(ring, so->bo, 0,
 122                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
 123         }
 124         for (i = 0; i < sz; i++) {
 125                 OUT_RING(ring, bin[i]);
 126         }
 127 }
 128
 129 void
 130 fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit)
 131 {
 132         const struct ir3_shader_variant *vp, *fp;
 133         const struct ir3_info *vsi, *fsi;
 134         enum a3xx_instrbuffermode fpbuffer, vpbuffer;
 135         uint32_t fpbuffersz, vpbuffersz, fsoff;
 136         uint32_t pos_regid, posz_regid, psize_regid, color_regid;
 137         int constmode;
 138         int i, j, k;
 139
 140         vp = fd3_emit_get_vp(emit);
 141
 142         if (emit->key.binning_pass) {
 143                 /* use dummy stateobj to simplify binning vs non-binning: */
 144                 static const struct ir3_shader_variant binning_fp = {};
 145                 fp = &binning_fp;
 146         } else {
 147                 fp = fd3_emit_get_fp(emit);
 148         }
 149
 150         vsi = &vp->info;
 151         fsi = &fp->info;
 152
 153         fpbuffer = BUFFER;
 154         vpbuffer = BUFFER;
 155         fpbuffersz = fp->instrlen;
 156         vpbuffersz = vp->instrlen;
 157
 158         /*
 159          * Decide whether to use BUFFER or CACHE mode for VS and FS.  It
 160          * appears like 256 is the hard limit, but when the combined size
 161          * exceeds 128 then blob will try to keep FS in BUFFER mode and
 162          * switch to CACHE for VS until VS is too large.  The blob seems
 163          * to switch FS out of BUFFER mode at slightly under 128.  But
 164          * a bit fuzzy on the decision tree, so use slightly conservative
 165          * limits.
 166          *
 167          * TODO check if these thresholds for BUFFER vs CACHE mode are the
 168          *      same for all a3xx or whether we need to consider the gpuid
 169          */
 170
 171         if ((fpbuffersz + vpbuffersz) > 128) {
 172                 if (fpbuffersz < 112) {
 173                         /* FP:BUFFER   VP:CACHE  */
 174                         vpbuffer = CACHE;
 175                         vpbuffersz = 256 - fpbuffersz;
 176                 } else if (vpbuffersz < 112) {
 177                         /* FP:CACHE    VP:BUFFER */
 178                         fpbuffer = CACHE;
 179                         fpbuffersz = 256 - vpbuffersz;
 180                 } else {
 181                         /* FP:CACHE    VP:CACHE  */
 182                         vpbuffer = fpbuffer = CACHE;
 183                         vpbuffersz = fpbuffersz = 192;
 184                 }
 185         }
 186
 187         if (fpbuffer == BUFFER) {
 188                 fsoff = 128 - fpbuffersz;
 189         } else {
 190                 fsoff = 256 - fpbuffersz;
 191         }
 192
 193         /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
 194         constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
 195
 196         pos_regid = ir3_find_output_regid(vp,
 197                 ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
 198         posz_regid = ir3_find_output_regid(fp,
 199                 ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
 200         psize_regid = ir3_find_output_regid(vp,
 201                 ir3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
 202         color_regid = ir3_find_output_regid(fp,
 203                 ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
 204
 205         /* we could probably divide this up into things that need to be
 206          * emitted if frag-prog is dirty vs if vert-prog is dirty..
 207          */
 208
 209         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
 210         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
 211                         A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
 212                         /* NOTE:  I guess SHADERRESTART and CONSTFULLUPDATE maybe
 213                          * flush some caches? I think we only need to set those
 214                          * bits if we have updated const or shader..
 215                          */
 216                         A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
 217                         A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
 218         OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
 219                         A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
 220                         COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_ZWCOORD));
 221         OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
 222         OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
 223         OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
 224                         A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
 225                         A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
 226         OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
 227                         A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
 228                         A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
 229
 230         OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
 231         OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
 232                         COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
 233                         A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
 234                         A3XX_SP_SP_CTRL_REG_L0MODE(0));
 235
 236         OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
 237         OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
 238
 239         OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
 240         OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
 241                         A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
 242                         COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
 243                         A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
 244                         A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
 245                         A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
 246                         A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
 247                         A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
 248                         COND(vp->has_samp, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
 249                         A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
 250         OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
 251                         A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
 252                         A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
 253         OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
 254                         A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
 255                         A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp->total_in, 4) / 4));
 256
 257         for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
 258                 uint32_t reg = 0;
 259
 260                 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
 261
 262                 j = ir3_next_varying(fp, j);
 263                 if (j < fp->inputs_count) {
 264                         k = ir3_find_output(vp, fp->inputs[j].semantic);
 265                         reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
 266                         reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
 267                 }
 268
 269                 j = ir3_next_varying(fp, j);
 270                 if (j < fp->inputs_count) {
 271                         k = ir3_find_output(vp, fp->inputs[j].semantic);
 272                         reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
 273                         reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
 274                 }
 275
 276                 OUT_RING(ring, reg);
 277         }
 278
 279         for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
 280                 uint32_t reg = 0;
 281
 282                 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
 283
 284                 j = ir3_next_varying(fp, j);
 285                 if (j < fp->inputs_count)
 286                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[j].inloc);
 287                 j = ir3_next_varying(fp, j);
 288                 if (j < fp->inputs_count)
 289                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[j].inloc);
 290                 j = ir3_next_varying(fp, j);
 291                 if (j < fp->inputs_count)
 292                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[j].inloc);
 293                 j = ir3_next_varying(fp, j);
 294                 if (j < fp->inputs_count)
 295                         reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[j].inloc);
 296
 297                 OUT_RING(ring, reg);
 298         }
 299
 300         OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
 301         OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
 302                         A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 303         OUT_RELOC(ring, vp->bo, 0, 0, 0);  /* SP_VS_OBJ_START_REG */
 304
 305         if (emit->key.binning_pass) {
 306                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 307                 OUT_RING(ring, 0x00000000);
 308
 309                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 310                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 311                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
 312                 OUT_RING(ring, 0x00000000);
 313
 314                 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
 315                 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
 316                                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 317         } else {
 318                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 319                 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
 320
 321                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 322                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 323                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
 324                                 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
 325                                 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
 326                                 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
 327                                 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
 328                                 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 329                                 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
 330                                 COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
 331                                 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
 332                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
 333                                 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
 334                                 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
 335                                 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
 336
 337                 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
 338                 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
 339                                         MAX2(128, vp->constlen)) |
 340                                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
 341                 OUT_RELOC(ring, fp->bo, 0, 0, 0);  /* SP_FS_OBJ_START_REG */
 342         }
 343
 344         OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
 345         if (fp->writes_pos) {
 346                 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE |
 347                                 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
 348         } else {
 349                 OUT_RING(ring, 0x00000000);
 350         }
 351
 352         OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
 353         OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(color_regid) |
 354                         COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION));
 355         OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
 356         OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
 357         OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
 358
 359         if (emit->key.binning_pass) {
 360                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 361                 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
 362                                 A3XX_VPC_ATTR_LMSIZE(1) |
 363                                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
 364                 OUT_RING(ring, 0x00000000);
 365         } else {
 366                 uint32_t vinterp[4] = {0}, flatshade[2] = {0};
 367
 368                 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
 369                 for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
 370                         uint32_t interp = fp->inputs[j].interpolate;
 371                         if ((interp == TGSI_INTERPOLATE_CONSTANT) ||
 372                                         ((interp == TGSI_INTERPOLATE_COLOR) && emit->rasterflat)) {
 373                                 /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
 374                                  * instead.. rather than -8 everywhere else..
 375                                  */
 376                                 uint32_t loc = fp->inputs[j].inloc - 8;
 377
 378                                 /* currently assuming varyings aligned to 4 (not
 379                                  * packed):
 380                                  */
 381                                 debug_assert((loc % 4) == 0);
 382
 383                                 for (i = 0; i < 4; i++, loc++) {
 384                                         vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
 385                                         flatshade[loc / 32] |= 1 << (loc % 32);
 386                                 }
 387                         }
 388                 }
 389
 390                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 391                 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
 392                                 A3XX_VPC_ATTR_THRDASSIGN(1) |
 393                                 A3XX_VPC_ATTR_LMSIZE(1) |
 394                                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
 395                 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
 396                                 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
 397
 398                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
 399                 OUT_RING(ring, vinterp[0]);    /* VPC_VARYING_INTERP[0].MODE */
 400                 OUT_RING(ring, vinterp[1]);    /* VPC_VARYING_INTERP[1].MODE */
 401                 OUT_RING(ring, vinterp[2]);    /* VPC_VARYING_INTERP[2].MODE */
 402                 OUT_RING(ring, vinterp[3]);    /* VPC_VARYING_INTERP[3].MODE */
 403
 404                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
 405                 OUT_RING(ring, fp->shader->vpsrepl[0]);    /* VPC_VARYING_PS_REPL[0].MODE */
 406                 OUT_RING(ring, fp->shader->vpsrepl[1]);    /* VPC_VARYING_PS_REPL[1].MODE */
 407                 OUT_RING(ring, fp->shader->vpsrepl[2]);    /* VPC_VARYING_PS_REPL[2].MODE */
 408                 OUT_RING(ring, fp->shader->vpsrepl[3]);    /* VPC_VARYING_PS_REPL[3].MODE */
 409
 410                 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
 411                 OUT_RING(ring, flatshade[0]);        /* SP_FS_FLAT_SHAD_MODE_REG_0 */
 412                 OUT_RING(ring, flatshade[1]);        /* SP_FS_FLAT_SHAD_MODE_REG_1 */
 413         }
 414
 415         OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
 416         OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
 417                         A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
 418
 419         if (vpbuffer == BUFFER)
 420                 emit_shader(ring, vp);
 421
 422         OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 423         OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 424
 425         if (!emit->key.binning_pass) {
 426                 if (fpbuffer == BUFFER)
 427                         emit_shader(ring, fp);
 428
 429                 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 430                 OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 431         }
 432 }
 433
 434 /* hack.. until we figure out how to deal w/ vpsrepl properly.. */
 435 static void
 436 fix_blit_fp(struct pipe_context *pctx)
 437 {
 438         struct fd_context *ctx = fd_context(pctx);
 439         struct fd3_shader_stateobj *so = ctx->blit_prog.fp;
 440
 441         so->shader->vpsrepl[0] = 0x99999999;
 442         so->shader->vpsrepl[1] = 0x99999999;
 443         so->shader->vpsrepl[2] = 0x99999999;
 444         so->shader->vpsrepl[3] = 0x99999999;
 445 }
 446
 447 void
 448 fd3_prog_init(struct pipe_context *pctx)
 449 {
 450         pctx->create_fs_state = fd3_fp_state_create;
 451         pctx->delete_fs_state = fd3_fp_state_delete;
 452
 453         pctx->create_vs_state = fd3_vp_state_create;
 454         pctx->delete_vs_state = fd3_vp_state_delete;
 455
 456         fd_prog_init(pctx);
 457
 458         fix_blit_fp(pctx);
 459 }