src/gallium/drivers/freedreno/a3xx/fd3_program.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_format.h"
  34 #include "tgsi/tgsi_dump.h"
  35 #include "tgsi/tgsi_parse.h"
  36
  37 #include "freedreno_lowering.h"
  38
  39 #include "fd3_program.h"
  40 #include "fd3_compiler.h"
  41 #include "fd3_emit.h"
  42 #include "fd3_texture.h"
  43 #include "fd3_util.h"
  44
  45 static void
  46 delete_shader(struct fd3_shader_stateobj *so)
  47 {
  48         ir3_shader_destroy(so->ir);
  49         fd_bo_del(so->bo);
  50         free(so);
  51 }
  52
  53 static void
  54 assemble_shader(struct pipe_context *pctx, struct fd3_shader_stateobj *so)
  55 {
  56         struct fd_context *ctx = fd_context(pctx);
  57         uint32_t sz, *bin;
  58
  59         bin = ir3_shader_assemble(so->ir, &so->info);
  60         sz = so->info.sizedwords * 4;
  61
  62         so->bo = fd_bo_new(ctx->dev, sz,
  63                         DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
  64                         DRM_FREEDRENO_GEM_TYPE_KMEM);
  65
  66         memcpy(fd_bo_map(so->bo), bin, sz);
  67
  68         free(bin);
  69
  70         so->instrlen = so->info.sizedwords / 8;
  71         so->constlen = so->info.max_const + 1;
  72 }
  73
  74 /* for vertex shader, the inputs are loaded into registers before the shader
  75  * is executed, so max_regs from the shader instructions might not properly
  76  * reflect the # of registers actually used:
  77  */
  78 static void
  79 fixup_vp_regfootprint(struct fd3_shader_stateobj *so)
  80 {
  81         unsigned i;
  82         for (i = 0; i < so->inputs_count; i++)
  83                 so->info.max_reg = MAX2(so->info.max_reg, so->inputs[i].regid >> 2);
  84         for (i = 0; i < so->outputs_count; i++)
  85                 so->info.max_reg = MAX2(so->info.max_reg, so->outputs[i].regid >> 2);
  86 }
  87
  88 static struct fd3_shader_stateobj *
  89 create_shader(struct pipe_context *pctx, const struct pipe_shader_state *cso,
  90                 enum shader_t type)
  91 {
  92         struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
  93         const struct tgsi_token *tokens = fd_transform_lowering(cso->tokens);
  94         int ret;
  95
  96         if (!so)
  97                 return NULL;
  98
  99         so->type = type;
 100
 101         if (fd_mesa_debug & FD_DBG_DISASM) {
 102                 DBG("dump tgsi: type=%d", so->type);
 103                 tgsi_dump(tokens, 0);
 104         }
 105
 106         if ((type == SHADER_FRAGMENT) && (fd_mesa_debug & FD_DBG_FRAGHALF))
 107                 so->half_precision = true;
 108
 109
 110         if (fd_mesa_debug & FD_DBG_OPTIMIZE) {
 111                 ret = fd3_compile_shader(so, tokens);
 112                 if (ret) {
 113                         debug_error("new compiler failed, trying fallback!");
 114
 115                         so->inputs_count = 0;
 116                         so->outputs_count = 0;
 117                         so->total_in = 0;
 118                         so->samplers_count = 0;
 119                         so->immediates_count = 0;
 120                 }
 121         } else {
 122                 ret = -1;  /* force fallback to old compiler */
 123         }
 124
 125         if (ret)
 126                 ret = fd3_compile_shader_old(so, tokens);
 127
 128         if (ret) {
 129                 debug_error("compile failed!");
 130                 goto fail;
 131         }
 132
 133         assemble_shader(pctx, so);
 134         if (!so->bo) {
 135                 debug_error("assemble failed!");
 136                 goto fail;
 137         }
 138
 139         if (type == SHADER_VERTEX)
 140                 fixup_vp_regfootprint(so);
 141
 142         if (fd_mesa_debug & FD_DBG_DISASM) {
 143                 DBG("disassemble: type=%d", so->type);
 144                 disasm_a3xx(fd_bo_map(so->bo), so->info.sizedwords, 0, so->type);
 145         }
 146
 147         return so;
 148
 149 fail:
 150         delete_shader(so);
 151         return NULL;
 152 }
 153
 154 static void *
 155 fd3_fp_state_create(struct pipe_context *pctx,
 156                 const struct pipe_shader_state *cso)
 157 {
 158         return create_shader(pctx, cso, SHADER_FRAGMENT);
 159 }
 160
 161 static void
 162 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
 163 {
 164         struct fd3_shader_stateobj *so = hwcso;
 165         delete_shader(so);
 166 }
 167
 168 static void
 169 fd3_fp_state_bind(struct pipe_context *pctx, void *hwcso)
 170 {
 171         struct fd_context *ctx = fd_context(pctx);
 172         ctx->prog.fp = hwcso;
 173         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 174         ctx->dirty |= FD_DIRTY_PROG;
 175 }
 176
 177 static void *
 178 fd3_vp_state_create(struct pipe_context *pctx,
 179                 const struct pipe_shader_state *cso)
 180 {
 181         return create_shader(pctx, cso, SHADER_VERTEX);
 182 }
 183
 184 static void
 185 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
 186 {
 187         struct fd3_shader_stateobj *so = hwcso;
 188         delete_shader(so);
 189 }
 190
 191 static void
 192 fd3_vp_state_bind(struct pipe_context *pctx, void *hwcso)
 193 {
 194         struct fd_context *ctx = fd_context(pctx);
 195         ctx->prog.vp = hwcso;
 196         ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
 197         ctx->dirty |= FD_DIRTY_PROG;
 198 }
 199
 200 static void
 201 emit_shader(struct fd_ringbuffer *ring, const struct fd3_shader_stateobj *so)
 202 {
 203         const struct ir3_shader_info *si = &so->info;
 204         enum adreno_state_block sb;
 205         enum adreno_state_src src;
 206         uint32_t i, sz, *bin;
 207
 208         if (so->type == SHADER_VERTEX) {
 209                 sb = SB_VERT_SHADER;
 210         } else {
 211                 sb = SB_FRAG_SHADER;
 212         }
 213
 214         if (fd_mesa_debug & FD_DBG_DIRECT) {
 215                 sz = si->sizedwords;
 216                 src = SS_DIRECT;
 217                 bin = fd_bo_map(so->bo);
 218         } else {
 219                 sz = 0;
 220                 src = SS_INDIRECT;
 221                 bin = NULL;
 222         }
 223
 224         OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
 225         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
 226                         CP_LOAD_STATE_0_STATE_SRC(src) |
 227                         CP_LOAD_STATE_0_STATE_BLOCK(sb) |
 228                         CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
 229         if (bin) {
 230                 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
 231                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
 232         } else {
 233                 OUT_RELOC(ring, so->bo, 0,
 234                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
 235         }
 236         for (i = 0; i < sz; i++) {
 237                 OUT_RING(ring, bin[i]);
 238         }
 239 }
 240
 241 static int
 242 find_output(const struct fd3_shader_stateobj *so, fd3_semantic semantic)
 243 {
 244         int j;
 245         for (j = 0; j < so->outputs_count; j++)
 246                 if (so->outputs[j].semantic == semantic)
 247                         return j;
 248         return 0;
 249 }
 250
 251 static uint32_t
 252 find_output_regid(const struct fd3_shader_stateobj *so, fd3_semantic semantic)
 253 {
 254         int j;
 255         for (j = 0; j < so->outputs_count; j++)
 256                 if (so->outputs[j].semantic == semantic)
 257                         return so->outputs[j].regid;
 258         return regid(63, 0);
 259 }
 260
 261 void
 262 fd3_program_emit(struct fd_ringbuffer *ring,
 263                 struct fd_program_stateobj *prog, bool binning)
 264 {
 265         const struct fd3_shader_stateobj *vp = prog->vp;
 266         const struct fd3_shader_stateobj *fp = prog->fp;
 267         const struct ir3_shader_info *vsi = &vp->info;
 268         const struct ir3_shader_info *fsi = &fp->info;
 269         uint32_t pos_regid, posz_regid, psize_regid, color_regid;
 270         int i;
 271
 272         if (binning) {
 273                 /* use dummy stateobj to simplify binning vs non-binning: */
 274                 static const struct fd3_shader_stateobj binning_fp = {};
 275                 fp = &binning_fp;
 276                 fsi = &fp->info;
 277         }
 278
 279         pos_regid = find_output_regid(vp,
 280                 fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
 281         posz_regid = find_output_regid(fp,
 282                 fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
 283         psize_regid = find_output_regid(vp,
 284                 fd3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
 285         color_regid = find_output_regid(fp,
 286                 fd3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
 287
 288         /* we could probably divide this up into things that need to be
 289          * emitted if frag-prog is dirty vs if vert-prog is dirty..
 290          */
 291
 292         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
 293         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
 294                         /* NOTE:  I guess SHADERRESTART and CONSTFULLUPDATE maybe
 295                          * flush some caches? I think we only need to set those
 296                          * bits if we have updated const or shader..
 297                          */
 298                         A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
 299                         A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
 300         OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
 301                         A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
 302         OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
 303         OUT_RING(ring, 0x00000000);        /* HLSQ_CONTROL_3_REG */
 304         OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
 305                         A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
 306                         A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vp->instrlen));
 307         OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
 308                         A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
 309                         A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fp->instrlen));
 310
 311         OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
 312         OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(0) |
 313                         COND(binning, A3XX_SP_SP_CTRL_REG_BINNING) |
 314                         A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
 315                         A3XX_SP_SP_CTRL_REG_L0MODE(0));
 316
 317         OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
 318         OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
 319
 320         OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
 321         OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
 322                         A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
 323                         A3XX_SP_VS_CTRL_REG0_CACHEINVALID |
 324                         A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
 325                         A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
 326                         A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
 327                         A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
 328                         A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
 329                         COND(vp->samplers_count > 0, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
 330                         A3XX_SP_VS_CTRL_REG0_LENGTH(vp->instrlen));
 331         OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
 332                         A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
 333                         A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vsi->max_const, 0)));
 334         OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
 335                         A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
 336                         A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->inputs_count));
 337
 338         for (i = 0; i < fp->inputs_count; ) {
 339                 uint32_t reg = 0;
 340                 int j;
 341
 342                 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i/2), 1);
 343
 344                 j = find_output(vp, fp->inputs[i].semantic);
 345                 reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[j].regid);
 346                 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[i].compmask);
 347                 i++;
 348
 349                 j = find_output(vp, fp->inputs[i].semantic);
 350                 reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[j].regid);
 351                 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[i].compmask);
 352                 i++;
 353
 354                 OUT_RING(ring, reg);
 355         }
 356
 357         for (i = 0; i < fp->inputs_count; ) {
 358                 uint32_t reg = 0;
 359
 360                 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i/4), 1);
 361
 362                 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[i++].inloc);
 363                 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[i++].inloc);
 364                 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[i++].inloc);
 365                 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[i++].inloc);
 366
 367                 OUT_RING(ring, reg);
 368         }
 369
 370         OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
 371         OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
 372                         A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 373         OUT_RELOC(ring, vp->bo, 0, 0, 0);  /* SP_VS_OBJ_START_REG */
 374
 375         if (binning) {
 376                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 377                 OUT_RING(ring, 0x00000000);
 378
 379                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 380                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 381                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
 382                 OUT_RING(ring, 0x00000000);
 383         } else {
 384                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 385                 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
 386
 387                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 388                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 389                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
 390                                 A3XX_SP_FS_CTRL_REG0_CACHEINVALID |
 391                                 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
 392                                 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
 393                                 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
 394                                 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 395                                 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
 396                                 COND(fp->samplers_count > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
 397                                 A3XX_SP_FS_CTRL_REG0_LENGTH(fp->instrlen));
 398                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
 399                                 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
 400                                 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fsi->max_const, 0)) |
 401                                 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
 402                 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
 403                 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
 404                                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 405                 OUT_RELOC(ring, fp->bo, 0, 0, 0);  /* SP_FS_OBJ_START_REG */
 406         }
 407
 408         OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
 409         OUT_RING(ring, 0x00000000);        /* SP_FS_FLAT_SHAD_MODE_REG_0 */
 410         OUT_RING(ring, 0x00000000);        /* SP_FS_FLAT_SHAD_MODE_REG_1 */
 411
 412         OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
 413         if (fp->writes_pos) {
 414                 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE |
 415                                 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
 416         } else {
 417                 OUT_RING(ring, 0x00000000);
 418         }
 419
 420         OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
 421         OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(color_regid) |
 422                         COND(fp->half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION));
 423         OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
 424         OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
 425         OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
 426
 427         if (binning) {
 428                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 429                 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
 430                                 A3XX_VPC_ATTR_LMSIZE(1));
 431                 OUT_RING(ring, 0x00000000);
 432         } else {
 433                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 434                 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
 435                                 A3XX_VPC_ATTR_THRDASSIGN(1) |
 436                                 A3XX_VPC_ATTR_LMSIZE(1));
 437                 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
 438                                 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
 439
 440                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
 441                 OUT_RING(ring, fp->vinterp[0]);    /* VPC_VARYING_INTERP[0].MODE */
 442                 OUT_RING(ring, fp->vinterp[1]);    /* VPC_VARYING_INTERP[1].MODE */
 443                 OUT_RING(ring, fp->vinterp[2]);    /* VPC_VARYING_INTERP[2].MODE */
 444                 OUT_RING(ring, fp->vinterp[3]);    /* VPC_VARYING_INTERP[3].MODE */
 445
 446                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
 447                 OUT_RING(ring, fp->vpsrepl[0]);    /* VPC_VARYING_PS_REPL[0].MODE */
 448                 OUT_RING(ring, fp->vpsrepl[1]);    /* VPC_VARYING_PS_REPL[1].MODE */
 449                 OUT_RING(ring, fp->vpsrepl[2]);    /* VPC_VARYING_PS_REPL[2].MODE */
 450                 OUT_RING(ring, fp->vpsrepl[3]);    /* VPC_VARYING_PS_REPL[3].MODE */
 451         }
 452
 453         OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
 454         OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
 455                         A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
 456
 457         emit_shader(ring, vp);
 458
 459         OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 460         OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 461
 462         if (!binning) {
 463                 emit_shader(ring, fp);
 464
 465                 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 466                 OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 467         }
 468
 469         OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
 470         OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(vp->total_in) |
 471                         A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
 472                         A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(vp->inputs_count) |
 473                         A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(vp->inputs_count));
 474         OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
 475                         A3XX_VFD_CONTROL_1_REGID4VTX(regid(63,0)) |
 476                         A3XX_VFD_CONTROL_1_REGID4INST(regid(63,0)));
 477 }
 478
 479 /* once the compiler is good enough, we should construct TGSI in the
 480  * core freedreno driver, and then let the a2xx/a3xx parts compile
 481  * the internal shaders from TGSI the same as regular shaders.  This
 482  * would be the first step towards handling most of clear (and the
 483  * gmem<->mem blits) from the core via normal state changes and shader
 484  * state objects.
 485  *
 486  * (Well, there would still be some special bits, because there are
 487  * some registers that don't get set for normal draw, but this should
 488  * be relatively small and could be handled via callbacks from core
 489  * into a2xx/a3xx..)
 490  */
 491 static struct fd3_shader_stateobj *
 492 create_internal_shader(struct pipe_context *pctx, enum shader_t type,
 493                 struct ir3_shader *ir)
 494 {
 495         struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
 496
 497         if (!so) {
 498                 ir3_shader_destroy(ir);
 499                 return NULL;
 500         }
 501
 502         so->type = type;
 503         so->ir = ir;
 504
 505         assemble_shader(pctx, so);
 506         assert(so->bo);
 507
 508         return so;
 509 }
 510
 511 /* Creates shader:
 512  *    (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)0, r0.x
 513  *    (rpt5)nop
 514  *    sam (f32)(xyzw)r0.x, r0.z, s#0, t#0
 515  *    (sy)(rpt3)cov.f32f16 hr0.x, (r)r0.x
 516  *    end
 517  */
 518 static struct fd3_shader_stateobj *
 519 create_blit_fp(struct pipe_context *pctx)
 520 {
 521         struct fd3_shader_stateobj *so;
 522         struct ir3_shader *ir = ir3_shader_create();
 523         struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
 524         struct ir3_instruction *instr;
 525
 526         /* (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)0, r0.x */
 527         instr = ir3_instr_create(block, 2, OPC_BARY_F);
 528         instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
 529         instr->repeat = 1;
 530
 531         ir3_reg_create(instr, regid(0,2), IR3_REG_EI);    /* (ei)r0.z */
 532         ir3_reg_create(instr, 0, IR3_REG_R |              /* (r)0 */
 533                         IR3_REG_IMMED)->iim_val = 0;
 534         ir3_reg_create(instr, regid(0,0), 0);             /* r0.x */
 535
 536         /* (rpt5)nop */
 537         instr = ir3_instr_create(block, 0, OPC_NOP);
 538         instr->repeat = 5;
 539
 540         /* sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 */
 541         instr = ir3_instr_create(block, 5, OPC_SAM);
 542         instr->cat5.samp = 0;
 543         instr->cat5.tex  = 0;
 544         instr->cat5.type = TYPE_F32;
 545
 546         ir3_reg_create(instr, regid(0,0),                 /* (xyzw)r0.x */
 547                         0)->wrmask = 0xf;
 548         ir3_reg_create(instr, regid(0,2), 0);             /* r0.z */
 549
 550         /* (sy)(rpt3)cov.f32f16 hr0.x, (r)r0.x */
 551         instr = ir3_instr_create(block, 1, 0);  /* mov/cov instructions have no opc */
 552         instr->flags = IR3_INSTR_SY;
 553         instr->repeat = 3;
 554         instr->cat1.src_type = TYPE_F32;
 555         instr->cat1.dst_type = TYPE_F16;
 556
 557         ir3_reg_create(instr, regid(0,0), IR3_REG_HALF);  /* hr0.x */
 558         ir3_reg_create(instr, regid(0,0), IR3_REG_R);     /* (r)r0.x */
 559
 560         /* end */
 561         instr = ir3_instr_create(block, 0, OPC_END);
 562
 563         so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
 564         if (!so)
 565                 return NULL;
 566
 567         so->half_precision = true;
 568         so->inputs_count = 1;
 569         so->inputs[0].semantic =
 570                 fd3_semantic_name(TGSI_SEMANTIC_TEXCOORD, 0);
 571         so->inputs[0].inloc = 8;
 572         so->inputs[0].compmask = 0x3;
 573         so->total_in = 2;
 574         so->outputs_count = 1;
 575         so->outputs[0].semantic =
 576                 fd3_semantic_name(TGSI_SEMANTIC_COLOR, 0);
 577         so->outputs[0].regid = regid(0,0);
 578         so->samplers_count = 1;
 579
 580         so->vpsrepl[0] = 0x99999999;
 581         so->vpsrepl[1] = 0x99999999;
 582         so->vpsrepl[2] = 0x99999999;
 583         so->vpsrepl[3] = 0x99999999;
 584
 585         return so;
 586 }
 587
 588 /* Creates shader:
 589  *    (sy)(ss)end
 590  */
 591 static struct fd3_shader_stateobj *
 592 create_blit_vp(struct pipe_context *pctx)
 593 {
 594         struct fd3_shader_stateobj *so;
 595         struct ir3_shader *ir = ir3_shader_create();
 596         struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
 597         struct ir3_instruction *instr;
 598
 599         /* (sy)(ss)end */
 600         instr = ir3_instr_create(block, 0, OPC_END);
 601         instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
 602
 603         so = create_internal_shader(pctx, SHADER_VERTEX, ir);
 604         if (!so)
 605                 return NULL;
 606
 607         so->inputs_count = 2;
 608         so->inputs[0].regid = regid(0,0);
 609         so->inputs[0].compmask = 0xf;
 610         so->inputs[1].regid = regid(1,0);
 611         so->inputs[1].compmask = 0xf;
 612         so->total_in = 8;
 613         so->outputs_count = 2;
 614         so->outputs[0].semantic =
 615                 fd3_semantic_name(TGSI_SEMANTIC_TEXCOORD, 0);
 616         so->outputs[0].regid = regid(0,0);
 617         so->outputs[1].semantic =
 618                 fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0);
 619         so->outputs[1].regid = regid(1,0);
 620
 621         fixup_vp_regfootprint(so);
 622
 623         return so;
 624 }
 625
 626 /* Creates shader:
 627  *    (sy)(ss)(rpt3)mov.f16f16 hr0.x, (r)hc0.x
 628  *    end
 629  */
 630 static struct fd3_shader_stateobj *
 631 create_solid_fp(struct pipe_context *pctx)
 632 {
 633         struct fd3_shader_stateobj *so;
 634         struct ir3_shader *ir = ir3_shader_create();
 635         struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
 636         struct ir3_instruction *instr;
 637
 638         /* (sy)(ss)(rpt3)mov.f16f16 hr0.x, (r)hc0.x */
 639         instr = ir3_instr_create(block, 1, 0);  /* mov/cov instructions have no opc */
 640         instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
 641         instr->repeat = 3;
 642         instr->cat1.src_type = TYPE_F16;
 643         instr->cat1.dst_type = TYPE_F16;
 644
 645         ir3_reg_create(instr, regid(0,0), IR3_REG_HALF);  /* hr0.x */
 646         ir3_reg_create(instr, regid(0,0), IR3_REG_HALF |  /* (r)hc0.x */
 647                         IR3_REG_CONST | IR3_REG_R);
 648
 649         /* end */
 650         instr = ir3_instr_create(block, 0, OPC_END);
 651
 652         so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
 653         if (!so)
 654                 return NULL;
 655
 656         so->half_precision = true;
 657         so->inputs_count = 0;
 658         so->outputs_count = 1;
 659         so->outputs[0].semantic =
 660                 fd3_semantic_name(TGSI_SEMANTIC_COLOR, 0);
 661         so->outputs[0].regid = regid(0, 0);
 662         so->total_in = 0;
 663
 664         return so;
 665 }
 666
 667 /* Creates shader:
 668  *    (sy)(ss)end
 669  */
 670 static struct fd3_shader_stateobj *
 671 create_solid_vp(struct pipe_context *pctx)
 672 {
 673         struct fd3_shader_stateobj *so;
 674         struct ir3_shader *ir = ir3_shader_create();
 675         struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
 676         struct ir3_instruction *instr;
 677
 678         /* (sy)(ss)end */
 679         instr = ir3_instr_create(block, 0, OPC_END);
 680         instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
 681
 682
 683         so = create_internal_shader(pctx, SHADER_VERTEX, ir);
 684         if (!so)
 685                 return NULL;
 686
 687         so->inputs_count = 1;
 688         so->inputs[0].regid = regid(0,0);
 689         so->inputs[0].compmask = 0xf;
 690         so->total_in = 4;
 691
 692         so->outputs_count = 1;
 693         so->outputs[0].semantic =
 694                 fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0);
 695         so->outputs[0].regid = regid(0,0);
 696
 697         fixup_vp_regfootprint(so);
 698
 699         return so;
 700 }
 701
 702 void
 703 fd3_prog_init(struct pipe_context *pctx)
 704 {
 705         struct fd_context *ctx = fd_context(pctx);
 706
 707         pctx->create_fs_state = fd3_fp_state_create;
 708         pctx->bind_fs_state = fd3_fp_state_bind;
 709         pctx->delete_fs_state = fd3_fp_state_delete;
 710
 711         pctx->create_vs_state = fd3_vp_state_create;
 712         pctx->bind_vs_state = fd3_vp_state_bind;
 713         pctx->delete_vs_state = fd3_vp_state_delete;
 714
 715         ctx->solid_prog.fp = create_solid_fp(pctx);
 716         ctx->solid_prog.vp = create_solid_vp(pctx);
 717         ctx->blit_prog.fp = create_blit_fp(pctx);
 718         ctx->blit_prog.vp = create_blit_vp(pctx);
 719 }
 720
 721 void
 722 fd3_prog_fini(struct pipe_context *pctx)
 723 {
 724         struct fd_context *ctx = fd_context(pctx);
 725
 726         delete_shader(ctx->solid_prog.vp);
 727         delete_shader(ctx->solid_prog.fp);
 728         delete_shader(ctx->blit_prog.vp);
 729         delete_shader(ctx->blit_prog.fp);
 730 }