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freedreno/a3xx/compiler: prepare for new compiler
[mesa.git] / src / gallium / drivers / freedreno / a3xx / fd3_program.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
36
37 #include "freedreno_lowering.h"
38
39 #include "fd3_program.h"
40 #include "fd3_compiler.h"
41 #include "fd3_emit.h"
42 #include "fd3_texture.h"
43 #include "fd3_util.h"
44
45 static void
46 delete_shader(struct fd3_shader_stateobj *so)
47 {
48 ir3_shader_destroy(so->ir);
49 fd_bo_del(so->bo);
50 free(so);
51 }
52
53 static void
54 assemble_shader(struct pipe_context *pctx, struct fd3_shader_stateobj *so)
55 {
56 struct fd_context *ctx = fd_context(pctx);
57 uint32_t sz, *bin;
58
59 bin = ir3_shader_assemble(so->ir, &so->info);
60 sz = so->info.sizedwords * 4;
61
62 so->bo = fd_bo_new(ctx->dev, sz,
63 DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
64 DRM_FREEDRENO_GEM_TYPE_KMEM);
65
66 memcpy(fd_bo_map(so->bo), bin, sz);
67
68 free(bin);
69
70 so->instrlen = so->info.sizedwords / 8;
71 so->constlen = so->info.max_const + 1;
72 }
73
74 /* for vertex shader, the inputs are loaded into registers before the shader
75 * is executed, so max_regs from the shader instructions might not properly
76 * reflect the # of registers actually used:
77 */
78 static void
79 fixup_vp_regfootprint(struct fd3_shader_stateobj *so)
80 {
81 unsigned i;
82 for (i = 0; i < so->inputs_count; i++)
83 so->info.max_reg = MAX2(so->info.max_reg, so->inputs[i].regid >> 2);
84 for (i = 0; i < so->outputs_count; i++)
85 so->info.max_reg = MAX2(so->info.max_reg, so->outputs[i].regid >> 2);
86 }
87
88 static struct fd3_shader_stateobj *
89 create_shader(struct pipe_context *pctx, const struct pipe_shader_state *cso,
90 enum shader_t type)
91 {
92 struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
93 const struct tgsi_token *tokens = fd_transform_lowering(cso->tokens);
94 int ret;
95
96 if (!so)
97 return NULL;
98
99 so->type = type;
100
101 if (fd_mesa_debug & FD_DBG_DISASM) {
102 DBG("dump tgsi: type=%d", so->type);
103 tgsi_dump(tokens, 0);
104 }
105
106 if ((type == SHADER_FRAGMENT) && (fd_mesa_debug & FD_DBG_FRAGHALF))
107 so->half_precision = true;
108
109 ret = fd3_compile_shader(so, tokens);
110 if (ret) {
111 debug_error("compile failed!");
112 goto fail;
113 }
114
115 assemble_shader(pctx, so);
116 if (!so->bo) {
117 debug_error("assemble failed!");
118 goto fail;
119 }
120
121 if (type == SHADER_VERTEX)
122 fixup_vp_regfootprint(so);
123
124 if (fd_mesa_debug & FD_DBG_DISASM) {
125 DBG("disassemble: type=%d", so->type);
126 disasm_a3xx(fd_bo_map(so->bo), so->info.sizedwords, 0, so->type);
127 }
128
129 return so;
130
131 fail:
132 delete_shader(so);
133 return NULL;
134 }
135
136 static void *
137 fd3_fp_state_create(struct pipe_context *pctx,
138 const struct pipe_shader_state *cso)
139 {
140 return create_shader(pctx, cso, SHADER_FRAGMENT);
141 }
142
143 static void
144 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
145 {
146 struct fd3_shader_stateobj *so = hwcso;
147 delete_shader(so);
148 }
149
150 static void
151 fd3_fp_state_bind(struct pipe_context *pctx, void *hwcso)
152 {
153 struct fd_context *ctx = fd_context(pctx);
154 ctx->prog.fp = hwcso;
155 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
156 ctx->dirty |= FD_DIRTY_PROG;
157 }
158
159 static void *
160 fd3_vp_state_create(struct pipe_context *pctx,
161 const struct pipe_shader_state *cso)
162 {
163 return create_shader(pctx, cso, SHADER_VERTEX);
164 }
165
166 static void
167 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
168 {
169 struct fd3_shader_stateobj *so = hwcso;
170 delete_shader(so);
171 }
172
173 static void
174 fd3_vp_state_bind(struct pipe_context *pctx, void *hwcso)
175 {
176 struct fd_context *ctx = fd_context(pctx);
177 ctx->prog.vp = hwcso;
178 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
179 ctx->dirty |= FD_DIRTY_PROG;
180 }
181
182 static void
183 emit_shader(struct fd_ringbuffer *ring, const struct fd3_shader_stateobj *so)
184 {
185 const struct ir3_shader_info *si = &so->info;
186 enum adreno_state_block sb;
187 enum adreno_state_src src;
188 uint32_t i, sz, *bin;
189
190 if (so->type == SHADER_VERTEX) {
191 sb = SB_VERT_SHADER;
192 } else {
193 sb = SB_FRAG_SHADER;
194 }
195
196 if (fd_mesa_debug & FD_DBG_DIRECT) {
197 sz = si->sizedwords;
198 src = SS_DIRECT;
199 bin = fd_bo_map(so->bo);
200 } else {
201 sz = 0;
202 src = SS_INDIRECT;
203 bin = NULL;
204 }
205
206 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
207 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
208 CP_LOAD_STATE_0_STATE_SRC(src) |
209 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
210 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
211 if (bin) {
212 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
213 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
214 } else {
215 OUT_RELOC(ring, so->bo, 0,
216 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
217 }
218 for (i = 0; i < sz; i++) {
219 OUT_RING(ring, bin[i]);
220 }
221 }
222
223 static int
224 find_output(const struct fd3_shader_stateobj *so, fd3_semantic semantic)
225 {
226 int j;
227 for (j = 0; j < so->outputs_count; j++)
228 if (so->outputs[j].semantic == semantic)
229 return j;
230 return 0;
231 }
232
233 static uint32_t
234 find_output_regid(const struct fd3_shader_stateobj *so, fd3_semantic semantic)
235 {
236 int j;
237 for (j = 0; j < so->outputs_count; j++)
238 if (so->outputs[j].semantic == semantic)
239 return so->outputs[j].regid;
240 return regid(63, 0);
241 }
242
243 void
244 fd3_program_emit(struct fd_ringbuffer *ring,
245 struct fd_program_stateobj *prog, bool binning)
246 {
247 const struct fd3_shader_stateobj *vp = prog->vp;
248 const struct fd3_shader_stateobj *fp = prog->fp;
249 const struct ir3_shader_info *vsi = &vp->info;
250 const struct ir3_shader_info *fsi = &fp->info;
251 uint32_t pos_regid, posz_regid, psize_regid, color_regid;
252 int i;
253
254 if (binning) {
255 /* use dummy stateobj to simplify binning vs non-binning: */
256 static const struct fd3_shader_stateobj binning_fp = {};
257 fp = &binning_fp;
258 fsi = &fp->info;
259 }
260
261 pos_regid = find_output_regid(vp,
262 fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
263 posz_regid = find_output_regid(fp,
264 fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
265 psize_regid = find_output_regid(vp,
266 fd3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
267 color_regid = find_output_regid(fp,
268 fd3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
269
270 /* we could probably divide this up into things that need to be
271 * emitted if frag-prog is dirty vs if vert-prog is dirty..
272 */
273
274 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
275 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
276 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
277 * flush some caches? I think we only need to set those
278 * bits if we have updated const or shader..
279 */
280 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
281 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
282 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
283 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
284 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
285 OUT_RING(ring, 0x00000000); /* HLSQ_CONTROL_3_REG */
286 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
287 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
288 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vp->instrlen));
289 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
290 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
291 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fp->instrlen));
292
293 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
294 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(0) |
295 COND(binning, A3XX_SP_SP_CTRL_REG_BINNING) |
296 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
297 A3XX_SP_SP_CTRL_REG_L0MODE(0));
298
299 OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
300 OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
301
302 OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
303 OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
304 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
305 A3XX_SP_VS_CTRL_REG0_CACHEINVALID |
306 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
307 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
308 A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
309 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
310 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
311 COND(vp->samplers_count > 0, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
312 A3XX_SP_VS_CTRL_REG0_LENGTH(vp->instrlen));
313 OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
314 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
315 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vsi->max_const, 0)));
316 OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
317 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
318 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->inputs_count));
319
320 for (i = 0; i < fp->inputs_count; ) {
321 uint32_t reg = 0;
322 int j;
323
324 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i/2), 1);
325
326 j = find_output(vp, fp->inputs[i].semantic);
327 reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[j].regid);
328 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[i].compmask);
329 i++;
330
331 j = find_output(vp, fp->inputs[i].semantic);
332 reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[j].regid);
333 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[i].compmask);
334 i++;
335
336 OUT_RING(ring, reg);
337 }
338
339 for (i = 0; i < fp->inputs_count; ) {
340 uint32_t reg = 0;
341
342 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i/4), 1);
343
344 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[i++].inloc);
345 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[i++].inloc);
346 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[i++].inloc);
347 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[i++].inloc);
348
349 OUT_RING(ring, reg);
350 }
351
352 OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
353 OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
354 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
355 OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
356
357 if (binning) {
358 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
359 OUT_RING(ring, 0x00000000);
360
361 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
362 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
363 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
364 OUT_RING(ring, 0x00000000);
365 } else {
366 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
367 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
368
369 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
370 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
371 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
372 A3XX_SP_FS_CTRL_REG0_CACHEINVALID |
373 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
374 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
375 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
376 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
377 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
378 COND(fp->samplers_count > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
379 A3XX_SP_FS_CTRL_REG0_LENGTH(fp->instrlen));
380 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
381 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
382 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fsi->max_const, 0)) |
383 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
384 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
385 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
386 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
387 OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
388 }
389
390 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
391 OUT_RING(ring, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
392 OUT_RING(ring, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
393
394 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
395 if (fp->writes_pos) {
396 OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE |
397 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
398 } else {
399 OUT_RING(ring, 0x00000000);
400 }
401
402 OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
403 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(color_regid) |
404 COND(fp->half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION));
405 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
406 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
407 OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
408
409 if (binning) {
410 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
411 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
412 A3XX_VPC_ATTR_LMSIZE(1));
413 OUT_RING(ring, 0x00000000);
414 } else {
415 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
416 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
417 A3XX_VPC_ATTR_THRDASSIGN(1) |
418 A3XX_VPC_ATTR_LMSIZE(1));
419 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
420 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
421
422 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
423 OUT_RING(ring, fp->vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
424 OUT_RING(ring, fp->vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
425 OUT_RING(ring, fp->vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
426 OUT_RING(ring, fp->vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
427
428 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
429 OUT_RING(ring, fp->vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
430 OUT_RING(ring, fp->vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
431 OUT_RING(ring, fp->vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
432 OUT_RING(ring, fp->vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
433 }
434
435 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
436 OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
437 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
438
439 emit_shader(ring, vp);
440
441 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
442 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
443
444 if (!binning) {
445 emit_shader(ring, fp);
446
447 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
448 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
449 }
450
451 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
452 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(vp->total_in) |
453 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
454 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(vp->inputs_count) |
455 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(vp->inputs_count));
456 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
457 A3XX_VFD_CONTROL_1_REGID4VTX(regid(63,0)) |
458 A3XX_VFD_CONTROL_1_REGID4INST(regid(63,0)));
459 }
460
461 /* once the compiler is good enough, we should construct TGSI in the
462 * core freedreno driver, and then let the a2xx/a3xx parts compile
463 * the internal shaders from TGSI the same as regular shaders. This
464 * would be the first step towards handling most of clear (and the
465 * gmem<->mem blits) from the core via normal state changes and shader
466 * state objects.
467 *
468 * (Well, there would still be some special bits, because there are
469 * some registers that don't get set for normal draw, but this should
470 * be relatively small and could be handled via callbacks from core
471 * into a2xx/a3xx..)
472 */
473 static struct fd3_shader_stateobj *
474 create_internal_shader(struct pipe_context *pctx, enum shader_t type,
475 struct ir3_shader *ir)
476 {
477 struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
478
479 if (!so) {
480 ir3_shader_destroy(ir);
481 return NULL;
482 }
483
484 so->type = type;
485 so->ir = ir;
486
487 assemble_shader(pctx, so);
488 assert(so->bo);
489
490 return so;
491 }
492
493 /* Creates shader:
494 * (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)0, r0.x
495 * (rpt5)nop
496 * sam (f32)(xyzw)r0.x, r0.z, s#0, t#0
497 * (sy)(rpt3)cov.f32f16 hr0.x, (r)r0.x
498 * end
499 */
500 static struct fd3_shader_stateobj *
501 create_blit_fp(struct pipe_context *pctx)
502 {
503 struct fd3_shader_stateobj *so;
504 struct ir3_shader *ir = ir3_shader_create();
505 struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
506 struct ir3_instruction *instr;
507
508 /* (sy)(ss)(rpt1)bary.f (ei)r0.z, (r)0, r0.x */
509 instr = ir3_instr_create(block, 2, OPC_BARY_F);
510 instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
511 instr->repeat = 1;
512
513 ir3_reg_create(instr, regid(0,2), IR3_REG_EI); /* (ei)r0.z */
514 ir3_reg_create(instr, 0, IR3_REG_R | /* (r)0 */
515 IR3_REG_IMMED)->iim_val = 0;
516 ir3_reg_create(instr, regid(0,0), 0); /* r0.x */
517
518 /* (rpt5)nop */
519 instr = ir3_instr_create(block, 0, OPC_NOP);
520 instr->repeat = 5;
521
522 /* sam (f32)(xyzw)r0.x, r0.z, s#0, t#0 */
523 instr = ir3_instr_create(block, 5, OPC_SAM);
524 instr->cat5.samp = 0;
525 instr->cat5.tex = 0;
526 instr->cat5.type = TYPE_F32;
527
528 ir3_reg_create(instr, regid(0,0), /* (xyzw)r0.x */
529 0)->wrmask = 0xf;
530 ir3_reg_create(instr, regid(0,2), 0); /* r0.z */
531
532 /* (sy)(rpt3)cov.f32f16 hr0.x, (r)r0.x */
533 instr = ir3_instr_create(block, 1, 0); /* mov/cov instructions have no opc */
534 instr->flags = IR3_INSTR_SY;
535 instr->repeat = 3;
536 instr->cat1.src_type = TYPE_F32;
537 instr->cat1.dst_type = TYPE_F16;
538
539 ir3_reg_create(instr, regid(0,0), IR3_REG_HALF); /* hr0.x */
540 ir3_reg_create(instr, regid(0,0), IR3_REG_R); /* (r)r0.x */
541
542 /* end */
543 instr = ir3_instr_create(block, 0, OPC_END);
544
545 so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
546 if (!so)
547 return NULL;
548
549 so->half_precision = true;
550 so->inputs_count = 1;
551 so->inputs[0].semantic =
552 fd3_semantic_name(TGSI_SEMANTIC_TEXCOORD, 0);
553 so->inputs[0].inloc = 8;
554 so->inputs[0].compmask = 0x3;
555 so->total_in = 2;
556 so->outputs_count = 1;
557 so->outputs[0].semantic =
558 fd3_semantic_name(TGSI_SEMANTIC_COLOR, 0);
559 so->outputs[0].regid = regid(0,0);
560 so->samplers_count = 1;
561
562 so->vpsrepl[0] = 0x99999999;
563 so->vpsrepl[1] = 0x99999999;
564 so->vpsrepl[2] = 0x99999999;
565 so->vpsrepl[3] = 0x99999999;
566
567 return so;
568 }
569
570 /* Creates shader:
571 * (sy)(ss)end
572 */
573 static struct fd3_shader_stateobj *
574 create_blit_vp(struct pipe_context *pctx)
575 {
576 struct fd3_shader_stateobj *so;
577 struct ir3_shader *ir = ir3_shader_create();
578 struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
579 struct ir3_instruction *instr;
580
581 /* (sy)(ss)end */
582 instr = ir3_instr_create(block, 0, OPC_END);
583 instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
584
585 so = create_internal_shader(pctx, SHADER_VERTEX, ir);
586 if (!so)
587 return NULL;
588
589 so->inputs_count = 2;
590 so->inputs[0].regid = regid(0,0);
591 so->inputs[0].compmask = 0xf;
592 so->inputs[1].regid = regid(1,0);
593 so->inputs[1].compmask = 0xf;
594 so->total_in = 8;
595 so->outputs_count = 2;
596 so->outputs[0].semantic =
597 fd3_semantic_name(TGSI_SEMANTIC_TEXCOORD, 0);
598 so->outputs[0].regid = regid(0,0);
599 so->outputs[1].semantic =
600 fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0);
601 so->outputs[1].regid = regid(1,0);
602
603 fixup_vp_regfootprint(so);
604
605 return so;
606 }
607
608 /* Creates shader:
609 * (sy)(ss)(rpt3)mov.f16f16 hr0.x, (r)hc0.x
610 * end
611 */
612 static struct fd3_shader_stateobj *
613 create_solid_fp(struct pipe_context *pctx)
614 {
615 struct fd3_shader_stateobj *so;
616 struct ir3_shader *ir = ir3_shader_create();
617 struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
618 struct ir3_instruction *instr;
619
620 /* (sy)(ss)(rpt3)mov.f16f16 hr0.x, (r)hc0.x */
621 instr = ir3_instr_create(block, 1, 0); /* mov/cov instructions have no opc */
622 instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
623 instr->repeat = 3;
624 instr->cat1.src_type = TYPE_F16;
625 instr->cat1.dst_type = TYPE_F16;
626
627 ir3_reg_create(instr, regid(0,0), IR3_REG_HALF); /* hr0.x */
628 ir3_reg_create(instr, regid(0,0), IR3_REG_HALF | /* (r)hc0.x */
629 IR3_REG_CONST | IR3_REG_R);
630
631 /* end */
632 instr = ir3_instr_create(block, 0, OPC_END);
633
634 so = create_internal_shader(pctx, SHADER_FRAGMENT, ir);
635 if (!so)
636 return NULL;
637
638 so->half_precision = true;
639 so->inputs_count = 0;
640 so->outputs_count = 1;
641 so->outputs[0].semantic =
642 fd3_semantic_name(TGSI_SEMANTIC_COLOR, 0);
643 so->outputs[0].regid = regid(0, 0);
644 so->total_in = 0;
645
646 return so;
647 }
648
649 /* Creates shader:
650 * (sy)(ss)end
651 */
652 static struct fd3_shader_stateobj *
653 create_solid_vp(struct pipe_context *pctx)
654 {
655 struct fd3_shader_stateobj *so;
656 struct ir3_shader *ir = ir3_shader_create();
657 struct ir3_block *block = ir3_block_create(ir, 0, 0, 0);
658 struct ir3_instruction *instr;
659
660 /* (sy)(ss)end */
661 instr = ir3_instr_create(block, 0, OPC_END);
662 instr->flags = IR3_INSTR_SY | IR3_INSTR_SS;
663
664
665 so = create_internal_shader(pctx, SHADER_VERTEX, ir);
666 if (!so)
667 return NULL;
668
669 so->inputs_count = 1;
670 so->inputs[0].regid = regid(0,0);
671 so->inputs[0].compmask = 0xf;
672 so->total_in = 4;
673
674 so->outputs_count = 1;
675 so->outputs[0].semantic =
676 fd3_semantic_name(TGSI_SEMANTIC_POSITION, 0);
677 so->outputs[0].regid = regid(0,0);
678
679 fixup_vp_regfootprint(so);
680
681 return so;
682 }
683
684 void
685 fd3_prog_init(struct pipe_context *pctx)
686 {
687 struct fd_context *ctx = fd_context(pctx);
688
689 pctx->create_fs_state = fd3_fp_state_create;
690 pctx->bind_fs_state = fd3_fp_state_bind;
691 pctx->delete_fs_state = fd3_fp_state_delete;
692
693 pctx->create_vs_state = fd3_vp_state_create;
694 pctx->bind_vs_state = fd3_vp_state_bind;
695 pctx->delete_vs_state = fd3_vp_state_delete;
696
697 ctx->solid_prog.fp = create_solid_fp(pctx);
698 ctx->solid_prog.vp = create_solid_vp(pctx);
699 ctx->blit_prog.fp = create_blit_fp(pctx);
700 ctx->blit_prog.vp = create_blit_vp(pctx);
701 }
702
703 void
704 fd3_prog_fini(struct pipe_context *pctx)
705 {
706 struct fd_context *ctx = fd_context(pctx);
707
708 delete_shader(ctx->solid_prog.vp);
709 delete_shader(ctx->solid_prog.fp);
710 delete_shader(ctx->blit_prog.vp);
711 delete_shader(ctx->blit_prog.fp);
712 }