src/gallium/drivers/freedreno/a3xx/fd3_program.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_math.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_inlines.h"
  34 #include "util/u_format.h"
  35
  36 #include "freedreno_program.h"
  37
  38 #include "fd3_program.h"
  39 #include "fd3_emit.h"
  40 #include "fd3_texture.h"
  41 #include "fd3_format.h"
  42
  43 static void
  44 delete_shader_stateobj(struct fd3_shader_stateobj *so)
  45 {
  46         ir3_shader_destroy(so->shader);
  47         free(so);
  48 }
  49
  50 static struct fd3_shader_stateobj *
  51 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
  52                 enum shader_t type)
  53 {
  54         struct fd_context *ctx = fd_context(pctx);
  55         struct ir3_compiler *compiler = ctx->screen->compiler;
  56         struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
  57         so->shader = ir3_shader_create(compiler, cso, type, &ctx->debug);
  58         return so;
  59 }
  60
  61 static void *
  62 fd3_fp_state_create(struct pipe_context *pctx,
  63                 const struct pipe_shader_state *cso)
  64 {
  65         return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
  66 }
  67
  68 static void
  69 fd3_fp_state_delete(struct pipe_context *pctx, void *hwcso)
  70 {
  71         struct fd3_shader_stateobj *so = hwcso;
  72         delete_shader_stateobj(so);
  73 }
  74
  75 static void *
  76 fd3_vp_state_create(struct pipe_context *pctx,
  77                 const struct pipe_shader_state *cso)
  78 {
  79         return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
  80 }
  81
  82 static void
  83 fd3_vp_state_delete(struct pipe_context *pctx, void *hwcso)
  84 {
  85         struct fd3_shader_stateobj *so = hwcso;
  86         delete_shader_stateobj(so);
  87 }
  88
  89 bool
  90 fd3_needs_manual_clipping(const struct fd3_shader_stateobj *so,
  91                                                   const struct pipe_rasterizer_state *rast)
  92 {
  93         uint64_t outputs = ir3_shader_outputs(so->shader);
  94
  95         return (!rast->depth_clip ||
  96                         util_bitcount(rast->clip_plane_enable) > 6 ||
  97                         outputs & ((1ULL << VARYING_SLOT_CLIP_VERTEX) |
  98                                            (1ULL << VARYING_SLOT_CLIP_DIST0) |
  99                                            (1ULL << VARYING_SLOT_CLIP_DIST1)));
 100 }
 101
 102
 103 static void
 104 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
 105 {
 106         const struct ir3_info *si = &so->info;
 107         enum adreno_state_block sb;
 108         enum adreno_state_src src;
 109         uint32_t i, sz, *bin;
 110
 111         if (so->type == SHADER_VERTEX) {
 112                 sb = SB_VERT_SHADER;
 113         } else {
 114                 sb = SB_FRAG_SHADER;
 115         }
 116
 117         if (fd_mesa_debug & FD_DBG_DIRECT) {
 118                 sz = si->sizedwords;
 119                 src = SS_DIRECT;
 120                 bin = fd_bo_map(so->bo);
 121         } else {
 122                 sz = 0;
 123                 src = SS_INDIRECT;
 124                 bin = NULL;
 125         }
 126
 127         OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
 128         OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
 129                         CP_LOAD_STATE_0_STATE_SRC(src) |
 130                         CP_LOAD_STATE_0_STATE_BLOCK(sb) |
 131                         CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
 132         if (bin) {
 133                 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
 134                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
 135         } else {
 136                 OUT_RELOC(ring, so->bo, 0,
 137                                 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
 138         }
 139         for (i = 0; i < sz; i++) {
 140                 OUT_RING(ring, bin[i]);
 141         }
 142 }
 143
 144 void
 145 fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
 146                                  int nr, struct pipe_surface **bufs)
 147 {
 148         const struct ir3_shader_variant *vp, *fp;
 149         const struct ir3_info *vsi, *fsi;
 150         enum a3xx_instrbuffermode fpbuffer, vpbuffer;
 151         uint32_t fpbuffersz, vpbuffersz, fsoff;
 152         uint32_t pos_regid, posz_regid, psize_regid, color_regid[4] = {0};
 153         int constmode;
 154         int i, j;
 155
 156         debug_assert(nr <= ARRAY_SIZE(color_regid));
 157
 158         vp = fd3_emit_get_vp(emit);
 159         fp = fd3_emit_get_fp(emit);
 160
 161         vsi = &vp->info;
 162         fsi = &fp->info;
 163
 164         fpbuffer = BUFFER;
 165         vpbuffer = BUFFER;
 166         fpbuffersz = fp->instrlen;
 167         vpbuffersz = vp->instrlen;
 168
 169         /*
 170          * Decide whether to use BUFFER or CACHE mode for VS and FS.  It
 171          * appears like 256 is the hard limit, but when the combined size
 172          * exceeds 128 then blob will try to keep FS in BUFFER mode and
 173          * switch to CACHE for VS until VS is too large.  The blob seems
 174          * to switch FS out of BUFFER mode at slightly under 128.  But
 175          * a bit fuzzy on the decision tree, so use slightly conservative
 176          * limits.
 177          *
 178          * TODO check if these thresholds for BUFFER vs CACHE mode are the
 179          *      same for all a3xx or whether we need to consider the gpuid
 180          */
 181
 182         if ((fpbuffersz + vpbuffersz) > 128) {
 183                 if (fpbuffersz < 112) {
 184                         /* FP:BUFFER   VP:CACHE  */
 185                         vpbuffer = CACHE;
 186                         vpbuffersz = 256 - fpbuffersz;
 187                 } else if (vpbuffersz < 112) {
 188                         /* FP:CACHE    VP:BUFFER */
 189                         fpbuffer = CACHE;
 190                         fpbuffersz = 256 - vpbuffersz;
 191                 } else {
 192                         /* FP:CACHE    VP:CACHE  */
 193                         vpbuffer = fpbuffer = CACHE;
 194                         vpbuffersz = fpbuffersz = 192;
 195                 }
 196         }
 197
 198         if (fpbuffer == BUFFER) {
 199                 fsoff = 128 - fpbuffersz;
 200         } else {
 201                 fsoff = 256 - fpbuffersz;
 202         }
 203
 204         /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
 205         constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
 206
 207         pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
 208         posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
 209         psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
 210         if (fp->color0_mrt) {
 211                 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
 212                         ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
 213         } else {
 214                 color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
 215                 color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
 216                 color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
 217                 color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
 218         }
 219
 220         /* adjust regids for alpha output formats. there is no alpha render
 221          * format, so it's just treated like red
 222          */
 223         for (i = 0; i < nr; i++)
 224                 if (util_format_is_alpha(pipe_surface_format(bufs[i])))
 225                         color_regid[i] += 3;
 226
 227         /* we could probably divide this up into things that need to be
 228          * emitted if frag-prog is dirty vs if vert-prog is dirty..
 229          */
 230
 231         OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
 232         OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
 233                         A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
 234                         /* NOTE:  I guess SHADERRESTART and CONSTFULLUPDATE maybe
 235                          * flush some caches? I think we only need to set those
 236                          * bits if we have updated const or shader..
 237                          */
 238                         A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
 239                         A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
 240         OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
 241                         A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
 242                         COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(regid(0,0)) |
 243                                         A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(regid(0,2))));
 244         OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
 245         OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
 246         OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
 247                         A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
 248                         A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
 249         OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
 250                         A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
 251                         A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
 252
 253         OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
 254         OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
 255                         COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
 256                         A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
 257                         A3XX_SP_SP_CTRL_REG_L0MODE(0));
 258
 259         OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
 260         OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
 261
 262         OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
 263         OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
 264                         A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
 265                         COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
 266                         A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
 267                         A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
 268                         A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
 269                         A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
 270                         A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
 271         OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
 272                         A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
 273                         A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
 274         OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
 275                         A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
 276                         A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->varying_in));
 277
 278         struct ir3_shader_linkage l = {0};
 279         ir3_link_shaders(&l, vp, fp);
 280
 281         for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
 282                 uint32_t reg = 0;
 283
 284                 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
 285
 286                 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
 287                 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
 288                 j++;
 289
 290                 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
 291                 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
 292                 j++;
 293
 294                 OUT_RING(ring, reg);
 295         }
 296
 297         for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
 298                 uint32_t reg = 0;
 299
 300                 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
 301
 302                 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
 303                 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
 304                 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
 305                 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
 306
 307                 OUT_RING(ring, reg);
 308         }
 309
 310         OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
 311         OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
 312                         A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 313         OUT_RELOC(ring, vp->bo, 0, 0, 0);  /* SP_VS_OBJ_START_REG */
 314
 315         if (emit->key.binning_pass) {
 316                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 317                 OUT_RING(ring, 0x00000000);
 318
 319                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 320                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 321                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
 322                 OUT_RING(ring, 0x00000000);
 323
 324                 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
 325                 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
 326                                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
 327         } else {
 328                 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
 329                 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
 330
 331                 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
 332                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
 333                                 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
 334                                 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
 335                                 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
 336                                 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
 337                                 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP |
 338                                 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
 339                                 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
 340                                 COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
 341                                 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
 342                 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
 343                                 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
 344                                 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
 345                                 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
 346
 347                 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
 348                 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
 349                                         MAX2(128, vp->constlen)) |
 350                                 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
 351                 OUT_RELOC(ring, fp->bo, 0, 0, 0);  /* SP_FS_OBJ_START_REG */
 352         }
 353
 354         OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
 355         OUT_RING(ring,
 356                          COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
 357                          A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
 358                          A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
 359
 360         OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
 361         for (i = 0; i < 4; i++) {
 362                 uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
 363                         COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
 364
 365                 if (i < nr) {
 366                         enum pipe_format fmt = pipe_surface_format(bufs[i]);
 367                         mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
 368                                 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
 369                 }
 370                 OUT_RING(ring, mrt_reg);
 371         }
 372
 373         if (emit->key.binning_pass) {
 374                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 375                 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
 376                                 A3XX_VPC_ATTR_LMSIZE(1) |
 377                                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
 378                 OUT_RING(ring, 0x00000000);
 379         } else {
 380                 uint32_t vinterp[4], flatshade[2], vpsrepl[4];
 381
 382                 memset(vinterp, 0, sizeof(vinterp));
 383                 memset(flatshade, 0, sizeof(flatshade));
 384                 memset(vpsrepl, 0, sizeof(vpsrepl));
 385
 386                 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
 387                 for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
 388                         /* NOTE: varyings are packed, so if compmask is 0xb
 389                          * then first, third, and fourth component occupy
 390                          * three consecutive varying slots:
 391                          */
 392                         unsigned compmask = fp->inputs[j].compmask;
 393
 394                         uint32_t inloc = fp->inputs[j].inloc;
 395
 396                         if ((fp->inputs[j].interpolate == INTERP_MODE_FLAT) ||
 397                                         (fp->inputs[j].rasterflat && emit->rasterflat)) {
 398                                 uint32_t loc = inloc;
 399
 400                                 for (i = 0; i < 4; i++) {
 401                                         if (compmask & (1 << i)) {
 402                                                 vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
 403                                                 flatshade[loc / 32] |= 1 << (loc % 32);
 404                                                 loc++;
 405                                         }
 406                                 }
 407                         }
 408
 409                         gl_varying_slot slot = fp->inputs[j].slot;
 410
 411                         /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
 412                         if (slot >= VARYING_SLOT_VAR0) {
 413                                 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
 414                                 /* Replace the .xy coordinates with S/T from the point sprite. Set
 415                                  * interpolation bits for .zw such that they become .01
 416                                  */
 417                                 if (emit->sprite_coord_enable & texmask) {
 418                                         /* mask is two 2-bit fields, where:
 419                                          *   '01' -> S
 420                                          *   '10' -> T
 421                                          *   '11' -> 1 - T  (flip mode)
 422                                          */
 423                                         unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
 424                                         uint32_t loc = inloc;
 425                                         if (compmask & 0x1) {
 426                                                 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
 427                                                 loc++;
 428                                         }
 429                                         if (compmask & 0x2) {
 430                                                 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
 431                                                 loc++;
 432                                         }
 433                                         if (compmask & 0x4) {
 434                                                 /* .z <- 0.0f */
 435                                                 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
 436                                                 loc++;
 437                                         }
 438                                         if (compmask & 0x8) {
 439                                                 /* .w <- 1.0f */
 440                                                 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
 441                                                 loc++;
 442                                         }
 443                                 }
 444                         }
 445                 }
 446
 447                 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
 448                 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
 449                                 A3XX_VPC_ATTR_THRDASSIGN(1) |
 450                                 A3XX_VPC_ATTR_LMSIZE(1) |
 451                                 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
 452                 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
 453                                 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
 454
 455                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
 456                 OUT_RING(ring, vinterp[0]);    /* VPC_VARYING_INTERP[0].MODE */
 457                 OUT_RING(ring, vinterp[1]);    /* VPC_VARYING_INTERP[1].MODE */
 458                 OUT_RING(ring, vinterp[2]);    /* VPC_VARYING_INTERP[2].MODE */
 459                 OUT_RING(ring, vinterp[3]);    /* VPC_VARYING_INTERP[3].MODE */
 460
 461                 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
 462                 OUT_RING(ring, vpsrepl[0]);    /* VPC_VARYING_PS_REPL[0].MODE */
 463                 OUT_RING(ring, vpsrepl[1]);    /* VPC_VARYING_PS_REPL[1].MODE */
 464                 OUT_RING(ring, vpsrepl[2]);    /* VPC_VARYING_PS_REPL[2].MODE */
 465                 OUT_RING(ring, vpsrepl[3]);    /* VPC_VARYING_PS_REPL[3].MODE */
 466
 467                 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
 468                 OUT_RING(ring, flatshade[0]);        /* SP_FS_FLAT_SHAD_MODE_REG_0 */
 469                 OUT_RING(ring, flatshade[1]);        /* SP_FS_FLAT_SHAD_MODE_REG_1 */
 470         }
 471
 472         if (vpbuffer == BUFFER)
 473                 emit_shader(ring, vp);
 474
 475         OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 476         OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 477
 478         if (!emit->key.binning_pass) {
 479                 if (fpbuffer == BUFFER)
 480                         emit_shader(ring, fp);
 481
 482                 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
 483                 OUT_RING(ring, 0x00000000);        /* VFD_PERFCOUNTER0_SELECT */
 484         }
 485 }
 486
 487 void
 488 fd3_prog_init(struct pipe_context *pctx)
 489 {
 490         pctx->create_fs_state = fd3_fp_state_create;
 491         pctx->delete_fs_state = fd3_fp_state_delete;
 492
 493         pctx->create_vs_state = fd3_vp_state_create;
 494         pctx->delete_vs_state = fd3_vp_state_delete;
 495
 496         fd_prog_init(pctx);
 497 }