1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
37 #include "freedreno_program.h"
39 #include "fd3_program.h"
41 #include "fd3_texture.h"
45 delete_shader_stateobj(struct fd3_shader_stateobj
*so
)
47 ir3_shader_destroy(so
->shader
);
51 static struct fd3_shader_stateobj
*
52 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
55 struct fd3_shader_stateobj
*so
= CALLOC_STRUCT(fd3_shader_stateobj
);
56 so
->shader
= ir3_shader_create(pctx
, cso
->tokens
, type
);
61 fd3_fp_state_create(struct pipe_context
*pctx
,
62 const struct pipe_shader_state
*cso
)
64 return create_shader_stateobj(pctx
, cso
, SHADER_FRAGMENT
);
68 fd3_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
70 struct fd3_shader_stateobj
*so
= hwcso
;
71 delete_shader_stateobj(so
);
75 fd3_vp_state_create(struct pipe_context
*pctx
,
76 const struct pipe_shader_state
*cso
)
78 return create_shader_stateobj(pctx
, cso
, SHADER_VERTEX
);
82 fd3_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
84 struct fd3_shader_stateobj
*so
= hwcso
;
85 delete_shader_stateobj(so
);
89 emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
91 const struct ir3_info
*si
= &so
->info
;
92 enum adreno_state_block sb
;
93 enum adreno_state_src src
;
96 if (so
->type
== SHADER_VERTEX
) {
102 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
105 bin
= fd_bo_map(so
->bo
);
112 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
113 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
114 CP_LOAD_STATE_0_STATE_SRC(src
) |
115 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
116 CP_LOAD_STATE_0_NUM_UNIT(so
->instrlen
));
118 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
119 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
));
121 OUT_RELOC(ring
, so
->bo
, 0,
122 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
), 0);
124 for (i
= 0; i
< sz
; i
++) {
125 OUT_RING(ring
, bin
[i
]);
130 find_output(const struct ir3_shader_variant
*so
, ir3_semantic semantic
)
134 for (j
= 0; j
< so
->outputs_count
; j
++)
135 if (so
->outputs
[j
].semantic
== semantic
)
138 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
139 * in the vertex shader.. but the fragment shader doesn't know this
140 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
141 * at link time if there is no matching OUT.BCOLOR[n], we must map
142 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
143 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
145 if (sem2name(semantic
) == TGSI_SEMANTIC_BCOLOR
) {
146 unsigned idx
= sem2idx(semantic
);
147 semantic
= ir3_semantic_name(TGSI_SEMANTIC_COLOR
, idx
);
148 } else if (sem2name(semantic
) == TGSI_SEMANTIC_COLOR
) {
149 unsigned idx
= sem2idx(semantic
);
150 semantic
= ir3_semantic_name(TGSI_SEMANTIC_BCOLOR
, idx
);
153 for (j
= 0; j
< so
->outputs_count
; j
++)
154 if (so
->outputs
[j
].semantic
== semantic
)
163 next_varying(const struct ir3_shader_variant
*so
, int i
)
165 while (++i
< so
->inputs_count
)
166 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
172 find_output_regid(const struct ir3_shader_variant
*so
, ir3_semantic semantic
)
175 for (j
= 0; j
< so
->outputs_count
; j
++)
176 if (so
->outputs
[j
].semantic
== semantic
)
177 return so
->outputs
[j
].regid
;
182 fd3_program_emit(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
)
184 const struct ir3_shader_variant
*vp
, *fp
;
185 const struct ir3_info
*vsi
, *fsi
;
186 enum a3xx_instrbuffermode fpbuffer
, vpbuffer
;
187 uint32_t fpbuffersz
, vpbuffersz
, fsoff
;
188 uint32_t pos_regid
, posz_regid
, psize_regid
, color_regid
;
192 vp
= fd3_emit_get_vp(emit
);
194 if (emit
->key
.binning_pass
) {
195 /* use dummy stateobj to simplify binning vs non-binning: */
196 static const struct ir3_shader_variant binning_fp
= {};
199 fp
= fd3_emit_get_fp(emit
);
207 fpbuffersz
= fp
->instrlen
;
208 vpbuffersz
= vp
->instrlen
;
211 * Decide whether to use BUFFER or CACHE mode for VS and FS. It
212 * appears like 256 is the hard limit, but when the combined size
213 * exceeds 128 then blob will try to keep FS in BUFFER mode and
214 * switch to CACHE for VS until VS is too large. The blob seems
215 * to switch FS out of BUFFER mode at slightly under 128. But
216 * a bit fuzzy on the decision tree, so use slightly conservative
219 * TODO check if these thresholds for BUFFER vs CACHE mode are the
220 * same for all a3xx or whether we need to consider the gpuid
223 if ((fpbuffersz
+ vpbuffersz
) > 128) {
224 if (fpbuffersz
< 112) {
225 /* FP:BUFFER VP:CACHE */
227 vpbuffersz
= 256 - fpbuffersz
;
228 } else if (vpbuffersz
< 112) {
229 /* FP:CACHE VP:BUFFER */
231 fpbuffersz
= 256 - vpbuffersz
;
233 /* FP:CACHE VP:CACHE */
234 vpbuffer
= fpbuffer
= CACHE
;
235 vpbuffersz
= fpbuffersz
= 192;
239 if (fpbuffer
== BUFFER
) {
240 fsoff
= 128 - fpbuffersz
;
242 fsoff
= 256 - fpbuffersz
;
245 /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
246 constmode
= ((vp
->constlen
+ fp
->constlen
) > 256) ? 1 : 0;
248 pos_regid
= find_output_regid(vp
,
249 ir3_semantic_name(TGSI_SEMANTIC_POSITION
, 0));
250 posz_regid
= find_output_regid(fp
,
251 ir3_semantic_name(TGSI_SEMANTIC_POSITION
, 0));
252 psize_regid
= find_output_regid(vp
,
253 ir3_semantic_name(TGSI_SEMANTIC_PSIZE
, 0));
254 color_regid
= find_output_regid(fp
,
255 ir3_semantic_name(TGSI_SEMANTIC_COLOR
, 0));
257 /* we could probably divide this up into things that need to be
258 * emitted if frag-prog is dirty vs if vert-prog is dirty..
261 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 6);
262 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
263 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode
) |
264 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
265 * flush some caches? I think we only need to set those
266 * bits if we have updated const or shader..
268 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
|
269 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
270 OUT_RING(ring
, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
271 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
|
272 COND(fp
->frag_coord
, A3XX_HLSQ_CONTROL_1_REG_ZWCOORD
));
273 OUT_RING(ring
, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
274 OUT_RING(ring
, A3XX_HLSQ_CONTROL_3_REG_REGID(fp
->pos_regid
));
275 OUT_RING(ring
, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp
->constlen
) |
276 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
277 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz
));
278 OUT_RING(ring
, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp
->constlen
) |
279 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
280 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz
));
282 OUT_PKT0(ring
, REG_A3XX_SP_SP_CTRL_REG
, 1);
283 OUT_RING(ring
, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode
) |
284 COND(emit
->key
.binning_pass
, A3XX_SP_SP_CTRL_REG_BINNING
) |
285 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
286 A3XX_SP_SP_CTRL_REG_L0MODE(0));
288 OUT_PKT0(ring
, REG_A3XX_SP_VS_LENGTH_REG
, 1);
289 OUT_RING(ring
, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp
->instrlen
));
291 OUT_PKT0(ring
, REG_A3XX_SP_VS_CTRL_REG0
, 3);
292 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI
) |
293 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer
) |
294 COND(vpbuffer
== CACHE
, A3XX_SP_VS_CTRL_REG0_CACHEINVALID
) |
295 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi
->max_half_reg
+ 1) |
296 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi
->max_reg
+ 1) |
297 A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
298 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
299 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
|
300 COND(vp
->has_samp
, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE
) |
301 A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz
));
302 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp
->constlen
) |
303 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp
->total_in
) |
304 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp
->constlen
+ 1, 0)));
305 OUT_RING(ring
, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid
) |
306 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid
) |
307 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp
->total_in
, 4) / 4));
309 for (i
= 0, j
= -1; (i
< 8) && (j
< (int)fp
->inputs_count
); i
++) {
312 OUT_PKT0(ring
, REG_A3XX_SP_VS_OUT_REG(i
), 1);
314 j
= next_varying(fp
, j
);
315 if (j
< fp
->inputs_count
) {
316 k
= find_output(vp
, fp
->inputs
[j
].semantic
);
317 reg
|= A3XX_SP_VS_OUT_REG_A_REGID(vp
->outputs
[k
].regid
);
318 reg
|= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp
->inputs
[j
].compmask
);
321 j
= next_varying(fp
, j
);
322 if (j
< fp
->inputs_count
) {
323 k
= find_output(vp
, fp
->inputs
[j
].semantic
);
324 reg
|= A3XX_SP_VS_OUT_REG_B_REGID(vp
->outputs
[k
].regid
);
325 reg
|= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp
->inputs
[j
].compmask
);
331 for (i
= 0, j
= -1; (i
< 4) && (j
< (int)fp
->inputs_count
); i
++) {
334 OUT_PKT0(ring
, REG_A3XX_SP_VS_VPC_DST_REG(i
), 1);
336 j
= next_varying(fp
, j
);
337 if (j
< fp
->inputs_count
)
338 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp
->inputs
[j
].inloc
);
339 j
= next_varying(fp
, j
);
340 if (j
< fp
->inputs_count
)
341 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp
->inputs
[j
].inloc
);
342 j
= next_varying(fp
, j
);
343 if (j
< fp
->inputs_count
)
344 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp
->inputs
[j
].inloc
);
345 j
= next_varying(fp
, j
);
346 if (j
< fp
->inputs_count
)
347 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp
->inputs
[j
].inloc
);
352 OUT_PKT0(ring
, REG_A3XX_SP_VS_OBJ_OFFSET_REG
, 2);
353 OUT_RING(ring
, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
354 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
355 OUT_RELOC(ring
, vp
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_REG */
357 if (emit
->key
.binning_pass
) {
358 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
359 OUT_RING(ring
, 0x00000000);
361 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
362 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
363 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER
));
364 OUT_RING(ring
, 0x00000000);
366 OUT_PKT0(ring
, REG_A3XX_SP_FS_OBJ_OFFSET_REG
, 1);
367 OUT_RING(ring
, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
368 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
370 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
371 OUT_RING(ring
, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp
->instrlen
));
373 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
374 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
375 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer
) |
376 COND(fpbuffer
== CACHE
, A3XX_SP_FS_CTRL_REG0_CACHEINVALID
) |
377 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi
->max_half_reg
+ 1) |
378 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi
->max_reg
+ 1) |
379 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
380 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
381 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
|
382 COND(fp
->has_samp
> 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE
) |
383 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz
));
384 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp
->constlen
) |
385 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp
->total_in
) |
386 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp
->constlen
+ 1, 0)) |
387 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
389 OUT_PKT0(ring
, REG_A3XX_SP_FS_OBJ_OFFSET_REG
, 2);
390 OUT_RING(ring
, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
391 MAX2(128, vp
->constlen
)) |
392 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff
));
393 OUT_RELOC(ring
, fp
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_REG */
396 OUT_PKT0(ring
, REG_A3XX_SP_FS_OUTPUT_REG
, 1);
397 if (fp
->writes_pos
) {
398 OUT_RING(ring
, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
|
399 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid
));
401 OUT_RING(ring
, 0x00000000);
404 OUT_PKT0(ring
, REG_A3XX_SP_FS_MRT_REG(0), 4);
405 OUT_RING(ring
, A3XX_SP_FS_MRT_REG_REGID(color_regid
) |
406 COND(fp
->key
.half_precision
, A3XX_SP_FS_MRT_REG_HALF_PRECISION
));
407 OUT_RING(ring
, A3XX_SP_FS_MRT_REG_REGID(0));
408 OUT_RING(ring
, A3XX_SP_FS_MRT_REG_REGID(0));
409 OUT_RING(ring
, A3XX_SP_FS_MRT_REG_REGID(0));
411 if (emit
->key
.binning_pass
) {
412 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
413 OUT_RING(ring
, A3XX_VPC_ATTR_THRDASSIGN(1) |
414 A3XX_VPC_ATTR_LMSIZE(1) |
415 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
416 OUT_RING(ring
, 0x00000000);
418 uint32_t vinterp
[4] = {0}, flatshade
[2] = {0};
420 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
421 for (j
= -1; (j
= next_varying(fp
, j
)) < (int)fp
->inputs_count
; ) {
422 uint32_t interp
= fp
->inputs
[j
].interpolate
;
423 if ((interp
== TGSI_INTERPOLATE_CONSTANT
) ||
424 ((interp
== TGSI_INTERPOLATE_COLOR
) && emit
->rasterflat
)) {
425 /* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
426 * instead.. rather than -8 everywhere else..
428 uint32_t loc
= fp
->inputs
[j
].inloc
- 8;
430 /* currently assuming varyings aligned to 4 (not
433 debug_assert((loc
% 4) == 0);
435 for (i
= 0; i
< 4; i
++, loc
++) {
436 vinterp
[loc
/ 16] |= FLAT
<< ((loc
% 16) * 2);
437 flatshade
[loc
/ 32] |= 1 << (loc
% 32);
442 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
443 OUT_RING(ring
, A3XX_VPC_ATTR_TOTALATTR(fp
->total_in
) |
444 A3XX_VPC_ATTR_THRDASSIGN(1) |
445 A3XX_VPC_ATTR_LMSIZE(1) |
446 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
447 OUT_RING(ring
, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp
->total_in
) |
448 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp
->total_in
));
450 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
451 OUT_RING(ring
, vinterp
[0]); /* VPC_VARYING_INTERP[0].MODE */
452 OUT_RING(ring
, vinterp
[1]); /* VPC_VARYING_INTERP[1].MODE */
453 OUT_RING(ring
, vinterp
[2]); /* VPC_VARYING_INTERP[2].MODE */
454 OUT_RING(ring
, vinterp
[3]); /* VPC_VARYING_INTERP[3].MODE */
456 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
457 OUT_RING(ring
, fp
->shader
->vpsrepl
[0]); /* VPC_VARYING_PS_REPL[0].MODE */
458 OUT_RING(ring
, fp
->shader
->vpsrepl
[1]); /* VPC_VARYING_PS_REPL[1].MODE */
459 OUT_RING(ring
, fp
->shader
->vpsrepl
[2]); /* VPC_VARYING_PS_REPL[2].MODE */
460 OUT_RING(ring
, fp
->shader
->vpsrepl
[3]); /* VPC_VARYING_PS_REPL[3].MODE */
462 OUT_PKT0(ring
, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0
, 2);
463 OUT_RING(ring
, flatshade
[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
464 OUT_RING(ring
, flatshade
[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
467 OUT_PKT0(ring
, REG_A3XX_VFD_VS_THREADING_THRESHOLD
, 1);
468 OUT_RING(ring
, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
469 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
471 if (vpbuffer
== BUFFER
)
472 emit_shader(ring
, vp
);
474 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
475 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
477 if (!emit
->key
.binning_pass
) {
478 if (fpbuffer
== BUFFER
)
479 emit_shader(ring
, fp
);
481 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
482 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
486 /* hack.. until we figure out how to deal w/ vpsrepl properly.. */
488 fix_blit_fp(struct pipe_context
*pctx
)
490 struct fd_context
*ctx
= fd_context(pctx
);
491 struct fd3_shader_stateobj
*so
= ctx
->blit_prog
.fp
;
493 so
->shader
->vpsrepl
[0] = 0x99999999;
494 so
->shader
->vpsrepl
[1] = 0x99999999;
495 so
->shader
->vpsrepl
[2] = 0x99999999;
496 so
->shader
->vpsrepl
[3] = 0x99999999;
500 fd3_prog_init(struct pipe_context
*pctx
)
502 pctx
->create_fs_state
= fd3_fp_state_create
;
503 pctx
->delete_fs_state
= fd3_fp_state_delete
;
505 pctx
->create_vs_state
= fd3_vp_state_create
;
506 pctx
->delete_vs_state
= fd3_vp_state_delete
;