1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34 #include "tgsi/tgsi_dump.h"
35 #include "tgsi/tgsi_parse.h"
37 #include "freedreno_lowering.h"
38 #include "freedreno_program.h"
40 #include "fd3_program.h"
41 #include "fd3_compiler.h"
43 #include "fd3_texture.h"
47 delete_variant(struct fd3_shader_variant
*v
)
55 assemble_variant(struct fd3_shader_variant
*so
)
57 struct fd_context
*ctx
= fd_context(so
->so
->pctx
);
60 bin
= ir3_assemble(so
->ir
, &so
->info
);
61 sz
= so
->info
.sizedwords
* 4;
63 so
->bo
= fd_bo_new(ctx
->dev
, sz
,
64 DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
65 DRM_FREEDRENO_GEM_TYPE_KMEM
);
67 memcpy(fd_bo_map(so
->bo
), bin
, sz
);
71 so
->instrlen
= so
->info
.sizedwords
/ 8;
72 so
->constlen
= so
->info
.max_const
+ 1;
75 /* for vertex shader, the inputs are loaded into registers before the shader
76 * is executed, so max_regs from the shader instructions might not properly
77 * reflect the # of registers actually used:
80 fixup_vp_regfootprint(struct fd3_shader_variant
*so
)
83 for (i
= 0; i
< so
->inputs_count
; i
++) {
84 if (so
->inputs
[i
].compmask
) {
85 uint32_t regid
= (so
->inputs
[i
].regid
+ 3) >> 2;
86 so
->info
.max_reg
= MAX2(so
->info
.max_reg
, regid
);
89 for (i
= 0; i
< so
->outputs_count
; i
++) {
90 uint32_t regid
= (so
->outputs
[i
].regid
+ 3) >> 2;
91 so
->info
.max_reg
= MAX2(so
->info
.max_reg
, regid
);
95 static struct fd3_shader_variant
*
96 create_variant(struct fd3_shader_stateobj
*so
, struct fd3_shader_key key
)
98 struct fd3_shader_variant
*v
= CALLOC_STRUCT(fd3_shader_variant
);
99 const struct tgsi_token
*tokens
= so
->tokens
;
109 if (fd_mesa_debug
& FD_DBG_DISASM
) {
110 DBG("dump tgsi: type=%d, k={bp=%u,cts=%u,hp=%u}", so
->type
,
111 key
.binning_pass
, key
.color_two_side
, key
.half_precision
);
112 tgsi_dump(tokens
, 0);
115 if (!(fd_mesa_debug
& FD_DBG_NOOPT
)) {
116 ret
= fd3_compile_shader(v
, tokens
, key
);
118 debug_error("new compiler failed, trying fallback!");
121 v
->outputs_count
= 0;
124 v
->immediates_count
= 0;
127 ret
= -1; /* force fallback to old compiler */
131 ret
= fd3_compile_shader_old(v
, tokens
, key
);
134 debug_error("compile failed!");
140 debug_error("assemble failed!");
144 if (so
->type
== SHADER_VERTEX
)
145 fixup_vp_regfootprint(v
);
147 if (fd_mesa_debug
& FD_DBG_DISASM
) {
148 DBG("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v
->type
,
149 key
.binning_pass
, key
.color_two_side
, key
.half_precision
);
150 disasm_a3xx(fd_bo_map(v
->bo
), v
->info
.sizedwords
, 0, v
->type
);
160 struct fd3_shader_variant
*
161 fd3_shader_variant(struct fd3_shader_stateobj
*so
, struct fd3_shader_key key
)
163 struct fd3_shader_variant
*v
;
165 /* some shader key values only apply to vertex or frag shader,
166 * so normalize the key to avoid constructing multiple identical
169 if (so
->type
== SHADER_FRAGMENT
) {
170 key
.binning_pass
= false;
172 if (so
->type
== SHADER_VERTEX
) {
173 key
.color_two_side
= false;
174 key
.half_precision
= false;
177 for (v
= so
->variants
; v
; v
= v
->next
)
178 if (!memcmp(&key
, &v
->key
, sizeof(key
)))
181 /* compile new variant if it doesn't exist already: */
182 v
= create_variant(so
, key
);
183 v
->next
= so
->variants
;
191 delete_shader(struct fd3_shader_stateobj
*so
)
193 struct fd3_shader_variant
*v
, *t
;
194 for (v
= so
->variants
; v
; ) {
199 free((void *)so
->tokens
);
203 static struct fd3_shader_stateobj
*
204 create_shader(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
207 struct fd3_shader_stateobj
*so
= CALLOC_STRUCT(fd3_shader_stateobj
);
210 so
->tokens
= tgsi_dup_tokens(cso
->tokens
);
215 fd3_fp_state_create(struct pipe_context
*pctx
,
216 const struct pipe_shader_state
*cso
)
218 return create_shader(pctx
, cso
, SHADER_FRAGMENT
);
222 fd3_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
224 struct fd3_shader_stateobj
*so
= hwcso
;
229 fd3_vp_state_create(struct pipe_context
*pctx
,
230 const struct pipe_shader_state
*cso
)
232 return create_shader(pctx
, cso
, SHADER_VERTEX
);
236 fd3_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
238 struct fd3_shader_stateobj
*so
= hwcso
;
243 emit_shader(struct fd_ringbuffer
*ring
, const struct fd3_shader_variant
*so
)
245 const struct ir3_info
*si
= &so
->info
;
246 enum adreno_state_block sb
;
247 enum adreno_state_src src
;
248 uint32_t i
, sz
, *bin
;
250 if (so
->type
== SHADER_VERTEX
) {
256 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
259 bin
= fd_bo_map(so
->bo
);
266 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
267 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
268 CP_LOAD_STATE_0_STATE_SRC(src
) |
269 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
270 CP_LOAD_STATE_0_NUM_UNIT(so
->instrlen
));
272 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
273 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
));
275 OUT_RELOC(ring
, so
->bo
, 0,
276 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
), 0);
278 for (i
= 0; i
< sz
; i
++) {
279 OUT_RING(ring
, bin
[i
]);
284 find_output(const struct fd3_shader_variant
*so
, fd3_semantic semantic
)
288 for (j
= 0; j
< so
->outputs_count
; j
++)
289 if (so
->outputs
[j
].semantic
== semantic
)
292 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
293 * in the vertex shader.. but the fragment shader doesn't know this
294 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
295 * at link time if there is no matching OUT.BCOLOR[n], we must map
296 * OUT.COLOR[n] to IN.BCOLOR[n].
298 if (sem2name(semantic
) == TGSI_SEMANTIC_BCOLOR
) {
299 unsigned idx
= sem2idx(semantic
);
300 return find_output(so
, fd3_semantic_name(TGSI_SEMANTIC_COLOR
, idx
));
309 next_varying(const struct fd3_shader_variant
*so
, int i
)
311 while (++i
< so
->inputs_count
)
312 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
318 find_output_regid(const struct fd3_shader_variant
*so
, fd3_semantic semantic
)
321 for (j
= 0; j
< so
->outputs_count
; j
++)
322 if (so
->outputs
[j
].semantic
== semantic
)
323 return so
->outputs
[j
].regid
;
328 fd3_program_emit(struct fd_ringbuffer
*ring
,
329 struct fd_program_stateobj
*prog
, struct fd3_shader_key key
)
331 const struct fd3_shader_variant
*vp
, *fp
;
332 const struct ir3_info
*vsi
, *fsi
;
333 uint32_t pos_regid
, posz_regid
, psize_regid
, color_regid
;
336 vp
= fd3_shader_variant(prog
->vp
, key
);
338 if (key
.binning_pass
) {
339 /* use dummy stateobj to simplify binning vs non-binning: */
340 static const struct fd3_shader_variant binning_fp
= {};
343 fp
= fd3_shader_variant(prog
->fp
, key
);
349 pos_regid
= find_output_regid(vp
,
350 fd3_semantic_name(TGSI_SEMANTIC_POSITION
, 0));
351 posz_regid
= find_output_regid(fp
,
352 fd3_semantic_name(TGSI_SEMANTIC_POSITION
, 0));
353 psize_regid
= find_output_regid(vp
,
354 fd3_semantic_name(TGSI_SEMANTIC_PSIZE
, 0));
355 color_regid
= find_output_regid(fp
,
356 fd3_semantic_name(TGSI_SEMANTIC_COLOR
, 0));
358 /* we could probably divide this up into things that need to be
359 * emitted if frag-prog is dirty vs if vert-prog is dirty..
362 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 6);
363 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
364 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
365 * flush some caches? I think we only need to set those
366 * bits if we have updated const or shader..
368 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
|
369 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
370 OUT_RING(ring
, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
371 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
|
372 COND(fp
->frag_coord
, A3XX_HLSQ_CONTROL_1_REG_ZWCOORD
));
373 OUT_RING(ring
, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
374 OUT_RING(ring
, A3XX_HLSQ_CONTROL_3_REG_REGID(fp
->pos_regid
));
375 OUT_RING(ring
, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp
->constlen
) |
376 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
377 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vp
->instrlen
));
378 OUT_RING(ring
, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp
->constlen
) |
379 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
380 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fp
->instrlen
));
382 OUT_PKT0(ring
, REG_A3XX_SP_SP_CTRL_REG
, 1);
383 OUT_RING(ring
, A3XX_SP_SP_CTRL_REG_CONSTMODE(0) |
384 COND(key
.binning_pass
, A3XX_SP_SP_CTRL_REG_BINNING
) |
385 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
386 A3XX_SP_SP_CTRL_REG_L0MODE(0));
388 OUT_PKT0(ring
, REG_A3XX_SP_VS_LENGTH_REG
, 1);
389 OUT_RING(ring
, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp
->instrlen
));
391 OUT_PKT0(ring
, REG_A3XX_SP_VS_CTRL_REG0
, 3);
392 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI
) |
393 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(BUFFER
) |
394 A3XX_SP_VS_CTRL_REG0_CACHEINVALID
|
395 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi
->max_half_reg
+ 1) |
396 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi
->max_reg
+ 1) |
397 A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
398 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
399 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
|
400 COND(vp
->has_samp
, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE
) |
401 A3XX_SP_VS_CTRL_REG0_LENGTH(vp
->instrlen
));
402 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp
->constlen
) |
403 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp
->total_in
) |
404 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vsi
->max_const
, 0)));
405 OUT_RING(ring
, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid
) |
406 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid
) |
407 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp
->total_in
, 4) / 4));
409 for (i
= 0, j
= -1; (i
< 8) && (j
< (int)fp
->inputs_count
); i
++) {
412 OUT_PKT0(ring
, REG_A3XX_SP_VS_OUT_REG(i
), 1);
414 j
= next_varying(fp
, j
);
415 if (j
< fp
->inputs_count
) {
416 k
= find_output(vp
, fp
->inputs
[j
].semantic
);
417 reg
|= A3XX_SP_VS_OUT_REG_A_REGID(vp
->outputs
[k
].regid
);
418 reg
|= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp
->inputs
[j
].compmask
);
421 j
= next_varying(fp
, j
);
422 if (j
< fp
->inputs_count
) {
423 k
= find_output(vp
, fp
->inputs
[j
].semantic
);
424 reg
|= A3XX_SP_VS_OUT_REG_B_REGID(vp
->outputs
[k
].regid
);
425 reg
|= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp
->inputs
[j
].compmask
);
431 for (i
= 0, j
= -1; (i
< 4) && (j
< (int)fp
->inputs_count
); i
++) {
434 OUT_PKT0(ring
, REG_A3XX_SP_VS_VPC_DST_REG(i
), 1);
436 j
= next_varying(fp
, j
);
437 if (j
< fp
->inputs_count
)
438 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp
->inputs
[j
].inloc
);
439 j
= next_varying(fp
, j
);
440 if (j
< fp
->inputs_count
)
441 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp
->inputs
[j
].inloc
);
442 j
= next_varying(fp
, j
);
443 if (j
< fp
->inputs_count
)
444 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp
->inputs
[j
].inloc
);
445 j
= next_varying(fp
, j
);
446 if (j
< fp
->inputs_count
)
447 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp
->inputs
[j
].inloc
);
452 OUT_PKT0(ring
, REG_A3XX_SP_VS_OBJ_OFFSET_REG
, 2);
453 OUT_RING(ring
, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
454 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
455 OUT_RELOC(ring
, vp
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_REG */
457 if (key
.binning_pass
) {
458 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
459 OUT_RING(ring
, 0x00000000);
461 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
462 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
463 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER
));
464 OUT_RING(ring
, 0x00000000);
466 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
467 OUT_RING(ring
, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp
->instrlen
));
469 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
470 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
471 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER
) |
472 A3XX_SP_FS_CTRL_REG0_CACHEINVALID
|
473 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi
->max_half_reg
+ 1) |
474 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi
->max_reg
+ 1) |
475 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
476 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
477 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
|
478 COND(fp
->has_samp
> 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE
) |
479 A3XX_SP_FS_CTRL_REG0_LENGTH(fp
->instrlen
));
480 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp
->constlen
) |
481 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp
->total_in
) |
482 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fsi
->max_const
, 0)) |
483 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
484 OUT_PKT0(ring
, REG_A3XX_SP_FS_OBJ_OFFSET_REG
, 2);
485 OUT_RING(ring
, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
486 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
487 OUT_RELOC(ring
, fp
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_REG */
490 OUT_PKT0(ring
, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0
, 2);
491 OUT_RING(ring
, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
492 OUT_RING(ring
, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
494 OUT_PKT0(ring
, REG_A3XX_SP_FS_OUTPUT_REG
, 1);
495 if (fp
->writes_pos
) {
496 OUT_RING(ring
, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
|
497 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid
));
499 OUT_RING(ring
, 0x00000000);
502 OUT_PKT0(ring
, REG_A3XX_SP_FS_MRT_REG(0), 4);
503 OUT_RING(ring
, A3XX_SP_FS_MRT_REG_REGID(color_regid
) |
504 COND(fp
->key
.half_precision
, A3XX_SP_FS_MRT_REG_HALF_PRECISION
));
505 OUT_RING(ring
, A3XX_SP_FS_MRT_REG_REGID(0));
506 OUT_RING(ring
, A3XX_SP_FS_MRT_REG_REGID(0));
507 OUT_RING(ring
, A3XX_SP_FS_MRT_REG_REGID(0));
509 if (key
.binning_pass
) {
510 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
511 OUT_RING(ring
, A3XX_VPC_ATTR_THRDASSIGN(1) |
512 A3XX_VPC_ATTR_LMSIZE(1) |
513 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
514 OUT_RING(ring
, 0x00000000);
516 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
517 OUT_RING(ring
, A3XX_VPC_ATTR_TOTALATTR(fp
->total_in
) |
518 A3XX_VPC_ATTR_THRDASSIGN(1) |
519 A3XX_VPC_ATTR_LMSIZE(1) |
520 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
521 OUT_RING(ring
, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp
->total_in
) |
522 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp
->total_in
));
524 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
525 OUT_RING(ring
, fp
->so
->vinterp
[0]); /* VPC_VARYING_INTERP[0].MODE */
526 OUT_RING(ring
, fp
->so
->vinterp
[1]); /* VPC_VARYING_INTERP[1].MODE */
527 OUT_RING(ring
, fp
->so
->vinterp
[2]); /* VPC_VARYING_INTERP[2].MODE */
528 OUT_RING(ring
, fp
->so
->vinterp
[3]); /* VPC_VARYING_INTERP[3].MODE */
530 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
531 OUT_RING(ring
, fp
->so
->vpsrepl
[0]); /* VPC_VARYING_PS_REPL[0].MODE */
532 OUT_RING(ring
, fp
->so
->vpsrepl
[1]); /* VPC_VARYING_PS_REPL[1].MODE */
533 OUT_RING(ring
, fp
->so
->vpsrepl
[2]); /* VPC_VARYING_PS_REPL[2].MODE */
534 OUT_RING(ring
, fp
->so
->vpsrepl
[3]); /* VPC_VARYING_PS_REPL[3].MODE */
537 OUT_PKT0(ring
, REG_A3XX_VFD_VS_THREADING_THRESHOLD
, 1);
538 OUT_RING(ring
, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
539 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
541 emit_shader(ring
, vp
);
543 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
544 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
546 if (!key
.binning_pass
) {
547 emit_shader(ring
, fp
);
549 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
550 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
554 /* hack.. until we figure out how to deal w/ vpsrepl properly.. */
556 fix_blit_fp(struct pipe_context
*pctx
)
558 struct fd_context
*ctx
= fd_context(pctx
);
559 struct fd3_shader_stateobj
*so
= ctx
->blit_prog
.fp
;
561 so
->vpsrepl
[0] = 0x99999999;
562 so
->vpsrepl
[1] = 0x99999999;
563 so
->vpsrepl
[2] = 0x99999999;
564 so
->vpsrepl
[3] = 0x99999999;
568 fd3_prog_init(struct pipe_context
*pctx
)
570 pctx
->create_fs_state
= fd3_fp_state_create
;
571 pctx
->delete_fs_state
= fd3_fp_state_delete
;
573 pctx
->create_vs_state
= fd3_vp_state_create
;
574 pctx
->delete_vs_state
= fd3_vp_state_delete
;