2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
34 #include "freedreno_program.h"
36 #include "fd3_program.h"
38 #include "fd3_texture.h"
39 #include "fd3_format.h"
42 fd3_needs_manual_clipping(const struct ir3_shader
*shader
,
43 const struct pipe_rasterizer_state
*rast
)
45 uint64_t outputs
= ir3_shader_outputs(shader
);
47 return (!rast
->depth_clip_near
||
48 util_bitcount(rast
->clip_plane_enable
) > 6 ||
49 outputs
& ((1ULL << VARYING_SLOT_CLIP_VERTEX
) |
50 (1ULL << VARYING_SLOT_CLIP_DIST0
) |
51 (1ULL << VARYING_SLOT_CLIP_DIST1
)));
56 emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
58 const struct ir3_info
*si
= &so
->info
;
59 enum adreno_state_block sb
;
60 enum adreno_state_src src
;
63 if (so
->type
== MESA_SHADER_VERTEX
) {
69 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
72 bin
= fd_bo_map(so
->bo
);
79 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
80 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
81 CP_LOAD_STATE_0_STATE_SRC(src
) |
82 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
83 CP_LOAD_STATE_0_NUM_UNIT(so
->instrlen
));
85 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
86 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
));
88 OUT_RELOC(ring
, so
->bo
, 0,
89 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
), 0);
91 for (i
= 0; i
< sz
; i
++) {
92 OUT_RING(ring
, bin
[i
]);
97 fd3_program_emit(struct fd_ringbuffer
*ring
, struct fd3_emit
*emit
,
98 int nr
, struct pipe_surface
**bufs
)
100 const struct ir3_shader_variant
*vp
, *fp
;
101 const struct ir3_info
*vsi
, *fsi
;
102 enum a3xx_instrbuffermode fpbuffer
, vpbuffer
;
103 uint32_t fpbuffersz
, vpbuffersz
, fsoff
;
104 uint32_t pos_regid
, posz_regid
, psize_regid
;
105 uint32_t ij_regid
[4], face_regid
, coord_regid
, zwcoord_regid
;
106 uint32_t color_regid
[4] = {0};
110 debug_assert(nr
<= ARRAY_SIZE(color_regid
));
112 vp
= fd3_emit_get_vp(emit
);
113 fp
= fd3_emit_get_fp(emit
);
120 fpbuffersz
= fp
->instrlen
;
121 vpbuffersz
= vp
->instrlen
;
124 * Decide whether to use BUFFER or CACHE mode for VS and FS. It
125 * appears like 256 is the hard limit, but when the combined size
126 * exceeds 128 then blob will try to keep FS in BUFFER mode and
127 * switch to CACHE for VS until VS is too large. The blob seems
128 * to switch FS out of BUFFER mode at slightly under 128. But
129 * a bit fuzzy on the decision tree, so use slightly conservative
132 * TODO check if these thresholds for BUFFER vs CACHE mode are the
133 * same for all a3xx or whether we need to consider the gpuid
136 if ((fpbuffersz
+ vpbuffersz
) > 128) {
137 if (fpbuffersz
< 112) {
138 /* FP:BUFFER VP:CACHE */
140 vpbuffersz
= 256 - fpbuffersz
;
141 } else if (vpbuffersz
< 112) {
142 /* FP:CACHE VP:BUFFER */
144 fpbuffersz
= 256 - vpbuffersz
;
146 /* FP:CACHE VP:CACHE */
147 vpbuffer
= fpbuffer
= CACHE
;
148 vpbuffersz
= fpbuffersz
= 192;
152 if (fpbuffer
== BUFFER
) {
153 fsoff
= 128 - fpbuffersz
;
155 fsoff
= 256 - fpbuffersz
;
158 /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
159 constmode
= ((vp
->constlen
+ fp
->constlen
) > 256) ? 1 : 0;
161 pos_regid
= ir3_find_output_regid(vp
, VARYING_SLOT_POS
);
162 posz_regid
= ir3_find_output_regid(fp
, FRAG_RESULT_DEPTH
);
163 psize_regid
= ir3_find_output_regid(vp
, VARYING_SLOT_PSIZ
);
164 if (fp
->color0_mrt
) {
165 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
166 ir3_find_output_regid(fp
, FRAG_RESULT_COLOR
);
168 color_regid
[0] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA0
);
169 color_regid
[1] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA1
);
170 color_regid
[2] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA2
);
171 color_regid
[3] = ir3_find_output_regid(fp
, FRAG_RESULT_DATA3
);
174 face_regid
= ir3_find_sysval_regid(fp
, SYSTEM_VALUE_FRONT_FACE
);
175 coord_regid
= ir3_find_sysval_regid(fp
, SYSTEM_VALUE_FRAG_COORD
);
176 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
177 ij_regid
[0] = ir3_find_sysval_regid(fp
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
178 ij_regid
[1] = ir3_find_sysval_regid(fp
, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL
);
179 ij_regid
[2] = ir3_find_sysval_regid(fp
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
180 ij_regid
[3] = ir3_find_sysval_regid(fp
, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID
);
182 /* adjust regids for alpha output formats. there is no alpha render
183 * format, so it's just treated like red
185 for (i
= 0; i
< nr
; i
++)
186 if (util_format_is_alpha(pipe_surface_format(bufs
[i
])))
189 /* we could probably divide this up into things that need to be
190 * emitted if frag-prog is dirty vs if vert-prog is dirty..
193 OUT_PKT0(ring
, REG_A3XX_HLSQ_CONTROL_0_REG
, 6);
194 OUT_RING(ring
, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS
) |
195 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
|
196 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode
) |
197 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
198 * flush some caches? I think we only need to set those
199 * bits if we have updated const or shader..
201 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
|
202 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
203 OUT_RING(ring
, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
204 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
|
205 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(coord_regid
) |
206 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(zwcoord_regid
));
207 OUT_RING(ring
, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31) |
208 A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(face_regid
));
210 A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(ij_regid
[0]) |
211 A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(ij_regid
[1]) |
212 A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(ij_regid
[2]) |
213 A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(ij_regid
[3]));
214 OUT_RING(ring
, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp
->constlen
) |
215 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
216 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz
));
217 OUT_RING(ring
, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp
->constlen
) |
218 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
219 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz
));
221 OUT_PKT0(ring
, REG_A3XX_SP_SP_CTRL_REG
, 1);
222 OUT_RING(ring
, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode
) |
223 COND(emit
->binning_pass
, A3XX_SP_SP_CTRL_REG_BINNING
) |
224 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
225 A3XX_SP_SP_CTRL_REG_L0MODE(0));
227 OUT_PKT0(ring
, REG_A3XX_SP_VS_LENGTH_REG
, 1);
228 OUT_RING(ring
, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp
->instrlen
));
230 OUT_PKT0(ring
, REG_A3XX_SP_VS_CTRL_REG0
, 3);
231 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI
) |
232 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer
) |
233 COND(vpbuffer
== CACHE
, A3XX_SP_VS_CTRL_REG0_CACHEINVALID
) |
234 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi
->max_half_reg
+ 1) |
235 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi
->max_reg
+ 1) |
236 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
237 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
|
238 A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz
));
239 OUT_RING(ring
, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp
->constlen
) |
240 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp
->total_in
) |
241 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp
->constlen
- 1, 0)));
242 OUT_RING(ring
, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid
) |
243 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid
) |
244 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp
->varying_in
));
246 struct ir3_shader_linkage l
= {0};
247 ir3_link_shaders(&l
, vp
, fp
, false);
249 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
252 OUT_PKT0(ring
, REG_A3XX_SP_VS_OUT_REG(i
), 1);
254 reg
|= A3XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
255 reg
|= A3XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
258 reg
|= A3XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
259 reg
|= A3XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
265 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
268 OUT_PKT0(ring
, REG_A3XX_SP_VS_VPC_DST_REG(i
), 1);
270 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
+ 8);
271 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
+ 8);
272 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
+ 8);
273 reg
|= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
+ 8);
278 OUT_PKT0(ring
, REG_A3XX_SP_VS_OBJ_OFFSET_REG
, 2);
279 OUT_RING(ring
, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
280 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
281 OUT_RELOC(ring
, vp
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_REG */
283 if (emit
->binning_pass
) {
284 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
285 OUT_RING(ring
, 0x00000000);
287 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
288 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
289 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER
));
290 OUT_RING(ring
, 0x00000000);
292 OUT_PKT0(ring
, REG_A3XX_SP_FS_OBJ_OFFSET_REG
, 1);
293 OUT_RING(ring
, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
294 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
296 OUT_PKT0(ring
, REG_A3XX_SP_FS_LENGTH_REG
, 1);
297 OUT_RING(ring
, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp
->instrlen
));
299 OUT_PKT0(ring
, REG_A3XX_SP_FS_CTRL_REG0
, 2);
300 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
301 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer
) |
302 COND(fpbuffer
== CACHE
, A3XX_SP_FS_CTRL_REG0_CACHEINVALID
) |
303 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi
->max_half_reg
+ 1) |
304 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi
->max_reg
+ 1) |
305 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP
|
306 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS
) |
307 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
|
308 COND(fp
->need_pixlod
, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE
) |
309 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz
));
310 OUT_RING(ring
, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp
->constlen
) |
311 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp
->total_in
) |
312 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp
->constlen
- 1, 0)) |
313 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
315 OUT_PKT0(ring
, REG_A3XX_SP_FS_OBJ_OFFSET_REG
, 2);
316 OUT_RING(ring
, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
317 MAX2(128, vp
->constlen
)) |
318 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff
));
319 OUT_RELOC(ring
, fp
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_REG */
322 OUT_PKT0(ring
, REG_A3XX_SP_FS_OUTPUT_REG
, 1);
324 COND(fp
->writes_pos
, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
) |
325 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid
) |
326 A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr
) - 1));
328 OUT_PKT0(ring
, REG_A3XX_SP_FS_MRT_REG(0), 4);
329 for (i
= 0; i
< 4; i
++) {
330 uint32_t mrt_reg
= A3XX_SP_FS_MRT_REG_REGID(color_regid
[i
]) |
331 COND(color_regid
[i
] & HALF_REG_ID
, A3XX_SP_FS_MRT_REG_HALF_PRECISION
);
334 enum pipe_format fmt
= pipe_surface_format(bufs
[i
]);
335 mrt_reg
|= COND(util_format_is_pure_uint(fmt
), A3XX_SP_FS_MRT_REG_UINT
) |
336 COND(util_format_is_pure_sint(fmt
), A3XX_SP_FS_MRT_REG_SINT
);
338 OUT_RING(ring
, mrt_reg
);
341 if (emit
->binning_pass
) {
342 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
343 OUT_RING(ring
, A3XX_VPC_ATTR_THRDASSIGN(1) |
344 A3XX_VPC_ATTR_LMSIZE(1) |
345 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
346 OUT_RING(ring
, 0x00000000);
348 uint32_t vinterp
[4], flatshade
[2], vpsrepl
[4];
350 memset(vinterp
, 0, sizeof(vinterp
));
351 memset(flatshade
, 0, sizeof(flatshade
));
352 memset(vpsrepl
, 0, sizeof(vpsrepl
));
354 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
355 for (j
= -1; (j
= ir3_next_varying(fp
, j
)) < (int)fp
->inputs_count
; ) {
356 /* NOTE: varyings are packed, so if compmask is 0xb
357 * then first, third, and fourth component occupy
358 * three consecutive varying slots:
360 unsigned compmask
= fp
->inputs
[j
].compmask
;
362 uint32_t inloc
= fp
->inputs
[j
].inloc
;
364 if (fp
->inputs
[j
].flat
||
365 (fp
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
366 uint32_t loc
= inloc
;
368 for (i
= 0; i
< 4; i
++) {
369 if (compmask
& (1 << i
)) {
370 vinterp
[loc
/ 16] |= FLAT
<< ((loc
% 16) * 2);
371 flatshade
[loc
/ 32] |= 1 << (loc
% 32);
377 bool coord_mode
= emit
->sprite_coord_mode
;
378 if (ir3_point_sprite(fp
, j
, emit
->sprite_coord_enable
, &coord_mode
)) {
379 /* mask is two 2-bit fields, where:
382 * '11' -> 1 - T (flip mode)
384 unsigned mask
= coord_mode
? 0b1101 : 0b1001;
385 uint32_t loc
= inloc
;
386 if (compmask
& 0x1) {
387 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
390 if (compmask
& 0x2) {
391 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
394 if (compmask
& 0x4) {
396 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
399 if (compmask
& 0x8) {
401 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
407 OUT_PKT0(ring
, REG_A3XX_VPC_ATTR
, 2);
408 OUT_RING(ring
, A3XX_VPC_ATTR_TOTALATTR(fp
->total_in
) |
409 A3XX_VPC_ATTR_THRDASSIGN(1) |
410 A3XX_VPC_ATTR_LMSIZE(1) |
411 COND(vp
->writes_psize
, A3XX_VPC_ATTR_PSIZE
));
412 OUT_RING(ring
, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp
->total_in
) |
413 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp
->total_in
));
415 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
416 OUT_RING(ring
, vinterp
[0]); /* VPC_VARYING_INTERP[0].MODE */
417 OUT_RING(ring
, vinterp
[1]); /* VPC_VARYING_INTERP[1].MODE */
418 OUT_RING(ring
, vinterp
[2]); /* VPC_VARYING_INTERP[2].MODE */
419 OUT_RING(ring
, vinterp
[3]); /* VPC_VARYING_INTERP[3].MODE */
421 OUT_PKT0(ring
, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
422 OUT_RING(ring
, vpsrepl
[0]); /* VPC_VARYING_PS_REPL[0].MODE */
423 OUT_RING(ring
, vpsrepl
[1]); /* VPC_VARYING_PS_REPL[1].MODE */
424 OUT_RING(ring
, vpsrepl
[2]); /* VPC_VARYING_PS_REPL[2].MODE */
425 OUT_RING(ring
, vpsrepl
[3]); /* VPC_VARYING_PS_REPL[3].MODE */
427 OUT_PKT0(ring
, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0
, 2);
428 OUT_RING(ring
, flatshade
[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
429 OUT_RING(ring
, flatshade
[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
432 if (vpbuffer
== BUFFER
)
433 emit_shader(ring
, vp
);
435 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
436 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
438 if (!emit
->binning_pass
) {
439 if (fpbuffer
== BUFFER
)
440 emit_shader(ring
, fp
);
442 OUT_PKT0(ring
, REG_A3XX_VFD_PERFCOUNTER0_SELECT
, 1);
443 OUT_RING(ring
, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
448 fd3_prog_init(struct pipe_context
*pctx
)