src/gallium/drivers/freedreno/a3xx/fd3_program.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef FD3_PROGRAM_H_
  30 #define FD3_PROGRAM_H_
  31
  32 #include "pipe/p_context.h"
  33
  34 #include "freedreno_context.h"
  35
  36 #include "ir-a3xx.h"
  37 #include "disasm.h"
  38
  39 struct fd3_shader_stateobj {
  40         enum shader_t type;
  41
  42         struct fd_bo *bo;
  43
  44         struct ir3_shader_info info;
  45         struct ir3_shader *ir;
  46
  47         /* is shader using (or more precisely, is color_regid) half-
  48          * precision register?
  49          */
  50         bool half_precision;
  51
  52         /* special output register locations: */
  53         uint8_t pos_regid, psize_regid, color_regid;
  54
  55         /* the instructions length is in units of instruction groups
  56          * (4 instructions, 8 dwords):
  57          */
  58         unsigned instrlen;
  59
  60         /* the constants length is in units of vec4's, and is the sum of
  61          * the uniforms and the built-in compiler constants
  62          */
  63         unsigned constlen;
  64
  65         /* About Linkage:
  66          *   + Let the frag shader determine the position/compmask for the
  67          *     varyings, since it is the place where we know if the varying
  68          *     is actually used, and if so, which components are used.  So
  69          *     what the hw calls "outloc" is taken from the "inloc" of the
  70          *     frag shader.
  71          *   + From the vert shader, we only need the output regid
  72          */
  73
  74         /* varyings/outputs: */
  75         unsigned outputs_count;
  76         struct {
  77                 uint8_t regid;
  78         } outputs[16];
  79
  80         /* vertices/inputs: */
  81         unsigned inputs_count;
  82         struct {
  83                 uint8_t regid;
  84                 uint8_t compmask;
  85                 /* in theory inloc of fs should match outloc of vs: */
  86                 uint8_t inloc;
  87         } inputs[16];
  88
  89         unsigned total_in;       /* sum of inputs (scalar) */
  90
  91         /* samplers: */
  92         unsigned samplers_count;
  93
  94         /* const reg # of first immediate, ie. 1 == c1
  95          * (not regid, because TGSI thinks in terms of vec4 registers,
  96          * not scalar registers)
  97          */
  98         unsigned first_immediate;
  99         unsigned immediates_count;
 100         struct {
 101                 uint32_t val[4];
 102         } immediates[64];
 103
 104         /* so far, only used for blit_prog shader.. values for
 105          * VPC_VARYING_INTERP[i].MODE and VPC_VARYING_PS_REPL[i].MODE
 106          */
 107         uint32_t vinterp[4], vpsrepl[4];
 108 };
 109
 110 void fd3_program_emit(struct fd_ringbuffer *ring,
 111                 struct fd_program_stateobj *prog);
 112
 113 void fd3_prog_init(struct pipe_context *pctx);
 114 void fd3_prog_fini(struct pipe_context *pctx);
 115
 116 #endif /* FD3_PROGRAM_H_ */