src/gallium/drivers/freedreno/a3xx/ir-a3xx.h

   1 /*
   2  * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef IR3_H_
  25 #define IR3_H_
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29
  30 #include "instr-a3xx.h"
  31
  32 /* low level intermediate representation of an adreno shader program */
  33
  34 struct ir3_shader;
  35
  36 struct ir3_shader * fd_asm_parse(const char *src);
  37
  38 struct ir3_shader_info {
  39         uint16_t sizedwords;
  40         /* NOTE: max_reg, etc, does not include registers not touched
  41          * by the shader (ie. vertex fetched via VFD_DECODE but not
  42          * touched by shader)
  43          */
  44         int8_t   max_reg;   /* highest GPR # used by shader */
  45         int8_t   max_half_reg;
  46         int8_t   max_const;
  47 };
  48
  49 struct ir3_register {
  50         enum {
  51                 IR3_REG_CONST  = 0x001,
  52                 IR3_REG_IMMED  = 0x002,
  53                 IR3_REG_HALF   = 0x004,
  54                 IR3_REG_RELATIV= 0x008,
  55                 IR3_REG_R      = 0x010,
  56                 IR3_REG_NEGATE = 0x020,
  57                 IR3_REG_ABS    = 0x040,
  58                 IR3_REG_EVEN   = 0x080,
  59                 IR3_REG_POS_INF= 0x100,
  60                 /* (ei) flag, end-input?  Set on last bary, presumably to signal
  61                  * that the shader needs no more input:
  62                  */
  63                 IR3_REG_EI     = 0x200,
  64         } flags;
  65         union {
  66                 /* normal registers:
  67                  * the component is in the low two bits of the reg #, so
  68                  * rN.x becomes: (N << 2) | x
  69                  */
  70                 int num;
  71                 /* immediate: */
  72                 int     iim_val;
  73                 float   fim_val;
  74                 /* relative: */
  75                 int offset;
  76         };
  77
  78         /* used for cat5 instructions, but also for internal/IR level
  79          * tracking of what registers are read/written by an instruction.
  80          * wrmask may be a bad name since it is used to represent both
  81          * src and dst that touch multiple adjacent registers.
  82          */
  83         int wrmask;
  84 };
  85
  86 struct ir3_instruction {
  87         struct ir3_shader *shader;
  88         int category;
  89         opc_t opc;
  90         enum {
  91                 /* (sy) flag is set on first instruction, and after sample
  92                  * instructions (probably just on RAW hazard).
  93                  */
  94                 IR3_INSTR_SY    = 0x001,
  95                 /* (ss) flag is set on first instruction, and first instruction
  96                  * to depend on the result of "long" instructions (RAW hazard):
  97                  *
  98                  *   rcp, rsq, log2, exp2, sin, cos, sqrt
  99                  *
 100                  * It seems to synchronize until all in-flight instructions are
 101                  * completed, for example:
 102                  *
 103                  *   rsq hr1.w, hr1.w
 104                  *   add.f hr2.z, (neg)hr2.z, hc0.y
 105                  *   mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
 106                  *   rsq hr2.x, hr2.x
 107                  *   (rpt1)nop
 108                  *   mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
 109                  *   nop
 110                  *   mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
 111                  *   (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
 112                  *   (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
 113                  *
 114                  * The last mul.f does not have (ss) set, presumably because the
 115                  * (ss) on the previous instruction does the job.
 116                  *
 117                  * The blob driver also seems to set it on WAR hazards, although
 118                  * not really clear if this is needed or just blob compiler being
 119                  * sloppy.  So far I haven't found a case where removing the (ss)
 120                  * causes problems for WAR hazard, but I could just be getting
 121                  * lucky:
 122                  *
 123                  *   rcp r1.y, r3.y
 124                  *   (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
 125                  *
 126                  */
 127                 IR3_INSTR_SS    = 0x002,
 128                 /* (jp) flag is set on jump targets:
 129                  */
 130                 IR3_INSTR_JP    = 0x004,
 131                 IR3_INSTR_UL    = 0x008,
 132                 IR3_INSTR_3D    = 0x010,
 133                 IR3_INSTR_A     = 0x020,
 134                 IR3_INSTR_O     = 0x040,
 135                 IR3_INSTR_P     = 0x080,
 136                 IR3_INSTR_S     = 0x100,
 137                 IR3_INSTR_S2EN  = 0x200,
 138         } flags;
 139         int repeat;
 140         unsigned regs_count;
 141         struct ir3_register *regs[4];
 142         union {
 143                 struct {
 144                         char inv;
 145                         char comp;
 146                         int  immed;
 147                 } cat0;
 148                 struct {
 149                         type_t src_type, dst_type;
 150                 } cat1;
 151                 struct {
 152                         enum {
 153                                 IR3_COND_LT = 0,
 154                                 IR3_COND_LE = 1,
 155                                 IR3_COND_GT = 2,
 156                                 IR3_COND_GE = 3,
 157                                 IR3_COND_EQ = 4,
 158                                 IR3_COND_NE = 5,
 159                         } condition;
 160                 } cat2;
 161                 struct {
 162                         unsigned samp, tex;
 163                         type_t type;
 164                 } cat5;
 165                 struct {
 166                         type_t type;
 167                         int offset;
 168                         int iim_val;
 169                 } cat6;
 170         };
 171 };
 172
 173 #define MAX_INSTRS 1024
 174
 175 struct ir3_shader {
 176         unsigned instrs_count;
 177         struct ir3_instruction *instrs[MAX_INSTRS];
 178         uint32_t heap[128 * MAX_INSTRS];
 179         unsigned heap_idx;
 180 };
 181
 182 struct ir3_shader * ir3_shader_create(void);
 183 void ir3_shader_destroy(struct ir3_shader *shader);
 184 void * ir3_shader_assemble(struct ir3_shader *shader,
 185                 struct ir3_shader_info *info);
 186
 187 struct ir3_instruction * ir3_instr_create(struct ir3_shader *shader,
 188                 int category, opc_t opc);
 189 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
 190
 191 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
 192                 int num, int flags);
 193
 194 #endif /* IR3_H_ */