src/gallium/drivers/freedreno/a3xx/ir3.h

   1 /*
   2  * Copyright (c) 2013 Rob Clark <robdclark@gmail.com>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef IR3_H_
  25 #define IR3_H_
  26
  27 #include <stdint.h>
  28 #include <stdbool.h>
  29
  30 #include "instr-a3xx.h"
  31 #include "disasm.h"  /* TODO move 'enum shader_t' somewhere else.. */
  32
  33 /* low level intermediate representation of an adreno shader program */
  34
  35 struct ir3_shader;
  36 struct ir3_instruction;
  37 struct ir3_block;
  38
  39 struct ir3_shader * fd_asm_parse(const char *src);
  40
  41 struct ir3_shader_info {
  42         uint16_t sizedwords;
  43         uint16_t instrs_count;   /* expanded to account for rpt's */
  44         /* NOTE: max_reg, etc, does not include registers not touched
  45          * by the shader (ie. vertex fetched via VFD_DECODE but not
  46          * touched by shader)
  47          */
  48         int8_t   max_reg;   /* highest GPR # used by shader */
  49         int8_t   max_half_reg;
  50         int8_t   max_const;
  51 };
  52
  53 struct ir3_register {
  54         enum {
  55                 IR3_REG_CONST  = 0x001,
  56                 IR3_REG_IMMED  = 0x002,
  57                 IR3_REG_HALF   = 0x004,
  58                 IR3_REG_RELATIV= 0x008,
  59                 IR3_REG_R      = 0x010,
  60                 IR3_REG_NEGATE = 0x020,
  61                 IR3_REG_ABS    = 0x040,
  62                 IR3_REG_EVEN   = 0x080,
  63                 IR3_REG_POS_INF= 0x100,
  64                 /* (ei) flag, end-input?  Set on last bary, presumably to signal
  65                  * that the shader needs no more input:
  66                  */
  67                 IR3_REG_EI     = 0x200,
  68         } flags;
  69         union {
  70                 /* normal registers:
  71                  * the component is in the low two bits of the reg #, so
  72                  * rN.x becomes: (N << 2) | x
  73                  */
  74                 int num;
  75                 /* immediate: */
  76                 int     iim_val;
  77                 float   fim_val;
  78                 /* relative: */
  79                 int offset;
  80         };
  81
  82         /* used for cat5 instructions, but also for internal/IR level
  83          * tracking of what registers are read/written by an instruction.
  84          * wrmask may be a bad name since it is used to represent both
  85          * src and dst that touch multiple adjacent registers.
  86          */
  87         int wrmask;
  88 };
  89
  90 struct ir3_instruction {
  91         struct ir3_block *block;
  92         int category;
  93         opc_t opc;
  94         enum {
  95                 /* (sy) flag is set on first instruction, and after sample
  96                  * instructions (probably just on RAW hazard).
  97                  */
  98                 IR3_INSTR_SY    = 0x001,
  99                 /* (ss) flag is set on first instruction, and first instruction
 100                  * to depend on the result of "long" instructions (RAW hazard):
 101                  *
 102                  *   rcp, rsq, log2, exp2, sin, cos, sqrt
 103                  *
 104                  * It seems to synchronize until all in-flight instructions are
 105                  * completed, for example:
 106                  *
 107                  *   rsq hr1.w, hr1.w
 108                  *   add.f hr2.z, (neg)hr2.z, hc0.y
 109                  *   mul.f hr2.w, (neg)hr2.y, (neg)hr2.y
 110                  *   rsq hr2.x, hr2.x
 111                  *   (rpt1)nop
 112                  *   mad.f16 hr2.w, hr2.z, hr2.z, hr2.w
 113                  *   nop
 114                  *   mad.f16 hr2.w, (neg)hr0.w, (neg)hr0.w, hr2.w
 115                  *   (ss)(rpt2)mul.f hr1.x, (r)hr1.x, hr1.w
 116                  *   (rpt2)mul.f hr0.x, (neg)(r)hr0.x, hr2.x
 117                  *
 118                  * The last mul.f does not have (ss) set, presumably because the
 119                  * (ss) on the previous instruction does the job.
 120                  *
 121                  * The blob driver also seems to set it on WAR hazards, although
 122                  * not really clear if this is needed or just blob compiler being
 123                  * sloppy.  So far I haven't found a case where removing the (ss)
 124                  * causes problems for WAR hazard, but I could just be getting
 125                  * lucky:
 126                  *
 127                  *   rcp r1.y, r3.y
 128                  *   (ss)(rpt2)mad.f32 r3.y, (r)c9.x, r1.x, (r)r3.z
 129                  *
 130                  */
 131                 IR3_INSTR_SS    = 0x002,
 132                 /* (jp) flag is set on jump targets:
 133                  */
 134                 IR3_INSTR_JP    = 0x004,
 135                 IR3_INSTR_UL    = 0x008,
 136                 IR3_INSTR_3D    = 0x010,
 137                 IR3_INSTR_A     = 0x020,
 138                 IR3_INSTR_O     = 0x040,
 139                 IR3_INSTR_P     = 0x080,
 140                 IR3_INSTR_S     = 0x100,
 141                 IR3_INSTR_S2EN  = 0x200,
 142         } flags;
 143         int repeat;
 144         unsigned regs_count;
 145         struct ir3_register *regs[5];
 146         union {
 147                 struct {
 148                         char inv;
 149                         char comp;
 150                         int  immed;
 151                 } cat0;
 152                 struct {
 153                         type_t src_type, dst_type;
 154                 } cat1;
 155                 struct {
 156                         enum {
 157                                 IR3_COND_LT = 0,
 158                                 IR3_COND_LE = 1,
 159                                 IR3_COND_GT = 2,
 160                                 IR3_COND_GE = 3,
 161                                 IR3_COND_EQ = 4,
 162                                 IR3_COND_NE = 5,
 163                         } condition;
 164                 } cat2;
 165                 struct {
 166                         unsigned samp, tex;
 167                         type_t type;
 168                 } cat5;
 169                 struct {
 170                         type_t type;
 171                         int offset;
 172                         int iim_val;
 173                 } cat6;
 174         };
 175 #ifdef DEBUG
 176         uint32_t serialno;
 177 #endif
 178 };
 179
 180 #define MAX_INSTRS 1024
 181
 182 struct ir3_shader {
 183         unsigned instrs_count;
 184         struct ir3_instruction *instrs[MAX_INSTRS];
 185         uint32_t heap[128 * MAX_INSTRS];
 186         unsigned heap_idx;
 187 };
 188
 189 struct ir3_block {
 190         struct ir3_shader *shader;
 191         unsigned ntemporaries, ninputs, noutputs;
 192         /* maps TGSI_FILE_TEMPORARY index back to the assigning instruction: */
 193         struct ir3_instruction **temporaries;
 194         struct ir3_instruction **inputs;
 195         struct ir3_instruction **outputs;
 196         struct ir3_block *parent;
 197         struct ir3_instruction *head;
 198 };
 199
 200 struct ir3_shader * ir3_shader_create(void);
 201 void ir3_shader_destroy(struct ir3_shader *shader);
 202 void * ir3_shader_assemble(struct ir3_shader *shader,
 203                 struct ir3_shader_info *info);
 204
 205 struct ir3_block * ir3_block_create(struct ir3_shader *shader,
 206                 unsigned ntmp, unsigned nin, unsigned nout);
 207
 208 struct ir3_instruction * ir3_instr_create(struct ir3_block *block,
 209                 int category, opc_t opc);
 210 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
 211
 212 struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
 213                 int num, int flags);
 214
 215
 216 /* comp:
 217  *   0 - x
 218  *   1 - y
 219  *   2 - z
 220  *   3 - w
 221  */
 222 static inline uint32_t regid(int num, int comp)
 223 {
 224         return (num << 2) | (comp & 0x3);
 225 }
 226
 227 static inline uint32_t reg_num(struct ir3_register *reg)
 228 {
 229         return reg->num >> 2;
 230 }
 231
 232 static inline uint32_t reg_comp(struct ir3_register *reg)
 233 {
 234         return reg->num & 0x3;
 235 }
 236
 237 static inline bool is_alu(struct ir3_instruction *instr)
 238 {
 239         return (1 <= instr->category) && (instr->category <= 3);
 240 }
 241
 242 static inline bool is_sfu(struct ir3_instruction *instr)
 243 {
 244         return (instr->category == 4);
 245 }
 246
 247 static inline bool is_tex(struct ir3_instruction *instr)
 248 {
 249         return (instr->category == 5);
 250 }
 251
 252 static inline bool is_input(struct ir3_instruction *instr)
 253 {
 254         return (instr->category == 2) && (instr->opc == OPC_BARY_F);
 255 }
 256
 257 static inline bool is_gpr(struct ir3_register *reg)
 258 {
 259         return !(reg->flags & (IR3_REG_CONST | IR3_REG_IMMED));
 260 }
 261
 262 /* TODO combine is_gpr()/reg_gpr().. */
 263 static inline bool reg_gpr(struct ir3_register *r)
 264 {
 265         if (r->flags & (IR3_REG_CONST | IR3_REG_IMMED | IR3_REG_RELATIV))
 266                 return false;
 267         if ((reg_num(r) == REG_A0) || (reg_num(r) == REG_P0))
 268                 return false;
 269         return true;
 270 }
 271
 272 #ifndef ARRAY_SIZE
 273 #  define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
 274 #endif
 275
 276 /* ************************************************************************* */
 277 /* split this out or find some helper to use.. like main/bitset.h.. */
 278
 279 #include <string.h>
 280
 281 #define MAX_REG 256
 282
 283 typedef uint8_t regmask_t[2 * MAX_REG / 8];
 284
 285 static inline unsigned regmask_idx(struct ir3_register *reg)
 286 {
 287         unsigned num = reg->num;
 288         assert(num < MAX_REG);
 289         if (reg->flags & IR3_REG_HALF)
 290                 num += MAX_REG;
 291         return num;
 292 }
 293
 294 static inline void regmask_init(regmask_t *regmask)
 295 {
 296         memset(regmask, 0, sizeof(*regmask));
 297 }
 298
 299 static inline void regmask_set(regmask_t *regmask, struct ir3_register *reg)
 300 {
 301         unsigned idx = regmask_idx(reg);
 302         unsigned i;
 303         for (i = 0; i < 4; i++, idx++)
 304                 if (reg->wrmask & (1 << i))
 305                         (*regmask)[idx / 8] |= 1 << (idx % 8);
 306 }
 307
 308 /* set bits in a if not set in b, conceptually:
 309  *   a |= (reg & ~b)
 310  */
 311 static inline void regmask_set_if_not(regmask_t *a,
 312                 struct ir3_register *reg, regmask_t *b)
 313 {
 314         unsigned idx = regmask_idx(reg);
 315         unsigned i;
 316         for (i = 0; i < 4; i++, idx++)
 317                 if (reg->wrmask & (1 << i))
 318                         if (!((*b)[idx / 8] & (1 << (idx % 8))))
 319                                 (*a)[idx / 8] |= 1 << (idx % 8);
 320 }
 321
 322 static inline unsigned regmask_get(regmask_t *regmask,
 323                 struct ir3_register *reg)
 324 {
 325         unsigned idx = regmask_idx(reg);
 326         unsigned i;
 327         for (i = 0; i < 4; i++, idx++)
 328                 if (reg->wrmask & (1 << i))
 329                         if ((*regmask)[idx / 8] & (1 << (idx % 8)))
 330                                 return true;
 331         return false;
 332 }
 333
 334 /* ************************************************************************* */
 335
 336 #endif /* IR3_H_ */