projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno/a4xx: use hardware RGTC texture samplers
[mesa.git] / src / gallium / drivers / freedreno / a4xx / a4xx.xml.h
1 #ifndef A4XX_XML
2 #define A4XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 68291 bytes, from 2015-11-17 16:39:59)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 64038 bytes, from 2015-11-17 16:37:36)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19
20 Copyright (C) 2013-2015 by the following authors:
21 - Rob Clark <robdclark@gmail.com> (robclark)
22
23 Permission is hereby granted, free of charge, to any person obtaining
24 a copy of this software and associated documentation files (the
25 "Software"), to deal in the Software without restriction, including
26 without limitation the rights to use, copy, modify, merge, publish,
27 distribute, sublicense, and/or sell copies of the Software, and to
28 permit persons to whom the Software is furnished to do so, subject to
29 the following conditions:
30
31 The above copyright notice and this permission notice (including the
32 next paragraph) shall be included in all copies or substantial
33 portions of the Software.
34
35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44
45 enum a4xx_color_fmt {
46 RB4_A8_UNORM = 1,
47 RB4_R8_UNORM = 2,
48 RB4_R4G4B4A4_UNORM = 8,
49 RB4_R5G5B5A1_UNORM = 10,
50 RB4_R5G6B5_UNORM = 14,
51 RB4_R8G8_UNORM = 15,
52 RB4_R8G8_SNORM = 16,
53 RB4_R8G8_UINT = 17,
54 RB4_R8G8_SINT = 18,
55 RB4_R16_UNORM = 19,
56 RB4_R16_SNORM = 20,
57 RB4_R16_FLOAT = 21,
58 RB4_R16_UINT = 22,
59 RB4_R16_SINT = 23,
60 RB4_R8G8B8_UNORM = 25,
61 RB4_R8G8B8A8_UNORM = 26,
62 RB4_R8G8B8A8_SNORM = 28,
63 RB4_R8G8B8A8_UINT = 29,
64 RB4_R8G8B8A8_SINT = 30,
65 RB4_R10G10B10A2_UNORM = 31,
66 RB4_R10G10B10A2_UINT = 34,
67 RB4_R11G11B10_FLOAT = 39,
68 RB4_R16G16_UNORM = 40,
69 RB4_R16G16_SNORM = 41,
70 RB4_R16G16_FLOAT = 42,
71 RB4_R16G16_UINT = 43,
72 RB4_R16G16_SINT = 44,
73 RB4_R32_FLOAT = 45,
74 RB4_R32_UINT = 46,
75 RB4_R32_SINT = 47,
76 RB4_R16G16B16A16_UNORM = 52,
77 RB4_R16G16B16A16_SNORM = 53,
78 RB4_R16G16B16A16_FLOAT = 54,
79 RB4_R16G16B16A16_UINT = 55,
80 RB4_R16G16B16A16_SINT = 56,
81 RB4_R32G32_FLOAT = 57,
82 RB4_R32G32_UINT = 58,
83 RB4_R32G32_SINT = 59,
84 RB4_R32G32B32A32_FLOAT = 60,
85 RB4_R32G32B32A32_UINT = 61,
86 RB4_R32G32B32A32_SINT = 62,
87 };
88
89 enum a4xx_tile_mode {
90 TILE4_LINEAR = 0,
91 TILE4_3 = 3,
92 };
93
94 enum a4xx_rb_blend_opcode {
95 BLEND_DST_PLUS_SRC = 0,
96 BLEND_SRC_MINUS_DST = 1,
97 BLEND_DST_MINUS_SRC = 2,
98 BLEND_MIN_DST_SRC = 3,
99 BLEND_MAX_DST_SRC = 4,
100 };
101
102 enum a4xx_vtx_fmt {
103 VFMT4_32_FLOAT = 1,
104 VFMT4_32_32_FLOAT = 2,
105 VFMT4_32_32_32_FLOAT = 3,
106 VFMT4_32_32_32_32_FLOAT = 4,
107 VFMT4_16_FLOAT = 5,
108 VFMT4_16_16_FLOAT = 6,
109 VFMT4_16_16_16_FLOAT = 7,
110 VFMT4_16_16_16_16_FLOAT = 8,
111 VFMT4_32_FIXED = 9,
112 VFMT4_32_32_FIXED = 10,
113 VFMT4_32_32_32_FIXED = 11,
114 VFMT4_32_32_32_32_FIXED = 12,
115 VFMT4_16_SINT = 16,
116 VFMT4_16_16_SINT = 17,
117 VFMT4_16_16_16_SINT = 18,
118 VFMT4_16_16_16_16_SINT = 19,
119 VFMT4_16_UINT = 20,
120 VFMT4_16_16_UINT = 21,
121 VFMT4_16_16_16_UINT = 22,
122 VFMT4_16_16_16_16_UINT = 23,
123 VFMT4_16_SNORM = 24,
124 VFMT4_16_16_SNORM = 25,
125 VFMT4_16_16_16_SNORM = 26,
126 VFMT4_16_16_16_16_SNORM = 27,
127 VFMT4_16_UNORM = 28,
128 VFMT4_16_16_UNORM = 29,
129 VFMT4_16_16_16_UNORM = 30,
130 VFMT4_16_16_16_16_UNORM = 31,
131 VFMT4_32_UINT = 32,
132 VFMT4_32_32_UINT = 33,
133 VFMT4_32_32_32_UINT = 34,
134 VFMT4_32_32_32_32_UINT = 35,
135 VFMT4_32_SINT = 36,
136 VFMT4_32_32_SINT = 37,
137 VFMT4_32_32_32_SINT = 38,
138 VFMT4_32_32_32_32_SINT = 39,
139 VFMT4_8_UINT = 40,
140 VFMT4_8_8_UINT = 41,
141 VFMT4_8_8_8_UINT = 42,
142 VFMT4_8_8_8_8_UINT = 43,
143 VFMT4_8_UNORM = 44,
144 VFMT4_8_8_UNORM = 45,
145 VFMT4_8_8_8_UNORM = 46,
146 VFMT4_8_8_8_8_UNORM = 47,
147 VFMT4_8_SINT = 48,
148 VFMT4_8_8_SINT = 49,
149 VFMT4_8_8_8_SINT = 50,
150 VFMT4_8_8_8_8_SINT = 51,
151 VFMT4_8_SNORM = 52,
152 VFMT4_8_8_SNORM = 53,
153 VFMT4_8_8_8_SNORM = 54,
154 VFMT4_8_8_8_8_SNORM = 55,
155 VFMT4_10_10_10_2_UINT = 60,
156 VFMT4_10_10_10_2_UNORM = 61,
157 VFMT4_10_10_10_2_SINT = 62,
158 VFMT4_10_10_10_2_SNORM = 63,
159 };
160
161 enum a4xx_tex_fmt {
162 TFMT4_5_6_5_UNORM = 11,
163 TFMT4_5_5_5_1_UNORM = 9,
164 TFMT4_4_4_4_4_UNORM = 8,
165 TFMT4_X8Z24_UNORM = 71,
166 TFMT4_10_10_10_2_UNORM = 33,
167 TFMT4_A8_UNORM = 3,
168 TFMT4_L8_A8_UNORM = 13,
169 TFMT4_8_UNORM = 4,
170 TFMT4_8_8_UNORM = 14,
171 TFMT4_8_8_8_8_UNORM = 28,
172 TFMT4_8_SNORM = 5,
173 TFMT4_8_8_SNORM = 15,
174 TFMT4_8_8_8_8_SNORM = 29,
175 TFMT4_8_UINT = 6,
176 TFMT4_8_8_UINT = 16,
177 TFMT4_8_8_8_8_UINT = 30,
178 TFMT4_8_SINT = 7,
179 TFMT4_8_8_SINT = 17,
180 TFMT4_8_8_8_8_SINT = 31,
181 TFMT4_16_UNORM = 18,
182 TFMT4_16_16_UNORM = 38,
183 TFMT4_16_16_16_16_UNORM = 51,
184 TFMT4_16_SNORM = 19,
185 TFMT4_16_16_SNORM = 39,
186 TFMT4_16_16_16_16_SNORM = 52,
187 TFMT4_16_UINT = 21,
188 TFMT4_16_16_UINT = 41,
189 TFMT4_16_16_16_16_UINT = 54,
190 TFMT4_16_SINT = 22,
191 TFMT4_16_16_SINT = 42,
192 TFMT4_16_16_16_16_SINT = 55,
193 TFMT4_32_UINT = 44,
194 TFMT4_32_32_UINT = 57,
195 TFMT4_32_32_32_32_UINT = 64,
196 TFMT4_32_SINT = 45,
197 TFMT4_32_32_SINT = 58,
198 TFMT4_32_32_32_32_SINT = 65,
199 TFMT4_16_FLOAT = 20,
200 TFMT4_16_16_FLOAT = 40,
201 TFMT4_16_16_16_16_FLOAT = 53,
202 TFMT4_32_FLOAT = 43,
203 TFMT4_32_32_FLOAT = 56,
204 TFMT4_32_32_32_32_FLOAT = 63,
205 TFMT4_9_9_9_E5_FLOAT = 32,
206 TFMT4_11_11_10_FLOAT = 37,
207 TFMT4_DXT1 = 86,
208 TFMT4_DXT3 = 87,
209 TFMT4_DXT5 = 88,
210 TFMT4_RGTC1_UNORM = 90,
211 TFMT4_RGTC1_SNORM = 91,
212 TFMT4_RGTC2_UNORM = 94,
213 TFMT4_RGTC2_SNORM = 95,
214 TFMT4_BPTC_UFLOAT = 97,
215 TFMT4_BPTC_FLOAT = 98,
216 TFMT4_BPTC = 99,
217 TFMT4_ATC_RGB = 100,
218 TFMT4_ATC_RGBA_EXPLICIT = 101,
219 TFMT4_ATC_RGBA_INTERPOLATED = 102,
220 TFMT4_ETC2_RG11_UNORM = 103,
221 TFMT4_ETC2_RG11_SNORM = 104,
222 TFMT4_ETC2_R11_UNORM = 105,
223 TFMT4_ETC2_R11_SNORM = 106,
224 TFMT4_ETC1 = 107,
225 TFMT4_ETC2_RGB8 = 108,
226 TFMT4_ETC2_RGBA8 = 109,
227 TFMT4_ETC2_RGB8A1 = 110,
228 TFMT4_ASTC_4x4 = 111,
229 TFMT4_ASTC_5x4 = 112,
230 TFMT4_ASTC_5x5 = 113,
231 TFMT4_ASTC_6x5 = 114,
232 TFMT4_ASTC_6x6 = 115,
233 TFMT4_ASTC_8x5 = 116,
234 TFMT4_ASTC_8x6 = 117,
235 TFMT4_ASTC_8x8 = 118,
236 TFMT4_ASTC_10x5 = 119,
237 TFMT4_ASTC_10x6 = 120,
238 TFMT4_ASTC_10x8 = 121,
239 TFMT4_ASTC_10x10 = 122,
240 TFMT4_ASTC_12x10 = 123,
241 TFMT4_ASTC_12x12 = 124,
242 };
243
244 enum a4xx_tex_fetchsize {
245 TFETCH4_1_BYTE = 0,
246 TFETCH4_2_BYTE = 1,
247 TFETCH4_4_BYTE = 2,
248 TFETCH4_8_BYTE = 3,
249 TFETCH4_16_BYTE = 4,
250 };
251
252 enum a4xx_depth_format {
253 DEPTH4_NONE = 0,
254 DEPTH4_16 = 1,
255 DEPTH4_24_8 = 2,
256 DEPTH4_32 = 3,
257 };
258
259 enum a4xx_tess_spacing {
260 EQUAL_SPACING = 0,
261 ODD_SPACING = 2,
262 EVEN_SPACING = 3,
263 };
264
265 enum a4xx_tex_filter {
266 A4XX_TEX_NEAREST = 0,
267 A4XX_TEX_LINEAR = 1,
268 A4XX_TEX_ANISO = 2,
269 };
270
271 enum a4xx_tex_clamp {
272 A4XX_TEX_REPEAT = 0,
273 A4XX_TEX_CLAMP_TO_EDGE = 1,
274 A4XX_TEX_MIRROR_REPEAT = 2,
275 A4XX_TEX_CLAMP_TO_BORDER = 3,
276 A4XX_TEX_MIRROR_CLAMP = 4,
277 };
278
279 enum a4xx_tex_aniso {
280 A4XX_TEX_ANISO_1 = 0,
281 A4XX_TEX_ANISO_2 = 1,
282 A4XX_TEX_ANISO_4 = 2,
283 A4XX_TEX_ANISO_8 = 3,
284 A4XX_TEX_ANISO_16 = 4,
285 };
286
287 enum a4xx_tex_swiz {
288 A4XX_TEX_X = 0,
289 A4XX_TEX_Y = 1,
290 A4XX_TEX_Z = 2,
291 A4XX_TEX_W = 3,
292 A4XX_TEX_ZERO = 4,
293 A4XX_TEX_ONE = 5,
294 };
295
296 enum a4xx_tex_type {
297 A4XX_TEX_1D = 0,
298 A4XX_TEX_2D = 1,
299 A4XX_TEX_CUBE = 2,
300 A4XX_TEX_3D = 3,
301 };
302
303 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
304 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
305 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
306 {
307 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
308 }
309 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
310 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
311 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
312 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
313 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
314 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
315 #define A4XX_INT0_VFD_ERROR 0x00000040
316 #define A4XX_INT0_CP_SW_INT 0x00000080
317 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
318 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
319 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
320 #define A4XX_INT0_CP_HW_FAULT 0x00000800
321 #define A4XX_INT0_CP_DMA 0x00001000
322 #define A4XX_INT0_CP_IB2_INT 0x00002000
323 #define A4XX_INT0_CP_IB1_INT 0x00004000
324 #define A4XX_INT0_CP_RB_INT 0x00008000
325 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
326 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000
327 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000
328 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000
329 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
330 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
331 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000
332 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
333 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
334
335 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
336
337 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
338
339 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
340
341 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
342
343 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
344
345 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
346
347 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
348
349 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
350
351 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
352
353 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
354 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
355 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
356 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
357 {
358 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
359 }
360 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
361 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
362 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
363 {
364 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
365 }
366
367 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
368
369 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
370
371 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
372
373 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
374
375 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0
376 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
377 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
378 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
379 {
380 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
381 }
382 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
383 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
384 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
385 {
386 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
387 }
388
389 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
390 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
391 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
392
393 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
394 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
395 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
396 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
397 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
398 {
399 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
400 }
401
402 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
403 #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
404 #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
405 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
406 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
407 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
408 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
409 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
410 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
411 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
412 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
413 {
414 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
415 }
416 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
417 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
418
419 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
420
421 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
422 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
423 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
424 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
425 #define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
426 #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
427 #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
428 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
429 {
430 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
431 }
432 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
433 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
434 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
435 {
436 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
437 }
438
439 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
440 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
441 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
442 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
443 {
444 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
445 }
446 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
447 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
448 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
449 {
450 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
451 }
452 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
453 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
454 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
455 {
456 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
457 }
458 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
459 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
460 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
461 {
462 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
463 }
464 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
465 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
466 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
467 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
468 {
469 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
470 }
471
472 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
473
474 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
475 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
476 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
477 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
478 {
479 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
480 }
481
482 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
483 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
484 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
485 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
486 {
487 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
488 }
489 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
490 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
491 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
492 {
493 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
494 }
495 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
496 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
497 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
498 {
499 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
500 }
501 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
502 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
503 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
504 {
505 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
506 }
507 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
508 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
509 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
510 {
511 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
512 }
513 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
514 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
515 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
516 {
517 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
518 }
519
520 #define REG_A4XX_RB_BLEND_RED 0x000020f0
521 #define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff
522 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0
523 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
524 {
525 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
526 }
527 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
528 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
529 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
530 {
531 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
532 }
533
534 #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
535 #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
536 #define A4XX_RB_BLEND_RED_F32__SHIFT 0
537 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
538 {
539 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
540 }
541
542 #define REG_A4XX_RB_BLEND_GREEN 0x000020f2
543 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff
544 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
545 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
546 {
547 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
548 }
549 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
550 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
551 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
552 {
553 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
554 }
555
556 #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
557 #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
558 #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
559 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
560 {
561 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
562 }
563
564 #define REG_A4XX_RB_BLEND_BLUE 0x000020f4
565 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff
566 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
567 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
568 {
569 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
570 }
571 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
572 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
573 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
574 {
575 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
576 }
577
578 #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
579 #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
580 #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
581 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
582 {
583 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
584 }
585
586 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
587 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff
588 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
589 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
590 {
591 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
592 }
593 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
594 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
595 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
596 {
597 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
598 }
599
600 #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
601 #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
602 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
603 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
604 {
605 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
606 }
607
608 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
609 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
610 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
611 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
612 {
613 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
614 }
615 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
616 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
617 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
618 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
619 {
620 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
621 }
622
623 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9
624 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
625 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
626 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
627 {
628 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
629 }
630 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100
631 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
632 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
633 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
634 {
635 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
636 }
637
638 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
639 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
640 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
641 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
642 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
643 {
644 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
645 }
646
647 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
648 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
649 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
650 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
651 {
652 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
653 }
654 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
655 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
656 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
657 {
658 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
659 }
660 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
661 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
662 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
663 {
664 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
665 }
666 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
667 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
668 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
669 {
670 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
671 }
672 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
673 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
674 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
675 {
676 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
677 }
678 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
679 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
680 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
681 {
682 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
683 }
684 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
685 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
686 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
687 {
688 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
689 }
690 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
691 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
692 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
693 {
694 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
695 }
696
697 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc
698 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
699 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
700 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
701 {
702 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
703 }
704 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
705 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
706 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
707 {
708 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
709 }
710 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
711 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
712 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
713 {
714 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
715 }
716 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
717 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
718 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
719 {
720 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
721 }
722
723 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
724 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
725 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
726 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
727 {
728 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
729 }
730
731 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
732 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
733 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
734 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
735 {
736 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
737 }
738
739 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
740 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
741 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
742 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
743 {
744 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
745 }
746 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
747 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
748 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
749 {
750 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
751 }
752 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
753 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
754 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
755 {
756 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
757 }
758 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
759 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
760 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
761 {
762 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
763 }
764 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
765 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
766 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
767 {
768 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
769 }
770 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
771 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
772 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
773 {
774 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
775 }
776
777 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
778 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
779 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
780 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
781 {
782 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
783 }
784 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
785
786 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
787 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
788 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
789 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
790 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
791 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
792 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
793 {
794 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
795 }
796 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
797 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
798 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
799
800 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
801
802 #define REG_A4XX_RB_DEPTH_INFO 0x00002103
803 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
804 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
805 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
806 {
807 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
808 }
809 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
810 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
811 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
812 {
813 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
814 }
815
816 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104
817 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
818 #define A4XX_RB_DEPTH_PITCH__SHIFT 0
819 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
820 {
821 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
822 }
823
824 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
825 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
826 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0
827 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
828 {
829 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
830 }
831
832 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
833 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
834 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
835 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
836 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
837 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
838 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
839 {
840 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
841 }
842 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
843 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
844 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
845 {
846 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
847 }
848 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
849 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
850 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
851 {
852 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
853 }
854 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
855 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
856 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
857 {
858 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
859 }
860 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
861 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
862 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
863 {
864 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
865 }
866 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
867 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
868 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
869 {
870 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
871 }
872 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
873 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
874 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
875 {
876 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
877 }
878 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
879 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
880 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
881 {
882 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
883 }
884
885 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
886 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
887
888 #define REG_A4XX_RB_STENCIL_INFO 0x00002108
889 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
890 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
891 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
892 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
893 {
894 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
895 }
896
897 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109
898 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
899 #define A4XX_RB_STENCIL_PITCH__SHIFT 0
900 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
901 {
902 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
903 }
904
905 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b
906 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
907 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
908 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
909 {
910 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
911 }
912 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
913 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
914 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
915 {
916 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
917 }
918 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
919 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
920 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
921 {
922 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
923 }
924
925 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
926 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
927 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
928 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
929 {
930 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
931 }
932 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
933 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
934 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
935 {
936 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
937 }
938 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
939 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
940 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
941 {
942 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
943 }
944
945 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d
946 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
947 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
948 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0
949 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
950 {
951 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
952 }
953 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
954 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
955 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
956 {
957 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
958 }
959
960 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
961
962 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
963
964 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
965
966 #define REG_A4XX_RBBM_HW_VERSION 0x00000000
967
968 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
969
970 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
971
972 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
973
974 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
975
976 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
977
978 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
979
980 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
981
982 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
983
984 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
985
986 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
987
988 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
989
990 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
991
992 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
993
994 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
995
996 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
997
998 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
999
1000 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
1001
1002 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
1003
1004 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
1005
1006 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
1007
1008 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
1009
1010 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
1011
1012 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
1013
1014 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
1015
1016 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023
1017
1018 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024
1019
1020 #define REG_A4XX_RBBM_AHB_CMD 0x00000025
1021
1022 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
1023
1024 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
1025
1026 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
1027
1028 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
1029
1030 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
1031
1032 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
1033
1034 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037
1035
1036 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
1037
1038 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
1039
1040 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
1041
1042 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
1043
1044 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1045
1046 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
1047
1048 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
1049
1050 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1051
1052 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1053
1054 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1055
1056 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1057
1058 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1059
1060 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1061
1062 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1063
1064 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1065
1066 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1067
1068 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1069
1070 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1071
1072 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1073
1074 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1075
1076 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1077
1078 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1079
1080 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1081
1082 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1083
1084 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1085
1086 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1087
1088 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1089
1090 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1091
1092 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
1093
1094 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
1095
1096 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
1097
1098 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
1099
1100 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
1101
1102 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
1103
1104 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1105
1106 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1107
1108 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
1109
1110 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
1111
1112 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
1113
1114 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
1115
1116 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
1117
1118 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
1119
1120 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
1121
1122 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
1123
1124 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
1125
1126 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
1127
1128 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189
1129
1130 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
1131
1132 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
1133
1134 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
1135
1136 #define REG_A4XX_RBBM_STATUS 0x00000191
1137 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
1138 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1139 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1140 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
1141 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
1142 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
1143 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
1144 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
1145 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1146 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1147 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
1148 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
1149 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
1150 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
1151 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
1152 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
1153 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
1154 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
1155 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1156 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
1157 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
1158
1159 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
1160
1161 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
1162
1163 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
1164
1165 #define REG_A4XX_CP_RB_BASE 0x00000200
1166
1167 #define REG_A4XX_CP_RB_CNTL 0x00000201
1168
1169 #define REG_A4XX_CP_RB_WPTR 0x00000205
1170
1171 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
1172
1173 #define REG_A4XX_CP_RB_RPTR 0x00000204
1174
1175 #define REG_A4XX_CP_IB1_BASE 0x00000206
1176
1177 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207
1178
1179 #define REG_A4XX_CP_IB2_BASE 0x00000208
1180
1181 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209
1182
1183 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
1184
1185 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
1186
1187 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
1188
1189 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
1190
1191 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
1192
1193 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c
1194
1195 #define REG_A4XX_CP_ROQ_DATA 0x0000021d
1196
1197 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e
1198
1199 #define REG_A4XX_CP_MEQ_DATA 0x0000021f
1200
1201 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220
1202
1203 #define REG_A4XX_CP_MERCIU_DATA 0x00000221
1204
1205 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222
1206
1207 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
1208
1209 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
1210
1211 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
1212
1213 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
1214
1215 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227
1216
1217 #define REG_A4XX_CP_PREEMPT 0x0000022a
1218
1219 #define REG_A4XX_CP_CNTL 0x0000022c
1220
1221 #define REG_A4XX_CP_ME_CNTL 0x0000022d
1222
1223 #define REG_A4XX_CP_DEBUG 0x0000022e
1224
1225 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
1226
1227 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
1228
1229 #define REG_A4XX_CP_PROTECT_REG_0 0x00000240
1230
1231 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1232
1233 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1234
1235 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250
1236
1237 #define REG_A4XX_CP_ST_BASE 0x000004c0
1238
1239 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce
1240
1241 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0
1242
1243 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
1244
1245 #define REG_A4XX_CP_HW_FAULT 0x000004d8
1246
1247 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da
1248
1249 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
1250
1251 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
1252
1253 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
1254
1255 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1256
1257 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1258
1259 #define REG_A4XX_SP_VS_STATUS 0x00000ec0
1260
1261 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
1262
1263 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
1264
1265 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
1266 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
1267
1268 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
1269 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
1270 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
1271 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
1272
1273 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
1274 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1275 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1276 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1277 {
1278 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
1279 }
1280 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
1281 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1282 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1283 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1284 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1285 {
1286 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1287 }
1288 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1289 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1290 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1291 {
1292 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1293 }
1294 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1295 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1296 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1297 {
1298 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1299 }
1300 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1301 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
1302 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1303 {
1304 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
1305 }
1306 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1307 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1308
1309 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
1310 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1311 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1312 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1313 {
1314 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
1315 }
1316 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
1317 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
1318 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
1319 {
1320 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
1321 }
1322
1323 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
1324 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
1325 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
1326 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
1327 {
1328 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
1329 }
1330 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
1331 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
1332 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
1333 {
1334 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
1335 }
1336 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
1337 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
1338 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
1339 {
1340 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
1341 }
1342
1343 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1344
1345 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1346 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
1347 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
1348 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
1349 {
1350 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
1351 }
1352 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1353 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
1354 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
1355 {
1356 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
1357 }
1358 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
1359 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
1360 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
1361 {
1362 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
1363 }
1364 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1365 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
1366 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
1367 {
1368 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
1369 }
1370
1371 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1372
1373 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1374 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1375 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
1376 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
1377 {
1378 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
1379 }
1380 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1381 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
1382 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
1383 {
1384 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
1385 }
1386 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1387 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
1388 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
1389 {
1390 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
1391 }
1392 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1393 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
1394 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
1395 {
1396 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
1397 }
1398
1399 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
1400 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1401 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1402 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1403 {
1404 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1405 }
1406 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1407 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1408 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1409 {
1410 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1411 }
1412
1413 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1
1414
1415 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
1416
1417 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
1418
1419 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
1420
1421 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
1422 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
1423 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
1424 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1425 {
1426 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
1427 }
1428 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
1429 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
1430 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1431 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1432 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1433 {
1434 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1435 }
1436 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1437 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1438 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1439 {
1440 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1441 }
1442 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1443 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1444 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1445 {
1446 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1447 }
1448 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1449 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
1450 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1451 {
1452 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
1453 }
1454 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1455 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1456
1457 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
1458 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1459 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1460 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1461 {
1462 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
1463 }
1464 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
1465 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
1466 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
1467
1468 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
1469 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1470 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1471 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1472 {
1473 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1474 }
1475 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1476 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1477 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1478 {
1479 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1480 }
1481
1482 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb
1483
1484 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
1485
1486 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
1487
1488 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
1489
1490 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
1491 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1492 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
1493 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
1494 {
1495 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
1496 }
1497 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
1498 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
1499 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
1500 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
1501 {
1502 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
1503 }
1504 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
1505 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
1506 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
1507 {
1508 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
1509 }
1510
1511 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1512
1513 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1514 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
1515 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
1516 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
1517 {
1518 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
1519 }
1520 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
1521 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
1522 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
1523 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
1524 {
1525 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
1526 }
1527 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
1528
1529 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
1530
1531 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
1532
1533 #define REG_A4XX_SP_CS_OBJ_START 0x00002302
1534
1535 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
1536
1537 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
1538
1539 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
1540
1541 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
1542
1543 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
1544 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1545 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1546 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1547 {
1548 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1549 }
1550 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1551 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1552 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1553 {
1554 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1555 }
1556
1557 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e
1558
1559 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
1560
1561 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
1562
1563 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
1564
1565 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
1566 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
1567 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
1568 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
1569 {
1570 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
1571 }
1572 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1573 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1574 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1575 {
1576 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
1577 }
1578
1579 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1580
1581 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1582 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
1583 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
1584 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
1585 {
1586 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
1587 }
1588 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1589 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
1590 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
1591 {
1592 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
1593 }
1594 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
1595 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
1596 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
1597 {
1598 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
1599 }
1600 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1601 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
1602 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
1603 {
1604 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
1605 }
1606
1607 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1608
1609 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1610 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1611 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
1612 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
1613 {
1614 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
1615 }
1616 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1617 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
1618 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
1619 {
1620 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
1621 }
1622 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1623 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
1624 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
1625 {
1626 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
1627 }
1628 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1629 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
1630 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
1631 {
1632 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
1633 }
1634
1635 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
1636 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1637 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1638 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1639 {
1640 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1641 }
1642 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1643 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1644 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1645 {
1646 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1647 }
1648
1649 #define REG_A4XX_SP_DS_OBJ_START 0x00002335
1650
1651 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
1652
1653 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
1654
1655 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
1656
1657 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341
1658 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
1659 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
1660 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
1661 {
1662 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
1663 }
1664 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
1665 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
1666 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
1667 {
1668 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
1669 }
1670 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1671 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1672 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1673 {
1674 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
1675 }
1676
1677 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1678
1679 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1680 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
1681 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
1682 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
1683 {
1684 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
1685 }
1686 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1687 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
1688 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
1689 {
1690 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
1691 }
1692 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
1693 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
1694 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
1695 {
1696 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
1697 }
1698 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1699 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
1700 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
1701 {
1702 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
1703 }
1704
1705 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1706
1707 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1708 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1709 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
1710 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
1711 {
1712 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
1713 }
1714 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1715 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
1716 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
1717 {
1718 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
1719 }
1720 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1721 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
1722 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
1723 {
1724 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
1725 }
1726 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1727 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
1728 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
1729 {
1730 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
1731 }
1732
1733 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
1734 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1735 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1736 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1737 {
1738 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1739 }
1740 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1741 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1742 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1743 {
1744 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1745 }
1746
1747 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c
1748
1749 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
1750
1751 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
1752
1753 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
1754
1755 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
1756
1757 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
1758
1759 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
1760
1761 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
1762
1763 #define REG_A4XX_VPC_ATTR 0x00002140
1764 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1765 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
1766 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
1767 {
1768 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
1769 }
1770 #define A4XX_VPC_ATTR_PSIZE 0x00000200
1771 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
1772 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1773 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
1774 {
1775 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
1776 }
1777 #define A4XX_VPC_ATTR_ENABLE 0x02000000
1778
1779 #define REG_A4XX_VPC_PACK 0x00002141
1780 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
1781 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
1782 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
1783 {
1784 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
1785 }
1786 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1787 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1788 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
1789 {
1790 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
1791 }
1792 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1793 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1794 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
1795 {
1796 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
1797 }
1798
1799 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1800
1801 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1802
1803 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1804
1805 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1806
1807 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
1808
1809 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00
1810 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1811 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1812 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1813 {
1814 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
1815 }
1816 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1817 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1818 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1819 {
1820 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
1821 }
1822
1823 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
1824
1825 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
1826
1827 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
1828
1829 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1830
1831 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1832 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1833 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1834 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1835 {
1836 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
1837 }
1838 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1839 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1840 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1841 {
1842 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1843 }
1844 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1845 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1846 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1847 {
1848 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
1849 }
1850 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1851 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
1852 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1853 {
1854 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
1855 }
1856
1857 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1858
1859 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1860
1861 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1862
1863 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1864
1865 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
1866
1867 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
1868
1869 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
1870
1871 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
1872
1873 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
1874
1875 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
1876
1877 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
1878
1879 #define REG_A4XX_VFD_CONTROL_0 0x00002200
1880 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
1881 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1882 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1883 {
1884 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1885 }
1886 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
1887 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
1888 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
1889 {
1890 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
1891 }
1892 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
1893 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
1894 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1895 {
1896 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1897 }
1898 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
1899 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
1900 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1901 {
1902 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1903 }
1904
1905 #define REG_A4XX_VFD_CONTROL_1 0x00002201
1906 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1907 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1908 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1909 {
1910 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1911 }
1912 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1913 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1914 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1915 {
1916 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
1917 }
1918 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1919 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1920 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1921 {
1922 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
1923 }
1924
1925 #define REG_A4XX_VFD_CONTROL_2 0x00002202
1926
1927 #define REG_A4XX_VFD_CONTROL_3 0x00002203
1928 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
1929 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
1930 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
1931 {
1932 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
1933 }
1934 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
1935 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
1936 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
1937 {
1938 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
1939 }
1940 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
1941 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
1942 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
1943 {
1944 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
1945 }
1946
1947 #define REG_A4XX_VFD_CONTROL_4 0x00002204
1948
1949 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
1950
1951 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1952
1953 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1954 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1955 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1956 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1957 {
1958 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1959 }
1960 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
1961 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1962 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1963 {
1964 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1965 }
1966 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
1967 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
1968
1969 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
1970
1971 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
1972 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
1973 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
1974 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
1975 {
1976 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
1977 }
1978
1979 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
1980 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
1981 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
1982 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
1983 {
1984 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
1985 }
1986
1987 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1988
1989 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1990 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1991 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1992 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1993 {
1994 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
1995 }
1996 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
1997 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
1998 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
1999 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
2000 {
2001 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
2002 }
2003 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
2004 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
2005 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
2006 {
2007 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
2008 }
2009 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000
2010 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
2011 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
2012 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
2013 {
2014 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
2015 }
2016 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
2017 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
2018 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
2019 {
2020 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
2021 }
2022 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
2023 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
2024
2025 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
2026
2027 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
2028
2029 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
2030
2031 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
2032
2033 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
2034 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
2035 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
2036 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
2037 {
2038 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
2039 }
2040 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
2041 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
2042 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
2043 {
2044 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
2045 }
2046 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
2047 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
2048 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
2049 {
2050 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
2051 }
2052 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
2053 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
2054 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
2055 {
2056 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
2057 }
2058
2059 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
2060
2061 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
2062
2063 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
2064
2065 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
2066
2067 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
2068
2069 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
2070
2071 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
2072
2073 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
2074
2075 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
2076
2077 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
2078
2079 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
2080
2081 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
2082
2083 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
2084
2085 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
2086 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
2087 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
2088
2089 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
2090 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
2091
2092 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
2093 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
2094 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
2095 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
2096 {
2097 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
2098 }
2099 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
2100 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
2101 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
2102 {
2103 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
2104 }
2105
2106 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
2107 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2108 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2109 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2110 {
2111 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2112 }
2113
2114 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
2115 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2116 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2117 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
2118 {
2119 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2120 }
2121
2122 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
2123 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2124 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2125 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2126 {
2127 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2128 }
2129
2130 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
2131 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2132 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2133 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
2134 {
2135 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2136 }
2137
2138 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
2139 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2140 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2141 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2142 {
2143 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2144 }
2145
2146 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
2147 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2148 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2149 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2150 {
2151 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2152 }
2153
2154 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
2155 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2156 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2157 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2158 {
2159 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2160 }
2161 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2162 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2163 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2164 {
2165 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2166 }
2167
2168 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
2169 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2170 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
2171 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
2172 {
2173 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
2174 }
2175
2176 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
2177 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
2178
2179 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
2180 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2181 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2182 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2183 {
2184 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2185 }
2186
2187 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
2188 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2189 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2190 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2191 {
2192 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2193 }
2194
2195 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
2196 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
2197 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
2198 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
2199 {
2200 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
2201 }
2202
2203 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
2204 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
2205 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
2206 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
2207 {
2208 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
2209 }
2210
2211 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
2212 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
2213 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
2214 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
2215 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
2216 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
2217 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
2218 {
2219 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
2220 }
2221 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
2222 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
2223
2224 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
2225 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
2226 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
2227 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
2228 {
2229 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
2230 }
2231 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
2232 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
2233 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
2234 {
2235 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
2236 }
2237 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
2238 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
2239 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
2240 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
2241 {
2242 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
2243 }
2244
2245 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
2246 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2247 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
2248 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
2249 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
2250 {
2251 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
2252 }
2253 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
2254 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
2255 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
2256 {
2257 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
2258 }
2259
2260 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
2261 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2262 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
2263 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
2264 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
2265 {
2266 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
2267 }
2268 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
2269 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
2270 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
2271 {
2272 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
2273 }
2274
2275 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
2276 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2277 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2278 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2279 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2280 {
2281 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2282 }
2283 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2284 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2285 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2286 {
2287 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2288 }
2289
2290 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
2291 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2292 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2293 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2294 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2295 {
2296 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2297 }
2298 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2299 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2300 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2301 {
2302 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2303 }
2304
2305 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
2306 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
2307 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
2308 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
2309 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
2310 {
2311 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
2312 }
2313 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
2314 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
2315 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
2316 {
2317 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
2318 }
2319
2320 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
2321 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
2322 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
2323 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
2324 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
2325 {
2326 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
2327 }
2328 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
2329 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
2330 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
2331 {
2332 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
2333 }
2334
2335 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
2336
2337 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
2338
2339 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
2340
2341 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
2342
2343 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
2344
2345 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
2346
2347 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
2348
2349 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
2350
2351 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
2352
2353 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
2354
2355 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
2356
2357 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
2358
2359 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
2360 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
2361 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
2362 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
2363 {
2364 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
2365 }
2366 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
2367 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
2368 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
2369 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
2370 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
2371 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
2372 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
2373 {
2374 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
2375 }
2376 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
2377 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
2378 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
2379 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
2380
2381 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
2382 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
2383 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
2384 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
2385 {
2386 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
2387 }
2388 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
2389 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
2390 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
2391 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
2392 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
2393 {
2394 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
2395 }
2396 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
2397 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
2398 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
2399 {
2400 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
2401 }
2402
2403 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
2404 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
2405 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
2406 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
2407 {
2408 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
2409 }
2410 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
2411 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
2412 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
2413 {
2414 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
2415 }
2416 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
2417 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
2418 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
2419 {
2420 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
2421 }
2422 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
2423 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
2424 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
2425 {
2426 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
2427 }
2428
2429 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
2430 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
2431 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
2432 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
2433 {
2434 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
2435 }
2436
2437 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
2438
2439 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
2440 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2441 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2442 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2443 {
2444 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
2445 }
2446 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2447 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2448 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2449 {
2450 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2451 }
2452 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
2453 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2454 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2455 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2456 {
2457 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2458 }
2459 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2460 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2461 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2462 {
2463 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
2464 }
2465
2466 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
2467 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2468 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2469 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2470 {
2471 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
2472 }
2473 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2474 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2475 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2476 {
2477 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2478 }
2479 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
2480 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2481 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2482 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2483 {
2484 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2485 }
2486 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2487 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2488 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2489 {
2490 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
2491 }
2492
2493 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
2494 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2495 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2496 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2497 {
2498 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
2499 }
2500 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2501 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2502 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2503 {
2504 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2505 }
2506 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
2507 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2508 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2509 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2510 {
2511 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2512 }
2513 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2514 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2515 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2516 {
2517 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
2518 }
2519
2520 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
2521 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2522 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2523 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2524 {
2525 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
2526 }
2527 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2528 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2529 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2530 {
2531 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2532 }
2533 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
2534 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2535 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2536 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2537 {
2538 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2539 }
2540 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2541 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2542 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2543 {
2544 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
2545 }
2546
2547 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
2548 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2549 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2550 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2551 {
2552 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
2553 }
2554 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2555 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2556 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2557 {
2558 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2559 }
2560 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
2561 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2562 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2563 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2564 {
2565 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2566 }
2567 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2568 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2569 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2570 {
2571 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
2572 }
2573
2574 #define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca
2575
2576 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
2577
2578 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
2579
2580 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
2581
2582 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
2583
2584 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
2585
2586 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
2587
2588 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
2589
2590 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
2591
2592 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
2593
2594 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
2595
2596 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
2597
2598 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
2599
2600 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
2601
2602 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
2603
2604 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
2605
2606 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
2607 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
2608
2609 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
2610
2611 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2612
2613 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2614
2615 #define REG_A4XX_PC_BIN_BASE 0x000021c0
2616
2617 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
2618 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
2619 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
2620 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
2621 {
2622 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
2623 }
2624 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
2625 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
2626 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
2627
2628 #define REG_A4XX_UNKNOWN_21C5 0x000021c5
2629
2630 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6
2631
2632 #define REG_A4XX_PC_GS_PARAM 0x000021e5
2633 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
2634 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
2635 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
2636 {
2637 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
2638 }
2639 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
2640 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
2641 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
2642 {
2643 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
2644 }
2645 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
2646 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
2647 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2648 {
2649 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
2650 }
2651 #define A4XX_PC_GS_PARAM_LAYER 0x80000000
2652
2653 #define REG_A4XX_PC_HS_PARAM 0x000021e7
2654 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
2655 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
2656 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
2657 {
2658 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
2659 }
2660 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
2661 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
2662 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
2663 {
2664 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
2665 }
2666 #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000
2667 #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23
2668 static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2669 {
2670 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
2671 }
2672
2673 #define REG_A4XX_VBIF_VERSION 0x00003000
2674
2675 #define REG_A4XX_VBIF_CLKON 0x00003001
2676 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
2677
2678 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
2679
2680 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
2681
2682 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2683
2684 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2685
2686 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2687
2688 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
2689
2690 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
2691
2692 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2693
2694 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
2695
2696 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
2697
2698 #define REG_A4XX_UNKNOWN_0D01 0x00000d01
2699
2700 #define REG_A4XX_UNKNOWN_0E42 0x00000e42
2701
2702 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
2703
2704 #define REG_A4XX_UNKNOWN_2001 0x00002001
2705
2706 #define REG_A4XX_UNKNOWN_209B 0x0000209b
2707
2708 #define REG_A4XX_UNKNOWN_20EF 0x000020ef
2709
2710 #define REG_A4XX_UNKNOWN_2152 0x00002152
2711
2712 #define REG_A4XX_UNKNOWN_2153 0x00002153
2713
2714 #define REG_A4XX_UNKNOWN_2154 0x00002154
2715
2716 #define REG_A4XX_UNKNOWN_2155 0x00002155
2717
2718 #define REG_A4XX_UNKNOWN_2156 0x00002156
2719
2720 #define REG_A4XX_UNKNOWN_2157 0x00002157
2721
2722 #define REG_A4XX_UNKNOWN_21C3 0x000021c3
2723
2724 #define REG_A4XX_UNKNOWN_21E6 0x000021e6
2725
2726 #define REG_A4XX_UNKNOWN_2209 0x00002209
2727
2728 #define REG_A4XX_UNKNOWN_22D7 0x000022d7
2729
2730 #define REG_A4XX_UNKNOWN_2352 0x00002352
2731
2732 #define REG_A4XX_TEX_SAMP_0 0x00000000
2733 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
2734 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
2735 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
2736 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
2737 {
2738 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
2739 }
2740 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
2741 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
2742 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
2743 {
2744 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
2745 }
2746 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
2747 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
2748 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
2749 {
2750 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
2751 }
2752 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
2753 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
2754 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
2755 {
2756 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
2757 }
2758 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
2759 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
2760 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
2761 {
2762 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
2763 }
2764 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
2765 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
2766 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
2767 {
2768 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
2769 }
2770 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
2771 #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
2772 static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
2773 {
2774 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
2775 }
2776
2777 #define REG_A4XX_TEX_SAMP_1 0x00000001
2778 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
2779 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
2780 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
2781 {
2782 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
2783 }
2784 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
2785 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
2786 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
2787 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
2788 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
2789 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
2790 {
2791 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
2792 }
2793 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
2794 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
2795 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
2796 {
2797 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
2798 }
2799
2800 #define REG_A4XX_TEX_CONST_0 0x00000000
2801 #define A4XX_TEX_CONST_0_TILED 0x00000001
2802 #define A4XX_TEX_CONST_0_SRGB 0x00000004
2803 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2804 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2805 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
2806 {
2807 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
2808 }
2809 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2810 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2811 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
2812 {
2813 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
2814 }
2815 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2816 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2817 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
2818 {
2819 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
2820 }
2821 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2822 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2823 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
2824 {
2825 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
2826 }
2827 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2828 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2829 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
2830 {
2831 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
2832 }
2833 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2834 #define A4XX_TEX_CONST_0_FMT__SHIFT 22
2835 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
2836 {
2837 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
2838 }
2839 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
2840 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29
2841 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
2842 {
2843 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
2844 }
2845
2846 #define REG_A4XX_TEX_CONST_1 0x00000001
2847 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
2848 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
2849 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
2850 {
2851 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
2852 }
2853 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000
2854 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
2855 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
2856 {
2857 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
2858 }
2859
2860 #define REG_A4XX_TEX_CONST_2 0x00000002
2861 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
2862 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
2863 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
2864 {
2865 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
2866 }
2867 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
2868 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9
2869 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
2870 {
2871 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
2872 }
2873 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2874 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30
2875 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
2876 {
2877 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
2878 }
2879
2880 #define REG_A4XX_TEX_CONST_3 0x00000003
2881 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
2882 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
2883 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
2884 {
2885 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
2886 }
2887 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
2888 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
2889 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
2890 {
2891 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
2892 }
2893
2894 #define REG_A4XX_TEX_CONST_4 0x00000004
2895 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
2896 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
2897 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
2898 {
2899 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
2900 }
2901 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
2902 #define A4XX_TEX_CONST_4_BASE__SHIFT 5
2903 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
2904 {
2905 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
2906 }
2907
2908 #define REG_A4XX_TEX_CONST_5 0x00000005
2909
2910 #define REG_A4XX_TEX_CONST_6 0x00000006
2911
2912 #define REG_A4XX_TEX_CONST_7 0x00000007
2913
2914
2915 #endif /* A4XX_XML */