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819f5b14a1777eb9be5459e7cba9384e23c76324
[mesa.git] / src / gallium / drivers / freedreno / a4xx / a4xx.xml.h
1 #ifndef A4XX_XML
2 #define A4XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12)
18
19 Copyright (C) 2013-2015 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
21
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
29
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
33
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43
44 enum a4xx_color_fmt {
45 RB4_A8_UNORM = 1,
46 RB4_R8_UNORM = 2,
47 RB4_R4G4B4A4_UNORM = 8,
48 RB4_R5G5B5A1_UNORM = 10,
49 RB4_R5G6R5_UNORM = 14,
50 RB4_R8G8_UNORM = 15,
51 RB4_R8G8_SNORM = 16,
52 RB4_R8G8_UINT = 17,
53 RB4_R8G8_SINT = 18,
54 RB4_R16_FLOAT = 21,
55 RB4_R16_UINT = 22,
56 RB4_R16_SINT = 23,
57 RB4_R8G8B8_UNORM = 25,
58 RB4_R8G8B8A8_UNORM = 26,
59 RB4_R8G8B8A8_SNORM = 28,
60 RB4_R8G8B8A8_UINT = 29,
61 RB4_R8G8B8A8_SINT = 30,
62 RB4_R10G10B10A2_UNORM = 31,
63 RB4_R10G10B10A2_UINT = 34,
64 RB4_R11G11B10_FLOAT = 39,
65 RB4_R16G16_FLOAT = 42,
66 RB4_R16G16_UINT = 43,
67 RB4_R16G16_SINT = 44,
68 RB4_R32_FLOAT = 45,
69 RB4_R32_UINT = 46,
70 RB4_R32_SINT = 47,
71 RB4_R16G16B16A16_FLOAT = 54,
72 RB4_R16G16B16A16_UINT = 55,
73 RB4_R16G16B16A16_SINT = 56,
74 RB4_R32G32_FLOAT = 57,
75 RB4_R32G32_UINT = 58,
76 RB4_R32G32_SINT = 59,
77 RB4_R32G32B32A32_FLOAT = 60,
78 RB4_R32G32B32A32_UINT = 61,
79 RB4_R32G32B32A32_SINT = 62,
80 };
81
82 enum a4xx_tile_mode {
83 TILE4_LINEAR = 0,
84 TILE4_3 = 3,
85 };
86
87 enum a4xx_rb_blend_opcode {
88 BLEND_DST_PLUS_SRC = 0,
89 BLEND_SRC_MINUS_DST = 1,
90 BLEND_DST_MINUS_SRC = 2,
91 BLEND_MIN_DST_SRC = 3,
92 BLEND_MAX_DST_SRC = 4,
93 };
94
95 enum a4xx_vtx_fmt {
96 VFMT4_32_FLOAT = 1,
97 VFMT4_32_32_FLOAT = 2,
98 VFMT4_32_32_32_FLOAT = 3,
99 VFMT4_32_32_32_32_FLOAT = 4,
100 VFMT4_16_FLOAT = 5,
101 VFMT4_16_16_FLOAT = 6,
102 VFMT4_16_16_16_FLOAT = 7,
103 VFMT4_16_16_16_16_FLOAT = 8,
104 VFMT4_32_FIXED = 9,
105 VFMT4_32_32_FIXED = 10,
106 VFMT4_32_32_32_FIXED = 11,
107 VFMT4_32_32_32_32_FIXED = 12,
108 VFMT4_16_SINT = 16,
109 VFMT4_16_16_SINT = 17,
110 VFMT4_16_16_16_SINT = 18,
111 VFMT4_16_16_16_16_SINT = 19,
112 VFMT4_16_UINT = 20,
113 VFMT4_16_16_UINT = 21,
114 VFMT4_16_16_16_UINT = 22,
115 VFMT4_16_16_16_16_UINT = 23,
116 VFMT4_16_SNORM = 24,
117 VFMT4_16_16_SNORM = 25,
118 VFMT4_16_16_16_SNORM = 26,
119 VFMT4_16_16_16_16_SNORM = 27,
120 VFMT4_16_UNORM = 28,
121 VFMT4_16_16_UNORM = 29,
122 VFMT4_16_16_16_UNORM = 30,
123 VFMT4_16_16_16_16_UNORM = 31,
124 VFMT4_32_UINT = 32,
125 VFMT4_32_32_UINT = 33,
126 VFMT4_32_32_32_UINT = 34,
127 VFMT4_32_32_32_32_UINT = 35,
128 VFMT4_32_SINT = 36,
129 VFMT4_32_32_SINT = 37,
130 VFMT4_32_32_32_SINT = 38,
131 VFMT4_32_32_32_32_SINT = 39,
132 VFMT4_8_UINT = 40,
133 VFMT4_8_8_UINT = 41,
134 VFMT4_8_8_8_UINT = 42,
135 VFMT4_8_8_8_8_UINT = 43,
136 VFMT4_8_UNORM = 44,
137 VFMT4_8_8_UNORM = 45,
138 VFMT4_8_8_8_UNORM = 46,
139 VFMT4_8_8_8_8_UNORM = 47,
140 VFMT4_8_SINT = 48,
141 VFMT4_8_8_SINT = 49,
142 VFMT4_8_8_8_SINT = 50,
143 VFMT4_8_8_8_8_SINT = 51,
144 VFMT4_8_SNORM = 52,
145 VFMT4_8_8_SNORM = 53,
146 VFMT4_8_8_8_SNORM = 54,
147 VFMT4_8_8_8_8_SNORM = 55,
148 VFMT4_10_10_10_2_UINT = 60,
149 VFMT4_10_10_10_2_UNORM = 61,
150 VFMT4_10_10_10_2_SINT = 62,
151 VFMT4_10_10_10_2_SNORM = 63,
152 };
153
154 enum a4xx_tex_fmt {
155 TFMT4_5_6_5_UNORM = 11,
156 TFMT4_5_5_5_1_UNORM = 10,
157 TFMT4_4_4_4_4_UNORM = 8,
158 TFMT4_X8Z24_UNORM = 71,
159 TFMT4_10_10_10_2_UNORM = 33,
160 TFMT4_A8_UNORM = 3,
161 TFMT4_L8_A8_UNORM = 13,
162 TFMT4_8_UNORM = 4,
163 TFMT4_8_8_UNORM = 14,
164 TFMT4_8_8_8_8_UNORM = 28,
165 TFMT4_8_SNORM = 5,
166 TFMT4_8_8_SNORM = 15,
167 TFMT4_8_8_8_8_SNORM = 29,
168 TFMT4_8_UINT = 6,
169 TFMT4_8_8_UINT = 16,
170 TFMT4_8_8_8_8_UINT = 30,
171 TFMT4_8_SINT = 7,
172 TFMT4_8_8_SINT = 17,
173 TFMT4_8_8_8_8_SINT = 31,
174 TFMT4_16_UINT = 21,
175 TFMT4_16_16_UINT = 41,
176 TFMT4_16_16_16_16_UINT = 54,
177 TFMT4_16_SINT = 22,
178 TFMT4_16_16_SINT = 42,
179 TFMT4_16_16_16_16_SINT = 55,
180 TFMT4_32_UINT = 44,
181 TFMT4_32_32_UINT = 57,
182 TFMT4_32_32_32_32_UINT = 64,
183 TFMT4_32_SINT = 45,
184 TFMT4_32_32_SINT = 58,
185 TFMT4_32_32_32_32_SINT = 65,
186 TFMT4_16_FLOAT = 20,
187 TFMT4_16_16_FLOAT = 40,
188 TFMT4_16_16_16_16_FLOAT = 53,
189 TFMT4_32_FLOAT = 43,
190 TFMT4_32_32_FLOAT = 56,
191 TFMT4_32_32_32_32_FLOAT = 63,
192 TFMT4_9_9_9_E5_FLOAT = 32,
193 TFMT4_11_11_10_FLOAT = 37,
194 TFMT4_ATC_RGB = 100,
195 TFMT4_ATC_RGBA_EXPLICIT = 101,
196 TFMT4_ATC_RGBA_INTERPOLATED = 102,
197 TFMT4_ETC2_RG11_UNORM = 103,
198 TFMT4_ETC2_RG11_SNORM = 104,
199 TFMT4_ETC2_R11_UNORM = 105,
200 TFMT4_ETC2_R11_SNORM = 106,
201 TFMT4_ETC1 = 107,
202 TFMT4_ETC2_RGB8 = 108,
203 TFMT4_ETC2_RGBA8 = 109,
204 TFMT4_ETC2_RGB8A1 = 110,
205 TFMT4_ASTC_4x4 = 111,
206 TFMT4_ASTC_5x4 = 112,
207 TFMT4_ASTC_5x5 = 113,
208 TFMT4_ASTC_6x5 = 114,
209 TFMT4_ASTC_6x6 = 115,
210 TFMT4_ASTC_8x5 = 116,
211 TFMT4_ASTC_8x6 = 117,
212 TFMT4_ASTC_8x8 = 118,
213 TFMT4_ASTC_10x5 = 119,
214 TFMT4_ASTC_10x6 = 120,
215 TFMT4_ASTC_10x8 = 121,
216 TFMT4_ASTC_10x10 = 122,
217 TFMT4_ASTC_12x10 = 123,
218 TFMT4_ASTC_12x12 = 124,
219 };
220
221 enum a4xx_tex_fetchsize {
222 TFETCH4_1_BYTE = 0,
223 TFETCH4_2_BYTE = 1,
224 TFETCH4_4_BYTE = 2,
225 TFETCH4_8_BYTE = 3,
226 TFETCH4_16_BYTE = 4,
227 };
228
229 enum a4xx_depth_format {
230 DEPTH4_NONE = 0,
231 DEPTH4_16 = 1,
232 DEPTH4_24_8 = 2,
233 DEPTH4_32 = 3,
234 };
235
236 enum a4xx_tess_spacing {
237 EQUAL_SPACING = 0,
238 ODD_SPACING = 2,
239 EVEN_SPACING = 3,
240 };
241
242 enum a4xx_tex_filter {
243 A4XX_TEX_NEAREST = 0,
244 A4XX_TEX_LINEAR = 1,
245 A4XX_TEX_ANISO = 2,
246 };
247
248 enum a4xx_tex_clamp {
249 A4XX_TEX_REPEAT = 0,
250 A4XX_TEX_CLAMP_TO_EDGE = 1,
251 A4XX_TEX_MIRROR_REPEAT = 2,
252 A4XX_TEX_CLAMP_TO_BORDER = 3,
253 A4XX_TEX_MIRROR_CLAMP = 4,
254 };
255
256 enum a4xx_tex_aniso {
257 A4XX_TEX_ANISO_1 = 0,
258 A4XX_TEX_ANISO_2 = 1,
259 A4XX_TEX_ANISO_4 = 2,
260 A4XX_TEX_ANISO_8 = 3,
261 A4XX_TEX_ANISO_16 = 4,
262 };
263
264 enum a4xx_tex_swiz {
265 A4XX_TEX_X = 0,
266 A4XX_TEX_Y = 1,
267 A4XX_TEX_Z = 2,
268 A4XX_TEX_W = 3,
269 A4XX_TEX_ZERO = 4,
270 A4XX_TEX_ONE = 5,
271 };
272
273 enum a4xx_tex_type {
274 A4XX_TEX_1D = 0,
275 A4XX_TEX_2D = 1,
276 A4XX_TEX_CUBE = 2,
277 A4XX_TEX_3D = 3,
278 };
279
280 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
281 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
282 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
283 {
284 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
285 }
286 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
287 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
288 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
289 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
290 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
291 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
292 #define A4XX_INT0_VFD_ERROR 0x00000040
293 #define A4XX_INT0_CP_SW_INT 0x00000080
294 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
295 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
296 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
297 #define A4XX_INT0_CP_HW_FAULT 0x00000800
298 #define A4XX_INT0_CP_DMA 0x00001000
299 #define A4XX_INT0_CP_IB2_INT 0x00002000
300 #define A4XX_INT0_CP_IB1_INT 0x00004000
301 #define A4XX_INT0_CP_RB_INT 0x00008000
302 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
303 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000
304 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000
305 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000
306 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
307 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
308 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000
309 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
310 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
311
312 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
313
314 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
315
316 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
317
318 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
319
320 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
321
322 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
323
324 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
325
326 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
327
328 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
329
330 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
331 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
332 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
333 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
334 {
335 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
336 }
337 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
338 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
339 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
340 {
341 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
342 }
343
344 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
345
346 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
347
348 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
349
350 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
351
352 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0
353 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
354 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
355 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
356 {
357 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
358 }
359 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
360 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
361 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
362 {
363 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
364 }
365
366 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
367 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
368 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
369
370 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
371 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
372 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
373 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
374 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
375 {
376 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
377 }
378
379 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
380 #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
381 #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
382 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
383 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
384 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
385 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
386 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
387 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
388 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
389 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
390 {
391 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
392 }
393 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
394 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
395
396 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
397
398 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
399 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
400 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
401 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
402 #define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400
403 #define A4XX_RB_MRT_CONTROL_B11 0x00000800
404 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
405 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
406 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
407 {
408 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
409 }
410
411 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
412 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
413 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
414 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
415 {
416 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
417 }
418 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
419 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
420 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
421 {
422 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
423 }
424 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
425 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
426 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
427 {
428 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
429 }
430 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
431 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
432 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
433 {
434 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
435 }
436 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
437 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
438 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
439 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
440 {
441 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
442 }
443
444 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
445
446 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
447 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
448 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
449 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
450 {
451 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
452 }
453
454 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
455 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
456 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
457 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
458 {
459 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
460 }
461 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
462 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
463 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
464 {
465 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
466 }
467 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
468 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
469 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
470 {
471 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
472 }
473 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
474 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
475 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
476 {
477 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
478 }
479 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
480 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
481 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
482 {
483 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
484 }
485 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
486 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
487 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
488 {
489 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
490 }
491
492 #define REG_A4XX_RB_BLEND_RED 0x000020f3
493 #define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff
494 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0
495 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
496 {
497 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
498 }
499 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
500 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
501 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
502 {
503 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
504 }
505
506 #define REG_A4XX_RB_BLEND_GREEN 0x000020f4
507 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff
508 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
509 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
510 {
511 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
512 }
513 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
514 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
515 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
516 {
517 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
518 }
519
520 #define REG_A4XX_RB_BLEND_BLUE 0x000020f5
521 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff
522 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
523 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
524 {
525 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
526 }
527 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
528 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
529 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
530 {
531 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
532 }
533
534 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
535 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff
536 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
537 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
538 {
539 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
540 }
541 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
542 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
543 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
544 {
545 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
546 }
547
548 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
549 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
550 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
551 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
552 {
553 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
554 }
555 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
556 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
557 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
558 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
559 {
560 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
561 }
562
563 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9
564 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
565 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
566 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
567 {
568 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
569 }
570 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100
571 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
572 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
573 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
574 {
575 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
576 }
577
578 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
579 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
580 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
581 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
582 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
583 {
584 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
585 }
586
587 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
588 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
589 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
590 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
591 {
592 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
593 }
594 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
595 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
596 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
597 {
598 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
599 }
600 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
601 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
602 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
603 {
604 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
605 }
606 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
607 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
608 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
609 {
610 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
611 }
612 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
613 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
614 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
615 {
616 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
617 }
618 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
619 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
620 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
621 {
622 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
623 }
624 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
625 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
626 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
627 {
628 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
629 }
630 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
631 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
632 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
633 {
634 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
635 }
636
637 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc
638 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
639 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
640 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
641 {
642 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
643 }
644 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
645 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
646 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
647 {
648 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
649 }
650 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
651 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
652 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
653 {
654 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
655 }
656 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
657 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
658 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
659 {
660 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
661 }
662
663 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
664 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
665 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
666 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
667 {
668 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
669 }
670
671 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
672 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
673 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
674 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
675 {
676 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
677 }
678
679 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
680 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
681 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
682 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
683 {
684 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
685 }
686 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
687 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
688 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
689 {
690 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
691 }
692 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
693 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
694 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
695 {
696 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
697 }
698 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
699 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
700 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
701 {
702 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
703 }
704 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
705 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
706 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
707 {
708 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
709 }
710 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
711 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
712 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
713 {
714 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
715 }
716
717 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
718 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
719 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
720 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
721 {
722 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
723 }
724 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
725
726 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
727 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
728 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
729 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
730 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
731 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
732 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
733 {
734 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
735 }
736 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
737 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
738 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
739
740 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
741
742 #define REG_A4XX_RB_DEPTH_INFO 0x00002103
743 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
744 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
745 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
746 {
747 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
748 }
749 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
750 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
751 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
752 {
753 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
754 }
755
756 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104
757 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
758 #define A4XX_RB_DEPTH_PITCH__SHIFT 0
759 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
760 {
761 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
762 }
763
764 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
765 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
766 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0
767 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
768 {
769 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
770 }
771
772 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
773 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
774 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
775 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
776 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
777 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
778 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
779 {
780 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
781 }
782 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
783 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
784 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
785 {
786 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
787 }
788 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
789 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
790 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
791 {
792 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
793 }
794 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
795 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
796 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
797 {
798 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
799 }
800 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
801 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
802 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
803 {
804 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
805 }
806 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
807 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
808 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
809 {
810 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
811 }
812 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
813 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
814 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
815 {
816 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
817 }
818 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
819 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
820 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
821 {
822 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
823 }
824
825 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
826 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
827
828 #define REG_A4XX_RB_STENCIL_INFO 0x00002108
829 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
830 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
831 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
832 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
833 {
834 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
835 }
836
837 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109
838 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
839 #define A4XX_RB_STENCIL_PITCH__SHIFT 0
840 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
841 {
842 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
843 }
844
845 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b
846 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
847 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
848 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
849 {
850 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
851 }
852 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
853 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
854 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
855 {
856 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
857 }
858 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
859 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
860 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
861 {
862 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
863 }
864
865 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
866 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
867 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
868 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
869 {
870 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
871 }
872 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
873 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
874 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
875 {
876 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
877 }
878 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
879 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
880 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
881 {
882 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
883 }
884
885 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d
886 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
887 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
888 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0
889 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
890 {
891 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
892 }
893 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
894 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
895 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
896 {
897 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
898 }
899
900 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
901
902 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
903
904 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
905
906 #define REG_A4XX_RBBM_HW_VERSION 0x00000000
907
908 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
909
910 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
911
912 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
913
914 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
915
916 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
917
918 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
919
920 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
921
922 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
923
924 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
925
926 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
927
928 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
929
930 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
931
932 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
933
934 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
935
936 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
937
938 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
939
940 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
941
942 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
943
944 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
945
946 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
947
948 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
949
950 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
951
952 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
953
954 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
955
956 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023
957
958 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024
959
960 #define REG_A4XX_RBBM_AHB_CMD 0x00000025
961
962 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
963
964 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
965
966 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
967
968 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
969
970 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
971
972 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
973
974 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037
975
976 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
977
978 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
979
980 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
981
982 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
983
984 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
985
986 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
987
988 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
989
990 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
991
992 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
993
994 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
995
996 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
997
998 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
999
1000 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1001
1002 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1003
1004 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1005
1006 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1007
1008 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1009
1010 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1011
1012 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1013
1014 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1015
1016 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1017
1018 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1019
1020 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1021
1022 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1023
1024 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1025
1026 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1027
1028 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1029
1030 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1031
1032 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
1033
1034 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
1035
1036 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
1037
1038 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
1039
1040 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
1041
1042 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
1043
1044 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1045
1046 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1047
1048 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
1049
1050 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
1051
1052 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
1053
1054 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
1055
1056 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
1057
1058 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
1059
1060 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
1061
1062 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
1063
1064 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
1065
1066 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
1067
1068 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189
1069
1070 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
1071
1072 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
1073
1074 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
1075
1076 #define REG_A4XX_RBBM_STATUS 0x00000191
1077 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
1078 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1079 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1080 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
1081 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
1082 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
1083 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
1084 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
1085 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1086 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1087 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
1088 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
1089 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
1090 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
1091 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
1092 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
1093 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
1094 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
1095 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1096 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
1097 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
1098
1099 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
1100
1101 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
1102
1103 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
1104
1105 #define REG_A4XX_CP_RB_BASE 0x00000200
1106
1107 #define REG_A4XX_CP_RB_CNTL 0x00000201
1108
1109 #define REG_A4XX_CP_RB_WPTR 0x00000205
1110
1111 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
1112
1113 #define REG_A4XX_CP_RB_RPTR 0x00000204
1114
1115 #define REG_A4XX_CP_IB1_BASE 0x00000206
1116
1117 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207
1118
1119 #define REG_A4XX_CP_IB2_BASE 0x00000208
1120
1121 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209
1122
1123 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
1124
1125 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
1126
1127 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
1128
1129 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
1130
1131 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
1132
1133 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c
1134
1135 #define REG_A4XX_CP_ROQ_DATA 0x0000021d
1136
1137 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e
1138
1139 #define REG_A4XX_CP_MEQ_DATA 0x0000021f
1140
1141 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220
1142
1143 #define REG_A4XX_CP_MERCIU_DATA 0x00000221
1144
1145 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222
1146
1147 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
1148
1149 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
1150
1151 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
1152
1153 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
1154
1155 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227
1156
1157 #define REG_A4XX_CP_PREEMPT 0x0000022a
1158
1159 #define REG_A4XX_CP_CNTL 0x0000022c
1160
1161 #define REG_A4XX_CP_ME_CNTL 0x0000022d
1162
1163 #define REG_A4XX_CP_DEBUG 0x0000022e
1164
1165 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
1166
1167 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
1168
1169 #define REG_A4XX_CP_PROTECT_REG_0 0x00000240
1170
1171 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1172
1173 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1174
1175 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250
1176
1177 #define REG_A4XX_CP_ST_BASE 0x000004c0
1178
1179 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce
1180
1181 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0
1182
1183 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
1184
1185 #define REG_A4XX_CP_HW_FAULT 0x000004d8
1186
1187 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da
1188
1189 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
1190
1191 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
1192
1193 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
1194
1195 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1196
1197 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1198
1199 #define REG_A4XX_SP_VS_STATUS 0x00000ec0
1200
1201 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
1202
1203 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
1204
1205 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
1206 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
1207
1208 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
1209 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
1210 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
1211 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
1212
1213 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
1214 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1215 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1216 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1217 {
1218 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
1219 }
1220 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
1221 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1222 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1223 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1224 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1225 {
1226 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1227 }
1228 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1229 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1230 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1231 {
1232 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1233 }
1234 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1235 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1236 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1237 {
1238 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1239 }
1240 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1241 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
1242 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1243 {
1244 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
1245 }
1246 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1247 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1248
1249 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
1250 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1251 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1252 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1253 {
1254 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
1255 }
1256 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
1257 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
1258 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
1259 {
1260 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
1261 }
1262
1263 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
1264 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
1265 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
1266 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
1267 {
1268 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
1269 }
1270 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
1271 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
1272 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
1273 {
1274 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
1275 }
1276 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
1277 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
1278 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
1279 {
1280 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
1281 }
1282
1283 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1284
1285 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1286 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
1287 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
1288 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
1289 {
1290 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
1291 }
1292 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1293 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
1294 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
1295 {
1296 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
1297 }
1298 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
1299 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
1300 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
1301 {
1302 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
1303 }
1304 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1305 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
1306 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
1307 {
1308 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
1309 }
1310
1311 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1312
1313 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1314 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1315 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
1316 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
1317 {
1318 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
1319 }
1320 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1321 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
1322 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
1323 {
1324 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
1325 }
1326 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1327 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
1328 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
1329 {
1330 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
1331 }
1332 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1333 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
1334 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
1335 {
1336 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
1337 }
1338
1339 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
1340 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1341 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1342 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1343 {
1344 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1345 }
1346 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1347 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1348 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1349 {
1350 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1351 }
1352
1353 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1
1354
1355 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
1356
1357 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
1358
1359 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
1360
1361 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
1362 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
1363 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
1364 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1365 {
1366 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
1367 }
1368 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
1369 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
1370 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1371 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1372 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1373 {
1374 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1375 }
1376 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1377 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1378 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1379 {
1380 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1381 }
1382 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1383 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1384 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1385 {
1386 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1387 }
1388 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1389 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
1390 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1391 {
1392 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
1393 }
1394 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1395 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1396
1397 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
1398 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1399 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1400 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1401 {
1402 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
1403 }
1404 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
1405 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
1406 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
1407
1408 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
1409 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1410 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1411 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1412 {
1413 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1414 }
1415 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1416 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1417 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1418 {
1419 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1420 }
1421
1422 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb
1423
1424 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
1425
1426 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
1427
1428 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
1429
1430 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
1431 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1432 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
1433 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
1434 {
1435 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
1436 }
1437 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
1438 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
1439 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
1440 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
1441 {
1442 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
1443 }
1444 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
1445 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
1446 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
1447 {
1448 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
1449 }
1450
1451 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1452
1453 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1454 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
1455 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
1456 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
1457 {
1458 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
1459 }
1460 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
1461 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
1462 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
1463 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
1464 {
1465 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
1466 }
1467 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
1468
1469 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
1470
1471 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
1472
1473 #define REG_A4XX_SP_CS_OBJ_START 0x00002302
1474
1475 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
1476
1477 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
1478
1479 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
1480
1481 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
1482
1483 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
1484 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1485 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1486 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1487 {
1488 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1489 }
1490 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1491 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1492 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1493 {
1494 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1495 }
1496
1497 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e
1498
1499 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
1500
1501 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
1502
1503 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
1504
1505 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
1506 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
1507 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
1508 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
1509 {
1510 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
1511 }
1512 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1513 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1514 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1515 {
1516 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
1517 }
1518
1519 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1520
1521 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1522 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
1523 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
1524 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
1525 {
1526 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
1527 }
1528 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1529 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
1530 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
1531 {
1532 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
1533 }
1534 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
1535 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
1536 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
1537 {
1538 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
1539 }
1540 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1541 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
1542 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
1543 {
1544 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
1545 }
1546
1547 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1548
1549 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1550 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1551 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
1552 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
1553 {
1554 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
1555 }
1556 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1557 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
1558 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
1559 {
1560 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
1561 }
1562 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1563 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
1564 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
1565 {
1566 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
1567 }
1568 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1569 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
1570 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
1571 {
1572 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
1573 }
1574
1575 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
1576 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1577 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1578 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1579 {
1580 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1581 }
1582 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1583 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1584 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1585 {
1586 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1587 }
1588
1589 #define REG_A4XX_SP_DS_OBJ_START 0x00002335
1590
1591 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
1592
1593 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
1594
1595 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
1596
1597 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341
1598 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
1599 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
1600 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
1601 {
1602 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
1603 }
1604 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
1605 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
1606 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
1607 {
1608 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
1609 }
1610 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1611 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1612 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1613 {
1614 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
1615 }
1616
1617 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1618
1619 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1620 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
1621 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
1622 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
1623 {
1624 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
1625 }
1626 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1627 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
1628 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
1629 {
1630 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
1631 }
1632 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
1633 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
1634 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
1635 {
1636 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
1637 }
1638 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1639 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
1640 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
1641 {
1642 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
1643 }
1644
1645 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1646
1647 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1648 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1649 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
1650 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
1651 {
1652 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
1653 }
1654 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1655 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
1656 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
1657 {
1658 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
1659 }
1660 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1661 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
1662 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
1663 {
1664 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
1665 }
1666 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1667 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
1668 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
1669 {
1670 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
1671 }
1672
1673 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
1674 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1675 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1676 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1677 {
1678 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1679 }
1680 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1681 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1682 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1683 {
1684 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1685 }
1686
1687 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c
1688
1689 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
1690
1691 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
1692
1693 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
1694
1695 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
1696
1697 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
1698
1699 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
1700
1701 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
1702
1703 #define REG_A4XX_VPC_ATTR 0x00002140
1704 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1705 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
1706 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
1707 {
1708 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
1709 }
1710 #define A4XX_VPC_ATTR_PSIZE 0x00000200
1711 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
1712 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1713 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
1714 {
1715 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
1716 }
1717 #define A4XX_VPC_ATTR_ENABLE 0x02000000
1718
1719 #define REG_A4XX_VPC_PACK 0x00002141
1720 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
1721 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
1722 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
1723 {
1724 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
1725 }
1726 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1727 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1728 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
1729 {
1730 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
1731 }
1732 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1733 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1734 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
1735 {
1736 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
1737 }
1738
1739 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1740
1741 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1742
1743 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1744
1745 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1746
1747 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
1748
1749 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00
1750 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1751 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1752 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1753 {
1754 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
1755 }
1756 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1757 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1758 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1759 {
1760 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
1761 }
1762
1763 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
1764
1765 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
1766
1767 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
1768
1769 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1770
1771 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1772 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1773 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1774 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1775 {
1776 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
1777 }
1778 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1779 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1780 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1781 {
1782 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1783 }
1784 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1785 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1786 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1787 {
1788 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
1789 }
1790 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1791 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
1792 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1793 {
1794 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
1795 }
1796
1797 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1798
1799 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1800
1801 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1802
1803 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1804
1805 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
1806
1807 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
1808
1809 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
1810
1811 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
1812
1813 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
1814
1815 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
1816
1817 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
1818
1819 #define REG_A4XX_VFD_CONTROL_0 0x00002200
1820 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
1821 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1822 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1823 {
1824 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1825 }
1826 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
1827 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
1828 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
1829 {
1830 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
1831 }
1832 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
1833 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
1834 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1835 {
1836 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1837 }
1838 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
1839 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
1840 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1841 {
1842 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1843 }
1844
1845 #define REG_A4XX_VFD_CONTROL_1 0x00002201
1846 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1847 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1848 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1849 {
1850 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1851 }
1852 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1853 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1854 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1855 {
1856 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
1857 }
1858 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1859 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1860 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1861 {
1862 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
1863 }
1864
1865 #define REG_A4XX_VFD_CONTROL_2 0x00002202
1866
1867 #define REG_A4XX_VFD_CONTROL_3 0x00002203
1868 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
1869 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
1870 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
1871 {
1872 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
1873 }
1874 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
1875 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
1876 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
1877 {
1878 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
1879 }
1880 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
1881 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
1882 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
1883 {
1884 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
1885 }
1886
1887 #define REG_A4XX_VFD_CONTROL_4 0x00002204
1888
1889 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
1890
1891 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1892
1893 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1894 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1895 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1896 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1897 {
1898 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1899 }
1900 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
1901 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1902 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1903 {
1904 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1905 }
1906 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
1907 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
1908
1909 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
1910
1911 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
1912 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
1913 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
1914 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
1915 {
1916 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
1917 }
1918
1919 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
1920 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
1921 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
1922 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
1923 {
1924 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
1925 }
1926
1927 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1928
1929 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1930 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1931 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1932 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1933 {
1934 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
1935 }
1936 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
1937 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
1938 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
1939 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
1940 {
1941 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
1942 }
1943 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
1944 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
1945 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
1946 {
1947 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
1948 }
1949 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000
1950 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
1951 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
1952 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
1953 {
1954 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
1955 }
1956 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
1957 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
1958 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
1959 {
1960 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
1961 }
1962 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
1963 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
1964
1965 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
1966
1967 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
1968
1969 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
1970
1971 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
1972
1973 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
1974 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
1975 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
1976 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
1977 {
1978 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
1979 }
1980 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
1981 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
1982 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
1983 {
1984 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
1985 }
1986 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
1987 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
1988 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
1989 {
1990 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
1991 }
1992 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
1993 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
1994 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
1995 {
1996 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
1997 }
1998
1999 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
2000
2001 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
2002
2003 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
2004
2005 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
2006
2007 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
2008
2009 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
2010
2011 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
2012
2013 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
2014
2015 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
2016
2017 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
2018
2019 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
2020
2021 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
2022
2023 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
2024
2025 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
2026
2027 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
2028 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
2029
2030 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
2031 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
2032 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
2033 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
2034 {
2035 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
2036 }
2037 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
2038 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
2039 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
2040 {
2041 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
2042 }
2043
2044 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
2045 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2046 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2047 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2048 {
2049 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2050 }
2051
2052 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
2053 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2054 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2055 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
2056 {
2057 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2058 }
2059
2060 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
2061 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2062 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2063 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2064 {
2065 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2066 }
2067
2068 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
2069 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2070 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2071 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
2072 {
2073 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2074 }
2075
2076 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
2077 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2078 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2079 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2080 {
2081 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2082 }
2083
2084 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
2085 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2086 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2087 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2088 {
2089 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2090 }
2091
2092 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
2093 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2094 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2095 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2096 {
2097 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2098 }
2099 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2100 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2101 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2102 {
2103 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2104 }
2105
2106 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
2107 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2108 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
2109 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
2110 {
2111 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
2112 }
2113
2114 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
2115 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
2116
2117 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
2118 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2119 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2120 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2121 {
2122 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2123 }
2124
2125 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
2126 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2127 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2128 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2129 {
2130 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2131 }
2132
2133 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
2134 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
2135 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
2136 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
2137 {
2138 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
2139 }
2140
2141 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
2142 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
2143 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
2144 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
2145 {
2146 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
2147 }
2148
2149 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
2150 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
2151 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
2152 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
2153 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
2154 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
2155 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
2156 {
2157 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
2158 }
2159 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
2160 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
2161
2162 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
2163 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
2164 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
2165 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
2166 {
2167 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
2168 }
2169 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
2170 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
2171 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
2172 {
2173 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
2174 }
2175 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
2176 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
2177 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
2178 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
2179 {
2180 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
2181 }
2182
2183 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
2184 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2185 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
2186 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
2187 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
2188 {
2189 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
2190 }
2191 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
2192 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
2193 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
2194 {
2195 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
2196 }
2197
2198 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
2199 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2200 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
2201 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
2202 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
2203 {
2204 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
2205 }
2206 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
2207 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
2208 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
2209 {
2210 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
2211 }
2212
2213 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
2214 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2215 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2216 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2217 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2218 {
2219 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2220 }
2221 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2222 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2223 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2224 {
2225 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2226 }
2227
2228 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
2229 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2230 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2231 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2232 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2233 {
2234 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2235 }
2236 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2237 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2238 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2239 {
2240 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2241 }
2242
2243 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
2244 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
2245 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
2246 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
2247 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
2248 {
2249 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
2250 }
2251 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
2252 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
2253 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
2254 {
2255 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
2256 }
2257
2258 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
2259 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
2260 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
2261 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
2262 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
2263 {
2264 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
2265 }
2266 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
2267 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
2268 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
2269 {
2270 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
2271 }
2272
2273 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
2274
2275 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
2276
2277 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
2278
2279 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
2280
2281 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
2282
2283 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
2284
2285 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
2286
2287 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
2288
2289 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
2290
2291 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
2292
2293 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
2294
2295 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
2296
2297 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
2298 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
2299 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
2300 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
2301 {
2302 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
2303 }
2304 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
2305 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
2306 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
2307 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
2308 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
2309 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
2310 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
2311 {
2312 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
2313 }
2314 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
2315 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
2316 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
2317 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
2318
2319 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
2320 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
2321 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
2322 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
2323 {
2324 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
2325 }
2326 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
2327 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
2328 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
2329 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
2330 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
2331 {
2332 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
2333 }
2334 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
2335 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
2336 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
2337 {
2338 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
2339 }
2340
2341 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
2342 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
2343 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
2344 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
2345 {
2346 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
2347 }
2348 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
2349 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
2350 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
2351 {
2352 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
2353 }
2354 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
2355 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
2356 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
2357 {
2358 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
2359 }
2360 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
2361 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
2362 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
2363 {
2364 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
2365 }
2366
2367 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
2368 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
2369 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
2370 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
2371 {
2372 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
2373 }
2374
2375 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
2376
2377 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
2378 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2379 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2380 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2381 {
2382 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
2383 }
2384 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2385 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2386 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2387 {
2388 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2389 }
2390 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
2391 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2392 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2393 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2394 {
2395 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2396 }
2397 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2398 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2399 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2400 {
2401 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
2402 }
2403
2404 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
2405 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2406 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2407 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2408 {
2409 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
2410 }
2411 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2412 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2413 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2414 {
2415 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2416 }
2417 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
2418 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2419 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2420 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2421 {
2422 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2423 }
2424 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2425 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2426 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2427 {
2428 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
2429 }
2430
2431 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
2432 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2433 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2434 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2435 {
2436 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
2437 }
2438 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2439 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2440 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2441 {
2442 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2443 }
2444 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
2445 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2446 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2447 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2448 {
2449 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2450 }
2451 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2452 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2453 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2454 {
2455 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
2456 }
2457
2458 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
2459 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2460 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2461 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2462 {
2463 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
2464 }
2465 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2466 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2467 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2468 {
2469 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2470 }
2471 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
2472 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2473 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2474 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2475 {
2476 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2477 }
2478 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2479 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2480 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2481 {
2482 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
2483 }
2484
2485 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
2486 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2487 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2488 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2489 {
2490 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
2491 }
2492 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2493 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2494 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2495 {
2496 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2497 }
2498 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
2499 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2500 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2501 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2502 {
2503 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2504 }
2505 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2506 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2507 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2508 {
2509 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
2510 }
2511
2512 #define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca
2513
2514 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
2515
2516 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
2517
2518 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
2519
2520 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
2521
2522 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
2523
2524 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
2525
2526 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
2527
2528 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
2529
2530 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
2531
2532 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
2533
2534 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
2535
2536 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
2537
2538 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
2539
2540 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
2541
2542 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
2543
2544 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
2545 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
2546
2547 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
2548
2549 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2550
2551 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2552
2553 #define REG_A4XX_PC_BIN_BASE 0x000021c0
2554
2555 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
2556 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
2557 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
2558 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
2559 {
2560 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
2561 }
2562 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
2563 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
2564 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
2565
2566 #define REG_A4XX_UNKNOWN_21C5 0x000021c5
2567
2568 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6
2569
2570 #define REG_A4XX_PC_GS_PARAM 0x000021e5
2571 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
2572 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
2573 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
2574 {
2575 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
2576 }
2577 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
2578 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
2579 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
2580 {
2581 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
2582 }
2583 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
2584 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
2585 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2586 {
2587 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
2588 }
2589 #define A4XX_PC_GS_PARAM_LAYER 0x80000000
2590
2591 #define REG_A4XX_PC_HS_PARAM 0x000021e7
2592 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
2593 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
2594 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
2595 {
2596 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
2597 }
2598 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
2599 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
2600 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
2601 {
2602 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
2603 }
2604 #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000
2605 #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23
2606 static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2607 {
2608 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
2609 }
2610
2611 #define REG_A4XX_VBIF_VERSION 0x00003000
2612
2613 #define REG_A4XX_VBIF_CLKON 0x00003001
2614 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
2615
2616 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
2617
2618 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
2619
2620 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2621
2622 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2623
2624 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2625
2626 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
2627
2628 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
2629
2630 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2631
2632 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
2633
2634 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
2635
2636 #define REG_A4XX_UNKNOWN_0D01 0x00000d01
2637
2638 #define REG_A4XX_UNKNOWN_0E42 0x00000e42
2639
2640 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
2641
2642 #define REG_A4XX_UNKNOWN_2001 0x00002001
2643
2644 #define REG_A4XX_UNKNOWN_209B 0x0000209b
2645
2646 #define REG_A4XX_UNKNOWN_20EF 0x000020ef
2647
2648 #define REG_A4XX_UNKNOWN_20F0 0x000020f0
2649
2650 #define REG_A4XX_UNKNOWN_20F1 0x000020f1
2651
2652 #define REG_A4XX_UNKNOWN_20F2 0x000020f2
2653
2654 #define REG_A4XX_UNKNOWN_20F7 0x000020f7
2655 #define A4XX_UNKNOWN_20F7__MASK 0xffffffff
2656 #define A4XX_UNKNOWN_20F7__SHIFT 0
2657 static inline uint32_t A4XX_UNKNOWN_20F7(float val)
2658 {
2659 return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK;
2660 }
2661
2662 #define REG_A4XX_UNKNOWN_2152 0x00002152
2663
2664 #define REG_A4XX_UNKNOWN_2153 0x00002153
2665
2666 #define REG_A4XX_UNKNOWN_2154 0x00002154
2667
2668 #define REG_A4XX_UNKNOWN_2155 0x00002155
2669
2670 #define REG_A4XX_UNKNOWN_2156 0x00002156
2671
2672 #define REG_A4XX_UNKNOWN_2157 0x00002157
2673
2674 #define REG_A4XX_UNKNOWN_21C3 0x000021c3
2675
2676 #define REG_A4XX_UNKNOWN_21E6 0x000021e6
2677
2678 #define REG_A4XX_UNKNOWN_2209 0x00002209
2679
2680 #define REG_A4XX_UNKNOWN_22D7 0x000022d7
2681
2682 #define REG_A4XX_UNKNOWN_2352 0x00002352
2683
2684 #define REG_A4XX_TEX_SAMP_0 0x00000000
2685 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
2686 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
2687 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
2688 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
2689 {
2690 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
2691 }
2692 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
2693 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
2694 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
2695 {
2696 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
2697 }
2698 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
2699 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
2700 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
2701 {
2702 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
2703 }
2704 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
2705 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
2706 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
2707 {
2708 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
2709 }
2710 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
2711 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
2712 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
2713 {
2714 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
2715 }
2716 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
2717 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
2718 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
2719 {
2720 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
2721 }
2722
2723 #define REG_A4XX_TEX_SAMP_1 0x00000001
2724 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
2725 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
2726 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
2727 {
2728 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
2729 }
2730 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
2731 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
2732 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
2733 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
2734 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
2735 {
2736 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
2737 }
2738 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
2739 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
2740 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
2741 {
2742 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
2743 }
2744
2745 #define REG_A4XX_TEX_CONST_0 0x00000000
2746 #define A4XX_TEX_CONST_0_TILED 0x00000001
2747 #define A4XX_TEX_CONST_0_SRGB 0x00000004
2748 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2749 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2750 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
2751 {
2752 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
2753 }
2754 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2755 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2756 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
2757 {
2758 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
2759 }
2760 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2761 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2762 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
2763 {
2764 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
2765 }
2766 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2767 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2768 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
2769 {
2770 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
2771 }
2772 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2773 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2774 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
2775 {
2776 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
2777 }
2778 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2779 #define A4XX_TEX_CONST_0_FMT__SHIFT 22
2780 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
2781 {
2782 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
2783 }
2784 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
2785 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29
2786 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
2787 {
2788 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
2789 }
2790
2791 #define REG_A4XX_TEX_CONST_1 0x00000001
2792 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
2793 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
2794 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
2795 {
2796 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
2797 }
2798 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000
2799 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
2800 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
2801 {
2802 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
2803 }
2804
2805 #define REG_A4XX_TEX_CONST_2 0x00000002
2806 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
2807 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
2808 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
2809 {
2810 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
2811 }
2812 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
2813 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9
2814 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
2815 {
2816 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
2817 }
2818 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2819 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30
2820 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
2821 {
2822 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
2823 }
2824
2825 #define REG_A4XX_TEX_CONST_3 0x00000003
2826 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
2827 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
2828 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
2829 {
2830 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
2831 }
2832 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
2833 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
2834 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
2835 {
2836 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
2837 }
2838
2839 #define REG_A4XX_TEX_CONST_4 0x00000004
2840 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
2841 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
2842 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
2843 {
2844 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
2845 }
2846 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
2847 #define A4XX_TEX_CONST_4_BASE__SHIFT 5
2848 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
2849 {
2850 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
2851 }
2852
2853 #define REG_A4XX_TEX_CONST_5 0x00000005
2854
2855 #define REG_A4XX_TEX_CONST_6 0x00000006
2856
2857 #define REG_A4XX_TEX_CONST_7 0x00000007
2858
2859
2860 #endif /* A4XX_XML */