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freedreno/a4xx: add formats for ARB_texture_buffer_object_rgb32 support
[mesa.git] / src / gallium / drivers / freedreno / a4xx / a4xx.xml.h
1 #ifndef A4XX_XML
2 #define A4XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 68291 bytes, from 2015-11-17 16:39:59)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 64038 bytes, from 2015-11-17 16:37:36)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19
20 Copyright (C) 2013-2015 by the following authors:
21 - Rob Clark <robdclark@gmail.com> (robclark)
22
23 Permission is hereby granted, free of charge, to any person obtaining
24 a copy of this software and associated documentation files (the
25 "Software"), to deal in the Software without restriction, including
26 without limitation the rights to use, copy, modify, merge, publish,
27 distribute, sublicense, and/or sell copies of the Software, and to
28 permit persons to whom the Software is furnished to do so, subject to
29 the following conditions:
30
31 The above copyright notice and this permission notice (including the
32 next paragraph) shall be included in all copies or substantial
33 portions of the Software.
34
35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44
45 enum a4xx_color_fmt {
46 RB4_A8_UNORM = 1,
47 RB4_R8_UNORM = 2,
48 RB4_R4G4B4A4_UNORM = 8,
49 RB4_R5G5B5A1_UNORM = 10,
50 RB4_R5G6B5_UNORM = 14,
51 RB4_R8G8_UNORM = 15,
52 RB4_R8G8_SNORM = 16,
53 RB4_R8G8_UINT = 17,
54 RB4_R8G8_SINT = 18,
55 RB4_R16_UNORM = 19,
56 RB4_R16_SNORM = 20,
57 RB4_R16_FLOAT = 21,
58 RB4_R16_UINT = 22,
59 RB4_R16_SINT = 23,
60 RB4_R8G8B8_UNORM = 25,
61 RB4_R8G8B8A8_UNORM = 26,
62 RB4_R8G8B8A8_SNORM = 28,
63 RB4_R8G8B8A8_UINT = 29,
64 RB4_R8G8B8A8_SINT = 30,
65 RB4_R10G10B10A2_UNORM = 31,
66 RB4_R10G10B10A2_UINT = 34,
67 RB4_R11G11B10_FLOAT = 39,
68 RB4_R16G16_UNORM = 40,
69 RB4_R16G16_SNORM = 41,
70 RB4_R16G16_FLOAT = 42,
71 RB4_R16G16_UINT = 43,
72 RB4_R16G16_SINT = 44,
73 RB4_R32_FLOAT = 45,
74 RB4_R32_UINT = 46,
75 RB4_R32_SINT = 47,
76 RB4_R16G16B16A16_UNORM = 52,
77 RB4_R16G16B16A16_SNORM = 53,
78 RB4_R16G16B16A16_FLOAT = 54,
79 RB4_R16G16B16A16_UINT = 55,
80 RB4_R16G16B16A16_SINT = 56,
81 RB4_R32G32_FLOAT = 57,
82 RB4_R32G32_UINT = 58,
83 RB4_R32G32_SINT = 59,
84 RB4_R32G32B32A32_FLOAT = 60,
85 RB4_R32G32B32A32_UINT = 61,
86 RB4_R32G32B32A32_SINT = 62,
87 };
88
89 enum a4xx_tile_mode {
90 TILE4_LINEAR = 0,
91 TILE4_3 = 3,
92 };
93
94 enum a4xx_rb_blend_opcode {
95 BLEND_DST_PLUS_SRC = 0,
96 BLEND_SRC_MINUS_DST = 1,
97 BLEND_DST_MINUS_SRC = 2,
98 BLEND_MIN_DST_SRC = 3,
99 BLEND_MAX_DST_SRC = 4,
100 };
101
102 enum a4xx_vtx_fmt {
103 VFMT4_32_FLOAT = 1,
104 VFMT4_32_32_FLOAT = 2,
105 VFMT4_32_32_32_FLOAT = 3,
106 VFMT4_32_32_32_32_FLOAT = 4,
107 VFMT4_16_FLOAT = 5,
108 VFMT4_16_16_FLOAT = 6,
109 VFMT4_16_16_16_FLOAT = 7,
110 VFMT4_16_16_16_16_FLOAT = 8,
111 VFMT4_32_FIXED = 9,
112 VFMT4_32_32_FIXED = 10,
113 VFMT4_32_32_32_FIXED = 11,
114 VFMT4_32_32_32_32_FIXED = 12,
115 VFMT4_11_11_10_FLOAT = 13,
116 VFMT4_16_SINT = 16,
117 VFMT4_16_16_SINT = 17,
118 VFMT4_16_16_16_SINT = 18,
119 VFMT4_16_16_16_16_SINT = 19,
120 VFMT4_16_UINT = 20,
121 VFMT4_16_16_UINT = 21,
122 VFMT4_16_16_16_UINT = 22,
123 VFMT4_16_16_16_16_UINT = 23,
124 VFMT4_16_SNORM = 24,
125 VFMT4_16_16_SNORM = 25,
126 VFMT4_16_16_16_SNORM = 26,
127 VFMT4_16_16_16_16_SNORM = 27,
128 VFMT4_16_UNORM = 28,
129 VFMT4_16_16_UNORM = 29,
130 VFMT4_16_16_16_UNORM = 30,
131 VFMT4_16_16_16_16_UNORM = 31,
132 VFMT4_32_UINT = 32,
133 VFMT4_32_32_UINT = 33,
134 VFMT4_32_32_32_UINT = 34,
135 VFMT4_32_32_32_32_UINT = 35,
136 VFMT4_32_SINT = 36,
137 VFMT4_32_32_SINT = 37,
138 VFMT4_32_32_32_SINT = 38,
139 VFMT4_32_32_32_32_SINT = 39,
140 VFMT4_8_UINT = 40,
141 VFMT4_8_8_UINT = 41,
142 VFMT4_8_8_8_UINT = 42,
143 VFMT4_8_8_8_8_UINT = 43,
144 VFMT4_8_UNORM = 44,
145 VFMT4_8_8_UNORM = 45,
146 VFMT4_8_8_8_UNORM = 46,
147 VFMT4_8_8_8_8_UNORM = 47,
148 VFMT4_8_SINT = 48,
149 VFMT4_8_8_SINT = 49,
150 VFMT4_8_8_8_SINT = 50,
151 VFMT4_8_8_8_8_SINT = 51,
152 VFMT4_8_SNORM = 52,
153 VFMT4_8_8_SNORM = 53,
154 VFMT4_8_8_8_SNORM = 54,
155 VFMT4_8_8_8_8_SNORM = 55,
156 VFMT4_10_10_10_2_UINT = 56,
157 VFMT4_10_10_10_2_UNORM = 57,
158 VFMT4_10_10_10_2_SINT = 58,
159 VFMT4_10_10_10_2_SNORM = 59,
160 };
161
162 enum a4xx_tex_fmt {
163 TFMT4_5_6_5_UNORM = 11,
164 TFMT4_5_5_5_1_UNORM = 9,
165 TFMT4_4_4_4_4_UNORM = 8,
166 TFMT4_X8Z24_UNORM = 71,
167 TFMT4_10_10_10_2_UNORM = 33,
168 TFMT4_10_10_10_2_UINT = 34,
169 TFMT4_A8_UNORM = 3,
170 TFMT4_L8_A8_UNORM = 13,
171 TFMT4_8_UNORM = 4,
172 TFMT4_8_8_UNORM = 14,
173 TFMT4_8_8_8_8_UNORM = 28,
174 TFMT4_8_SNORM = 5,
175 TFMT4_8_8_SNORM = 15,
176 TFMT4_8_8_8_8_SNORM = 29,
177 TFMT4_8_UINT = 6,
178 TFMT4_8_8_UINT = 16,
179 TFMT4_8_8_8_8_UINT = 30,
180 TFMT4_8_SINT = 7,
181 TFMT4_8_8_SINT = 17,
182 TFMT4_8_8_8_8_SINT = 31,
183 TFMT4_16_UNORM = 18,
184 TFMT4_16_16_UNORM = 38,
185 TFMT4_16_16_16_16_UNORM = 51,
186 TFMT4_16_SNORM = 19,
187 TFMT4_16_16_SNORM = 39,
188 TFMT4_16_16_16_16_SNORM = 52,
189 TFMT4_16_UINT = 21,
190 TFMT4_16_16_UINT = 41,
191 TFMT4_16_16_16_16_UINT = 54,
192 TFMT4_16_SINT = 22,
193 TFMT4_16_16_SINT = 42,
194 TFMT4_16_16_16_16_SINT = 55,
195 TFMT4_32_UINT = 44,
196 TFMT4_32_32_UINT = 57,
197 TFMT4_32_32_32_32_UINT = 64,
198 TFMT4_32_SINT = 45,
199 TFMT4_32_32_SINT = 58,
200 TFMT4_32_32_32_32_SINT = 65,
201 TFMT4_16_FLOAT = 20,
202 TFMT4_16_16_FLOAT = 40,
203 TFMT4_16_16_16_16_FLOAT = 53,
204 TFMT4_32_FLOAT = 43,
205 TFMT4_32_32_FLOAT = 56,
206 TFMT4_32_32_32_32_FLOAT = 63,
207 TFMT4_32_32_32_FLOAT = 59,
208 TFMT4_32_32_32_UINT = 60,
209 TFMT4_32_32_32_SINT = 61,
210 TFMT4_9_9_9_E5_FLOAT = 32,
211 TFMT4_11_11_10_FLOAT = 37,
212 TFMT4_DXT1 = 86,
213 TFMT4_DXT3 = 87,
214 TFMT4_DXT5 = 88,
215 TFMT4_RGTC1_UNORM = 90,
216 TFMT4_RGTC1_SNORM = 91,
217 TFMT4_RGTC2_UNORM = 94,
218 TFMT4_RGTC2_SNORM = 95,
219 TFMT4_BPTC_UFLOAT = 97,
220 TFMT4_BPTC_FLOAT = 98,
221 TFMT4_BPTC = 99,
222 TFMT4_ATC_RGB = 100,
223 TFMT4_ATC_RGBA_EXPLICIT = 101,
224 TFMT4_ATC_RGBA_INTERPOLATED = 102,
225 TFMT4_ETC2_RG11_UNORM = 103,
226 TFMT4_ETC2_RG11_SNORM = 104,
227 TFMT4_ETC2_R11_UNORM = 105,
228 TFMT4_ETC2_R11_SNORM = 106,
229 TFMT4_ETC1 = 107,
230 TFMT4_ETC2_RGB8 = 108,
231 TFMT4_ETC2_RGBA8 = 109,
232 TFMT4_ETC2_RGB8A1 = 110,
233 TFMT4_ASTC_4x4 = 111,
234 TFMT4_ASTC_5x4 = 112,
235 TFMT4_ASTC_5x5 = 113,
236 TFMT4_ASTC_6x5 = 114,
237 TFMT4_ASTC_6x6 = 115,
238 TFMT4_ASTC_8x5 = 116,
239 TFMT4_ASTC_8x6 = 117,
240 TFMT4_ASTC_8x8 = 118,
241 TFMT4_ASTC_10x5 = 119,
242 TFMT4_ASTC_10x6 = 120,
243 TFMT4_ASTC_10x8 = 121,
244 TFMT4_ASTC_10x10 = 122,
245 TFMT4_ASTC_12x10 = 123,
246 TFMT4_ASTC_12x12 = 124,
247 };
248
249 enum a4xx_tex_fetchsize {
250 TFETCH4_1_BYTE = 0,
251 TFETCH4_2_BYTE = 1,
252 TFETCH4_4_BYTE = 2,
253 TFETCH4_8_BYTE = 3,
254 TFETCH4_16_BYTE = 4,
255 };
256
257 enum a4xx_depth_format {
258 DEPTH4_NONE = 0,
259 DEPTH4_16 = 1,
260 DEPTH4_24_8 = 2,
261 DEPTH4_32 = 3,
262 };
263
264 enum a4xx_tess_spacing {
265 EQUAL_SPACING = 0,
266 ODD_SPACING = 2,
267 EVEN_SPACING = 3,
268 };
269
270 enum a4xx_tex_filter {
271 A4XX_TEX_NEAREST = 0,
272 A4XX_TEX_LINEAR = 1,
273 A4XX_TEX_ANISO = 2,
274 };
275
276 enum a4xx_tex_clamp {
277 A4XX_TEX_REPEAT = 0,
278 A4XX_TEX_CLAMP_TO_EDGE = 1,
279 A4XX_TEX_MIRROR_REPEAT = 2,
280 A4XX_TEX_CLAMP_TO_BORDER = 3,
281 A4XX_TEX_MIRROR_CLAMP = 4,
282 };
283
284 enum a4xx_tex_aniso {
285 A4XX_TEX_ANISO_1 = 0,
286 A4XX_TEX_ANISO_2 = 1,
287 A4XX_TEX_ANISO_4 = 2,
288 A4XX_TEX_ANISO_8 = 3,
289 A4XX_TEX_ANISO_16 = 4,
290 };
291
292 enum a4xx_tex_swiz {
293 A4XX_TEX_X = 0,
294 A4XX_TEX_Y = 1,
295 A4XX_TEX_Z = 2,
296 A4XX_TEX_W = 3,
297 A4XX_TEX_ZERO = 4,
298 A4XX_TEX_ONE = 5,
299 };
300
301 enum a4xx_tex_type {
302 A4XX_TEX_1D = 0,
303 A4XX_TEX_2D = 1,
304 A4XX_TEX_CUBE = 2,
305 A4XX_TEX_3D = 3,
306 };
307
308 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
309 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
310 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
311 {
312 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
313 }
314 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
315 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
316 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
317 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
318 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
319 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
320 #define A4XX_INT0_VFD_ERROR 0x00000040
321 #define A4XX_INT0_CP_SW_INT 0x00000080
322 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
323 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
324 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
325 #define A4XX_INT0_CP_HW_FAULT 0x00000800
326 #define A4XX_INT0_CP_DMA 0x00001000
327 #define A4XX_INT0_CP_IB2_INT 0x00002000
328 #define A4XX_INT0_CP_IB1_INT 0x00004000
329 #define A4XX_INT0_CP_RB_INT 0x00008000
330 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
331 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000
332 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000
333 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000
334 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
335 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
336 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000
337 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
338 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
339
340 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
341
342 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
343
344 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
345
346 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
347
348 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
349
350 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
351
352 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
353
354 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
355
356 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
357
358 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
359 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
360 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
361 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
362 {
363 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
364 }
365 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
366 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
367 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
368 {
369 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
370 }
371
372 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
373
374 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
375
376 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
377
378 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
379
380 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0
381 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
382 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
383 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
384 {
385 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
386 }
387 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
388 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
389 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
390 {
391 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
392 }
393
394 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
395 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
396 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
397
398 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
399 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
400 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
401 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
402 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
403 {
404 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
405 }
406
407 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
408 #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
409 #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
410 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
411 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
412 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
413 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
414 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
415 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
416 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
417 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
418 {
419 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
420 }
421 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
422 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
423
424 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
425
426 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
427 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
428 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
429 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
430 #define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
431 #define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
432 #define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
433 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
434 {
435 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
436 }
437 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
438 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
439 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
440 {
441 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
442 }
443
444 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
445 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
446 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
447 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
448 {
449 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
450 }
451 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
452 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
453 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
454 {
455 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
456 }
457 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
458 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
459 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
460 {
461 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
462 }
463 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
464 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
465 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
466 {
467 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
468 }
469 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
470 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
471 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
472 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
473 {
474 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
475 }
476
477 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
478
479 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
480 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
481 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
482 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
483 {
484 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
485 }
486
487 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
488 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
489 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
490 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
491 {
492 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
493 }
494 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
495 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
496 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
497 {
498 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
499 }
500 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
501 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
502 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
503 {
504 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
505 }
506 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
507 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
508 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
509 {
510 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
511 }
512 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
513 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
514 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
515 {
516 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
517 }
518 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
519 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
520 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
521 {
522 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
523 }
524
525 #define REG_A4XX_RB_BLEND_RED 0x000020f0
526 #define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff
527 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0
528 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
529 {
530 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
531 }
532 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
533 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
534 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
535 {
536 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
537 }
538
539 #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
540 #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
541 #define A4XX_RB_BLEND_RED_F32__SHIFT 0
542 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
543 {
544 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
545 }
546
547 #define REG_A4XX_RB_BLEND_GREEN 0x000020f2
548 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff
549 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
550 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
551 {
552 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
553 }
554 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
555 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
556 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
557 {
558 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
559 }
560
561 #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
562 #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
563 #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
564 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
565 {
566 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
567 }
568
569 #define REG_A4XX_RB_BLEND_BLUE 0x000020f4
570 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff
571 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
572 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
573 {
574 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
575 }
576 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
577 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
578 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
579 {
580 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
581 }
582
583 #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
584 #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
585 #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
586 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
587 {
588 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
589 }
590
591 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
592 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff
593 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
594 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
595 {
596 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
597 }
598 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
599 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
600 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
601 {
602 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
603 }
604
605 #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
606 #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
607 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
608 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
609 {
610 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
611 }
612
613 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
614 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
615 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
616 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
617 {
618 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
619 }
620 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
621 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
622 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
623 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
624 {
625 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
626 }
627
628 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9
629 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
630 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
631 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
632 {
633 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
634 }
635 #define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
636 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
637 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
638 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
639 {
640 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
641 }
642
643 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
644 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
645 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
646 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
647 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
648 {
649 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
650 }
651
652 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
653 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
654 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
655 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
656 {
657 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
658 }
659 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
660 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
661 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
662 {
663 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
664 }
665 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
666 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
667 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
668 {
669 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
670 }
671 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
672 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
673 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
674 {
675 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
676 }
677 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
678 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
679 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
680 {
681 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
682 }
683 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
684 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
685 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
686 {
687 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
688 }
689 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
690 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
691 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
692 {
693 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
694 }
695 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
696 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
697 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
698 {
699 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
700 }
701
702 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc
703 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
704 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
705 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
706 {
707 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
708 }
709 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
710 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
711 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
712 {
713 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
714 }
715 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
716 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
717 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
718 {
719 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
720 }
721 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
722 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
723 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
724 {
725 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
726 }
727
728 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
729 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
730 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
731 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
732 {
733 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
734 }
735
736 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
737 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
738 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
739 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
740 {
741 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
742 }
743
744 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
745 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
746 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
747 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
748 {
749 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
750 }
751 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
752 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
753 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
754 {
755 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
756 }
757 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
758 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
759 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
760 {
761 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
762 }
763 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
764 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
765 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
766 {
767 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
768 }
769 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
770 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
771 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
772 {
773 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
774 }
775 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
776 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
777 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
778 {
779 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
780 }
781
782 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
783 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
784 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
785 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
786 {
787 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
788 }
789 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
790
791 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
792 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
793 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
794 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
795 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
796 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
797 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
798 {
799 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
800 }
801 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
802 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
803 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
804
805 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
806
807 #define REG_A4XX_RB_DEPTH_INFO 0x00002103
808 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
809 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
810 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
811 {
812 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
813 }
814 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
815 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
816 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
817 {
818 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
819 }
820
821 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104
822 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
823 #define A4XX_RB_DEPTH_PITCH__SHIFT 0
824 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
825 {
826 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
827 }
828
829 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
830 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
831 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0
832 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
833 {
834 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
835 }
836
837 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
838 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
839 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
840 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
841 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
842 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
843 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
844 {
845 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
846 }
847 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
848 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
849 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
850 {
851 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
852 }
853 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
854 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
855 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
856 {
857 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
858 }
859 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
860 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
861 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
862 {
863 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
864 }
865 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
866 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
867 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
868 {
869 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
870 }
871 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
872 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
873 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
874 {
875 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
876 }
877 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
878 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
879 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
880 {
881 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
882 }
883 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
884 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
885 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
886 {
887 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
888 }
889
890 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
891 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
892
893 #define REG_A4XX_RB_STENCIL_INFO 0x00002108
894 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
895 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
896 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
897 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
898 {
899 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
900 }
901
902 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109
903 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
904 #define A4XX_RB_STENCIL_PITCH__SHIFT 0
905 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
906 {
907 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
908 }
909
910 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b
911 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
912 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
913 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
914 {
915 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
916 }
917 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
918 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
919 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
920 {
921 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
922 }
923 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
924 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
925 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
926 {
927 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
928 }
929
930 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
931 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
932 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
933 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
934 {
935 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
936 }
937 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
938 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
939 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
940 {
941 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
942 }
943 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
944 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
945 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
946 {
947 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
948 }
949
950 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d
951 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
952 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
953 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0
954 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
955 {
956 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
957 }
958 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
959 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
960 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
961 {
962 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
963 }
964
965 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
966
967 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
968
969 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
970
971 #define REG_A4XX_RBBM_HW_VERSION 0x00000000
972
973 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
974
975 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
976
977 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
978
979 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
980
981 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
982
983 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
984
985 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
986
987 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
988
989 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
990
991 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
992
993 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
994
995 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
996
997 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
998
999 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
1000
1001 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
1002
1003 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
1004
1005 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
1006
1007 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
1008
1009 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
1010
1011 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
1012
1013 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
1014
1015 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
1016
1017 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
1018
1019 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
1020
1021 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023
1022
1023 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024
1024
1025 #define REG_A4XX_RBBM_AHB_CMD 0x00000025
1026
1027 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
1028
1029 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
1030
1031 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
1032
1033 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
1034
1035 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
1036
1037 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
1038
1039 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037
1040
1041 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
1042
1043 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
1044
1045 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
1046
1047 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
1048
1049 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1050
1051 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
1052
1053 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
1054
1055 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1056
1057 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1058
1059 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1060
1061 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1062
1063 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1064
1065 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1066
1067 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1068
1069 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1070
1071 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1072
1073 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1074
1075 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1076
1077 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1078
1079 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1080
1081 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1082
1083 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1084
1085 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1086
1087 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1088
1089 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1090
1091 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1092
1093 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1094
1095 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1096
1097 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
1098
1099 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
1100
1101 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
1102
1103 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
1104
1105 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
1106
1107 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
1108
1109 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1110
1111 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1112
1113 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
1114
1115 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
1116
1117 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
1118
1119 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
1120
1121 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
1122
1123 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
1124
1125 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
1126
1127 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
1128
1129 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
1130
1131 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
1132
1133 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189
1134
1135 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
1136
1137 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
1138
1139 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
1140
1141 #define REG_A4XX_RBBM_STATUS 0x00000191
1142 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
1143 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1144 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1145 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
1146 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
1147 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
1148 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
1149 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
1150 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1151 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1152 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
1153 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
1154 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
1155 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
1156 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
1157 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
1158 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
1159 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
1160 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1161 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
1162 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
1163
1164 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
1165
1166 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
1167
1168 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
1169
1170 #define REG_A4XX_CP_RB_BASE 0x00000200
1171
1172 #define REG_A4XX_CP_RB_CNTL 0x00000201
1173
1174 #define REG_A4XX_CP_RB_WPTR 0x00000205
1175
1176 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
1177
1178 #define REG_A4XX_CP_RB_RPTR 0x00000204
1179
1180 #define REG_A4XX_CP_IB1_BASE 0x00000206
1181
1182 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207
1183
1184 #define REG_A4XX_CP_IB2_BASE 0x00000208
1185
1186 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209
1187
1188 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
1189
1190 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
1191
1192 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
1193
1194 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
1195
1196 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
1197
1198 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c
1199
1200 #define REG_A4XX_CP_ROQ_DATA 0x0000021d
1201
1202 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e
1203
1204 #define REG_A4XX_CP_MEQ_DATA 0x0000021f
1205
1206 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220
1207
1208 #define REG_A4XX_CP_MERCIU_DATA 0x00000221
1209
1210 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222
1211
1212 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
1213
1214 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
1215
1216 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
1217
1218 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
1219
1220 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227
1221
1222 #define REG_A4XX_CP_PREEMPT 0x0000022a
1223
1224 #define REG_A4XX_CP_CNTL 0x0000022c
1225
1226 #define REG_A4XX_CP_ME_CNTL 0x0000022d
1227
1228 #define REG_A4XX_CP_DEBUG 0x0000022e
1229
1230 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
1231
1232 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
1233
1234 #define REG_A4XX_CP_PROTECT_REG_0 0x00000240
1235
1236 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1237
1238 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1239
1240 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250
1241
1242 #define REG_A4XX_CP_ST_BASE 0x000004c0
1243
1244 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce
1245
1246 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0
1247
1248 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
1249
1250 #define REG_A4XX_CP_HW_FAULT 0x000004d8
1251
1252 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da
1253
1254 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
1255
1256 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
1257
1258 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
1259
1260 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1261
1262 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1263
1264 #define REG_A4XX_SP_VS_STATUS 0x00000ec0
1265
1266 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
1267
1268 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
1269
1270 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
1271 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
1272
1273 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
1274 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
1275 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
1276 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
1277
1278 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
1279 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1280 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1281 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1282 {
1283 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
1284 }
1285 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
1286 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1287 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1288 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1289 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1290 {
1291 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1292 }
1293 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1294 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1295 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1296 {
1297 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1298 }
1299 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1300 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1301 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1302 {
1303 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1304 }
1305 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1306 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
1307 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1308 {
1309 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
1310 }
1311 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1312 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1313
1314 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
1315 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1316 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1317 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1318 {
1319 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
1320 }
1321 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
1322 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
1323 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
1324 {
1325 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
1326 }
1327
1328 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
1329 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
1330 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
1331 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
1332 {
1333 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
1334 }
1335 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
1336 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
1337 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
1338 {
1339 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
1340 }
1341 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
1342 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
1343 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
1344 {
1345 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
1346 }
1347
1348 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1349
1350 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1351 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
1352 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
1353 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
1354 {
1355 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
1356 }
1357 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1358 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
1359 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
1360 {
1361 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
1362 }
1363 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
1364 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
1365 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
1366 {
1367 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
1368 }
1369 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1370 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
1371 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
1372 {
1373 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
1374 }
1375
1376 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1377
1378 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1379 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1380 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
1381 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
1382 {
1383 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
1384 }
1385 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1386 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
1387 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
1388 {
1389 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
1390 }
1391 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1392 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
1393 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
1394 {
1395 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
1396 }
1397 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1398 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
1399 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
1400 {
1401 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
1402 }
1403
1404 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
1405 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1406 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1407 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1408 {
1409 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1410 }
1411 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1412 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1413 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1414 {
1415 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1416 }
1417
1418 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1
1419
1420 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
1421
1422 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
1423
1424 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
1425
1426 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
1427 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
1428 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
1429 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1430 {
1431 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
1432 }
1433 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
1434 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
1435 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1436 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1437 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1438 {
1439 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1440 }
1441 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1442 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1443 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1444 {
1445 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1446 }
1447 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1448 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1449 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1450 {
1451 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1452 }
1453 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1454 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
1455 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1456 {
1457 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
1458 }
1459 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1460 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1461
1462 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
1463 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1464 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1465 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1466 {
1467 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
1468 }
1469 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
1470 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
1471 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
1472
1473 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
1474 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1475 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1476 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1477 {
1478 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1479 }
1480 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1481 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1482 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1483 {
1484 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1485 }
1486
1487 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb
1488
1489 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
1490
1491 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
1492
1493 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
1494
1495 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
1496 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1497 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
1498 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
1499 {
1500 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
1501 }
1502 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
1503 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
1504 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
1505 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
1506 {
1507 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
1508 }
1509 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
1510 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
1511 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
1512 {
1513 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
1514 }
1515
1516 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1517
1518 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1519 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
1520 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
1521 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
1522 {
1523 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
1524 }
1525 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
1526 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
1527 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
1528 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
1529 {
1530 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
1531 }
1532 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
1533
1534 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
1535
1536 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
1537
1538 #define REG_A4XX_SP_CS_OBJ_START 0x00002302
1539
1540 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
1541
1542 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
1543
1544 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
1545
1546 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
1547
1548 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
1549 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1550 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1551 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1552 {
1553 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1554 }
1555 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1556 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1557 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1558 {
1559 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1560 }
1561
1562 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e
1563
1564 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
1565
1566 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
1567
1568 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
1569
1570 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
1571 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
1572 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
1573 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
1574 {
1575 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
1576 }
1577 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1578 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1579 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1580 {
1581 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
1582 }
1583
1584 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1585
1586 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1587 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
1588 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
1589 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
1590 {
1591 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
1592 }
1593 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1594 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
1595 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
1596 {
1597 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
1598 }
1599 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
1600 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
1601 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
1602 {
1603 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
1604 }
1605 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1606 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
1607 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
1608 {
1609 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
1610 }
1611
1612 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1613
1614 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1615 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1616 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
1617 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
1618 {
1619 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
1620 }
1621 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1622 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
1623 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
1624 {
1625 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
1626 }
1627 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1628 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
1629 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
1630 {
1631 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
1632 }
1633 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1634 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
1635 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
1636 {
1637 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
1638 }
1639
1640 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
1641 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1642 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1643 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1644 {
1645 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1646 }
1647 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1648 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1649 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1650 {
1651 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1652 }
1653
1654 #define REG_A4XX_SP_DS_OBJ_START 0x00002335
1655
1656 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
1657
1658 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
1659
1660 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
1661
1662 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341
1663 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
1664 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
1665 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
1666 {
1667 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
1668 }
1669 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
1670 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
1671 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
1672 {
1673 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
1674 }
1675 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1676 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1677 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1678 {
1679 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
1680 }
1681
1682 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1683
1684 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1685 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
1686 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
1687 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
1688 {
1689 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
1690 }
1691 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1692 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
1693 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
1694 {
1695 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
1696 }
1697 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
1698 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
1699 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
1700 {
1701 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
1702 }
1703 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1704 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
1705 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
1706 {
1707 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
1708 }
1709
1710 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1711
1712 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1713 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1714 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
1715 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
1716 {
1717 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
1718 }
1719 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1720 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
1721 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
1722 {
1723 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
1724 }
1725 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1726 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
1727 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
1728 {
1729 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
1730 }
1731 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1732 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
1733 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
1734 {
1735 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
1736 }
1737
1738 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
1739 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1740 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1741 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1742 {
1743 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1744 }
1745 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1746 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1747 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1748 {
1749 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1750 }
1751
1752 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c
1753
1754 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
1755
1756 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
1757
1758 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
1759
1760 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
1761
1762 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
1763
1764 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
1765
1766 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
1767
1768 #define REG_A4XX_VPC_ATTR 0x00002140
1769 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1770 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
1771 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
1772 {
1773 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
1774 }
1775 #define A4XX_VPC_ATTR_PSIZE 0x00000200
1776 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
1777 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1778 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
1779 {
1780 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
1781 }
1782 #define A4XX_VPC_ATTR_ENABLE 0x02000000
1783
1784 #define REG_A4XX_VPC_PACK 0x00002141
1785 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
1786 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
1787 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
1788 {
1789 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
1790 }
1791 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1792 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1793 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
1794 {
1795 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
1796 }
1797 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1798 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1799 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
1800 {
1801 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
1802 }
1803
1804 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1805
1806 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1807
1808 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1809
1810 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1811
1812 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
1813
1814 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00
1815 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1816 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1817 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1818 {
1819 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
1820 }
1821 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1822 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1823 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1824 {
1825 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
1826 }
1827
1828 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
1829
1830 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
1831
1832 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
1833
1834 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1835
1836 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1837 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1838 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1839 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1840 {
1841 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
1842 }
1843 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1844 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1845 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1846 {
1847 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1848 }
1849 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1850 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1851 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1852 {
1853 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
1854 }
1855 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1856 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
1857 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1858 {
1859 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
1860 }
1861
1862 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1863
1864 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1865
1866 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1867
1868 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1869
1870 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
1871
1872 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
1873
1874 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
1875
1876 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
1877
1878 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
1879
1880 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
1881
1882 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
1883
1884 #define REG_A4XX_VFD_CONTROL_0 0x00002200
1885 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
1886 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1887 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1888 {
1889 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1890 }
1891 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
1892 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
1893 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
1894 {
1895 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
1896 }
1897 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
1898 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
1899 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1900 {
1901 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1902 }
1903 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
1904 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
1905 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1906 {
1907 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1908 }
1909
1910 #define REG_A4XX_VFD_CONTROL_1 0x00002201
1911 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1912 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1913 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1914 {
1915 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1916 }
1917 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1918 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1919 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1920 {
1921 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
1922 }
1923 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1924 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1925 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1926 {
1927 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
1928 }
1929
1930 #define REG_A4XX_VFD_CONTROL_2 0x00002202
1931
1932 #define REG_A4XX_VFD_CONTROL_3 0x00002203
1933 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
1934 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
1935 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
1936 {
1937 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
1938 }
1939 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
1940 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
1941 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
1942 {
1943 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
1944 }
1945 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
1946 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
1947 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
1948 {
1949 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
1950 }
1951
1952 #define REG_A4XX_VFD_CONTROL_4 0x00002204
1953
1954 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
1955
1956 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1957
1958 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1959 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1960 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1961 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1962 {
1963 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1964 }
1965 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
1966 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1967 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1968 {
1969 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1970 }
1971 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
1972 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
1973
1974 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
1975
1976 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
1977 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
1978 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
1979 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
1980 {
1981 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
1982 }
1983
1984 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
1985 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
1986 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
1987 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
1988 {
1989 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
1990 }
1991
1992 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1993
1994 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1995 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1996 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1997 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1998 {
1999 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
2000 }
2001 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
2002 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
2003 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
2004 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
2005 {
2006 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
2007 }
2008 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
2009 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
2010 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
2011 {
2012 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
2013 }
2014 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000
2015 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
2016 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
2017 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
2018 {
2019 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
2020 }
2021 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
2022 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
2023 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
2024 {
2025 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
2026 }
2027 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
2028 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
2029
2030 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
2031
2032 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
2033
2034 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
2035
2036 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
2037
2038 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
2039 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
2040 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
2041 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
2042 {
2043 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
2044 }
2045 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
2046 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
2047 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
2048 {
2049 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
2050 }
2051 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
2052 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
2053 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
2054 {
2055 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
2056 }
2057 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
2058 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
2059 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
2060 {
2061 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
2062 }
2063
2064 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
2065
2066 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
2067
2068 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
2069
2070 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
2071
2072 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
2073
2074 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
2075
2076 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
2077
2078 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
2079
2080 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
2081
2082 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
2083
2084 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
2085
2086 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
2087
2088 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
2089
2090 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
2091 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
2092 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
2093
2094 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
2095 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
2096
2097 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
2098 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
2099 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
2100 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
2101 {
2102 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
2103 }
2104 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
2105 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
2106 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
2107 {
2108 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
2109 }
2110
2111 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
2112 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2113 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2114 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2115 {
2116 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2117 }
2118
2119 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
2120 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2121 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2122 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
2123 {
2124 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2125 }
2126
2127 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
2128 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2129 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2130 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2131 {
2132 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2133 }
2134
2135 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
2136 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2137 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2138 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
2139 {
2140 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2141 }
2142
2143 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
2144 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2145 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2146 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2147 {
2148 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2149 }
2150
2151 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
2152 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2153 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2154 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2155 {
2156 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2157 }
2158
2159 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
2160 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2161 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2162 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2163 {
2164 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2165 }
2166 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2167 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2168 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2169 {
2170 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2171 }
2172
2173 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
2174 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2175 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
2176 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
2177 {
2178 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
2179 }
2180
2181 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
2182 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
2183
2184 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
2185 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2186 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2187 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2188 {
2189 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2190 }
2191
2192 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
2193 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2194 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2195 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2196 {
2197 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2198 }
2199
2200 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
2201 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
2202 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
2203 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
2204 {
2205 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
2206 }
2207
2208 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
2209 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
2210 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
2211 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
2212 {
2213 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
2214 }
2215
2216 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
2217 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
2218 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
2219 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
2220 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
2221 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
2222 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
2223 {
2224 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
2225 }
2226 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
2227 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
2228
2229 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
2230 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
2231 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
2232 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
2233 {
2234 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
2235 }
2236 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
2237 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
2238 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
2239 {
2240 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
2241 }
2242 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
2243 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
2244 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
2245 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
2246 {
2247 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
2248 }
2249
2250 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
2251 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2252 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
2253 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
2254 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
2255 {
2256 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
2257 }
2258 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
2259 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
2260 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
2261 {
2262 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
2263 }
2264
2265 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
2266 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2267 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
2268 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
2269 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
2270 {
2271 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
2272 }
2273 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
2274 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
2275 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
2276 {
2277 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
2278 }
2279
2280 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
2281 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2282 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2283 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2284 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2285 {
2286 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2287 }
2288 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2289 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2290 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2291 {
2292 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2293 }
2294
2295 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
2296 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2297 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2298 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2299 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2300 {
2301 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2302 }
2303 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2304 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2305 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2306 {
2307 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2308 }
2309
2310 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
2311 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
2312 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
2313 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
2314 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
2315 {
2316 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
2317 }
2318 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
2319 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
2320 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
2321 {
2322 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
2323 }
2324
2325 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
2326 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
2327 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
2328 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
2329 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
2330 {
2331 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
2332 }
2333 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
2334 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
2335 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
2336 {
2337 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
2338 }
2339
2340 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
2341
2342 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
2343
2344 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
2345
2346 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
2347
2348 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
2349
2350 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
2351
2352 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
2353
2354 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
2355
2356 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
2357
2358 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
2359
2360 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
2361
2362 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
2363
2364 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
2365 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
2366 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
2367 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
2368 {
2369 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
2370 }
2371 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
2372 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
2373 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
2374 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
2375 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
2376 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
2377 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
2378 {
2379 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
2380 }
2381 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
2382 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
2383 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
2384 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
2385
2386 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
2387 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
2388 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
2389 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
2390 {
2391 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
2392 }
2393 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
2394 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
2395 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
2396 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
2397 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
2398 {
2399 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
2400 }
2401 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
2402 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
2403 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
2404 {
2405 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
2406 }
2407
2408 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
2409 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
2410 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
2411 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
2412 {
2413 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
2414 }
2415 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
2416 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
2417 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
2418 {
2419 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
2420 }
2421 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
2422 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
2423 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
2424 {
2425 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
2426 }
2427 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
2428 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
2429 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
2430 {
2431 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
2432 }
2433
2434 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
2435 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
2436 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
2437 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
2438 {
2439 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
2440 }
2441
2442 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
2443
2444 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
2445 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2446 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2447 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2448 {
2449 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
2450 }
2451 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2452 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2453 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2454 {
2455 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2456 }
2457 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
2458 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2459 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2460 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2461 {
2462 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2463 }
2464 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2465 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2466 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2467 {
2468 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
2469 }
2470
2471 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
2472 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2473 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2474 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2475 {
2476 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
2477 }
2478 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2479 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2480 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2481 {
2482 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2483 }
2484 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
2485 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2486 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2487 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2488 {
2489 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2490 }
2491 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2492 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2493 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2494 {
2495 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
2496 }
2497
2498 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
2499 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2500 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2501 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2502 {
2503 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
2504 }
2505 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2506 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2507 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2508 {
2509 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2510 }
2511 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
2512 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2513 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2514 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2515 {
2516 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2517 }
2518 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2519 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2520 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2521 {
2522 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
2523 }
2524
2525 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
2526 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2527 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2528 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2529 {
2530 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
2531 }
2532 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2533 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2534 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2535 {
2536 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2537 }
2538 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
2539 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2540 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2541 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2542 {
2543 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2544 }
2545 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2546 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2547 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2548 {
2549 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
2550 }
2551
2552 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
2553 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2554 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2555 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2556 {
2557 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
2558 }
2559 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2560 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2561 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2562 {
2563 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2564 }
2565 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
2566 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2567 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2568 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2569 {
2570 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2571 }
2572 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2573 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2574 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2575 {
2576 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
2577 }
2578
2579 #define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca
2580
2581 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
2582
2583 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
2584
2585 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
2586
2587 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
2588
2589 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
2590
2591 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
2592
2593 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
2594
2595 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
2596
2597 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
2598
2599 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
2600
2601 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
2602
2603 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
2604
2605 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
2606
2607 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
2608
2609 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
2610
2611 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
2612 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
2613
2614 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
2615
2616 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2617
2618 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2619
2620 #define REG_A4XX_PC_BIN_BASE 0x000021c0
2621
2622 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
2623 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
2624 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
2625 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
2626 {
2627 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
2628 }
2629 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
2630 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
2631 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
2632
2633 #define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
2634 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
2635 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
2636 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
2637 {
2638 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
2639 }
2640 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
2641 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3
2642 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
2643 {
2644 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
2645 }
2646 #define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
2647
2648 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6
2649
2650 #define REG_A4XX_PC_GS_PARAM 0x000021e5
2651 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
2652 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
2653 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
2654 {
2655 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
2656 }
2657 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
2658 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
2659 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
2660 {
2661 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
2662 }
2663 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
2664 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
2665 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2666 {
2667 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
2668 }
2669 #define A4XX_PC_GS_PARAM_LAYER 0x80000000
2670
2671 #define REG_A4XX_PC_HS_PARAM 0x000021e7
2672 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
2673 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
2674 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
2675 {
2676 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
2677 }
2678 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
2679 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
2680 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
2681 {
2682 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
2683 }
2684 #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000
2685 #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23
2686 static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2687 {
2688 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
2689 }
2690
2691 #define REG_A4XX_VBIF_VERSION 0x00003000
2692
2693 #define REG_A4XX_VBIF_CLKON 0x00003001
2694 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
2695
2696 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
2697
2698 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
2699
2700 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2701
2702 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2703
2704 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2705
2706 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
2707
2708 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
2709
2710 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2711
2712 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
2713
2714 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
2715
2716 #define REG_A4XX_UNKNOWN_0D01 0x00000d01
2717
2718 #define REG_A4XX_UNKNOWN_0E42 0x00000e42
2719
2720 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
2721
2722 #define REG_A4XX_UNKNOWN_2001 0x00002001
2723
2724 #define REG_A4XX_UNKNOWN_209B 0x0000209b
2725
2726 #define REG_A4XX_UNKNOWN_20EF 0x000020ef
2727
2728 #define REG_A4XX_UNKNOWN_2152 0x00002152
2729
2730 #define REG_A4XX_UNKNOWN_2153 0x00002153
2731
2732 #define REG_A4XX_UNKNOWN_2154 0x00002154
2733
2734 #define REG_A4XX_UNKNOWN_2155 0x00002155
2735
2736 #define REG_A4XX_UNKNOWN_2156 0x00002156
2737
2738 #define REG_A4XX_UNKNOWN_2157 0x00002157
2739
2740 #define REG_A4XX_UNKNOWN_21C3 0x000021c3
2741
2742 #define REG_A4XX_UNKNOWN_21E6 0x000021e6
2743
2744 #define REG_A4XX_UNKNOWN_2209 0x00002209
2745
2746 #define REG_A4XX_UNKNOWN_22D7 0x000022d7
2747
2748 #define REG_A4XX_UNKNOWN_2352 0x00002352
2749
2750 #define REG_A4XX_TEX_SAMP_0 0x00000000
2751 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
2752 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
2753 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
2754 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
2755 {
2756 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
2757 }
2758 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
2759 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
2760 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
2761 {
2762 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
2763 }
2764 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
2765 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
2766 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
2767 {
2768 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
2769 }
2770 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
2771 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
2772 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
2773 {
2774 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
2775 }
2776 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
2777 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
2778 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
2779 {
2780 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
2781 }
2782 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
2783 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
2784 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
2785 {
2786 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
2787 }
2788 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
2789 #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
2790 static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
2791 {
2792 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
2793 }
2794
2795 #define REG_A4XX_TEX_SAMP_1 0x00000001
2796 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
2797 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
2798 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
2799 {
2800 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
2801 }
2802 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
2803 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
2804 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
2805 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
2806 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
2807 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
2808 {
2809 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
2810 }
2811 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
2812 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
2813 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
2814 {
2815 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
2816 }
2817
2818 #define REG_A4XX_TEX_CONST_0 0x00000000
2819 #define A4XX_TEX_CONST_0_TILED 0x00000001
2820 #define A4XX_TEX_CONST_0_SRGB 0x00000004
2821 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2822 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2823 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
2824 {
2825 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
2826 }
2827 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2828 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2829 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
2830 {
2831 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
2832 }
2833 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2834 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2835 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
2836 {
2837 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
2838 }
2839 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2840 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2841 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
2842 {
2843 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
2844 }
2845 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2846 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2847 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
2848 {
2849 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
2850 }
2851 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2852 #define A4XX_TEX_CONST_0_FMT__SHIFT 22
2853 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
2854 {
2855 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
2856 }
2857 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
2858 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29
2859 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
2860 {
2861 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
2862 }
2863
2864 #define REG_A4XX_TEX_CONST_1 0x00000001
2865 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
2866 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
2867 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
2868 {
2869 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
2870 }
2871 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
2872 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
2873 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
2874 {
2875 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
2876 }
2877
2878 #define REG_A4XX_TEX_CONST_2 0x00000002
2879 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
2880 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
2881 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
2882 {
2883 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
2884 }
2885 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
2886 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9
2887 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
2888 {
2889 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
2890 }
2891 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2892 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30
2893 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
2894 {
2895 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
2896 }
2897
2898 #define REG_A4XX_TEX_CONST_3 0x00000003
2899 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
2900 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
2901 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
2902 {
2903 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
2904 }
2905 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
2906 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
2907 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
2908 {
2909 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
2910 }
2911
2912 #define REG_A4XX_TEX_CONST_4 0x00000004
2913 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
2914 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
2915 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
2916 {
2917 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
2918 }
2919 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
2920 #define A4XX_TEX_CONST_4_BASE__SHIFT 5
2921 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
2922 {
2923 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
2924 }
2925
2926 #define REG_A4XX_TEX_CONST_5 0x00000005
2927
2928 #define REG_A4XX_TEX_CONST_6 0x00000006
2929
2930 #define REG_A4XX_TEX_CONST_7 0x00000007
2931
2932
2933 #endif /* A4XX_XML */