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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a4xx / a4xx.xml.h
1 #ifndef A4XX_XML
2 #define A4XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14895 bytes, from 2015-04-19 15:23:28)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-04-12 18:16:35)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 59314 bytes, from 2015-04-19 16:21:40)
18
19 Copyright (C) 2013-2015 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
21
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
29
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
33
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43
44 enum a4xx_color_fmt {
45 RB4_A8_UNORM = 1,
46 RB4_R8_UNORM = 2,
47 RB4_R4G4B4A4_UNORM = 8,
48 RB4_R5G5B5A1_UNORM = 10,
49 RB4_R5G6R5_UNORM = 14,
50 RB4_R8G8_UNORM = 15,
51 RB4_R8G8_SNORM = 16,
52 RB4_R8G8_UINT = 17,
53 RB4_R8G8_SINT = 18,
54 RB4_R16_FLOAT = 21,
55 RB4_R16_UINT = 22,
56 RB4_R16_SINT = 23,
57 RB4_R8G8B8_UNORM = 25,
58 RB4_R8G8B8A8_UNORM = 26,
59 RB4_R8G8B8A8_SNORM = 28,
60 RB4_R8G8B8A8_UINT = 29,
61 RB4_R8G8B8A8_SINT = 30,
62 RB4_R10G10B10A2_UNORM = 31,
63 RB4_R10G10B10A2_UINT = 34,
64 RB4_R11G11B10_FLOAT = 39,
65 RB4_R16G16_FLOAT = 42,
66 RB4_R16G16_UINT = 43,
67 RB4_R16G16_SINT = 44,
68 RB4_R32_FLOAT = 45,
69 RB4_R32_UINT = 46,
70 RB4_R32_SINT = 47,
71 RB4_R16G16B16A16_FLOAT = 54,
72 RB4_R16G16B16A16_UINT = 55,
73 RB4_R16G16B16A16_SINT = 56,
74 RB4_R32G32_FLOAT = 57,
75 RB4_R32G32_UINT = 58,
76 RB4_R32G32_SINT = 59,
77 RB4_R32G32B32A32_FLOAT = 60,
78 RB4_R32G32B32A32_UINT = 61,
79 RB4_R32G32B32A32_SINT = 62,
80 };
81
82 enum a4xx_tile_mode {
83 TILE4_LINEAR = 0,
84 TILE4_3 = 3,
85 };
86
87 enum a4xx_rb_blend_opcode {
88 BLEND_DST_PLUS_SRC = 0,
89 BLEND_SRC_MINUS_DST = 1,
90 BLEND_DST_MINUS_SRC = 2,
91 BLEND_MIN_DST_SRC = 3,
92 BLEND_MAX_DST_SRC = 4,
93 };
94
95 enum a4xx_vtx_fmt {
96 VFMT4_32_FLOAT = 1,
97 VFMT4_32_32_FLOAT = 2,
98 VFMT4_32_32_32_FLOAT = 3,
99 VFMT4_32_32_32_32_FLOAT = 4,
100 VFMT4_16_FLOAT = 5,
101 VFMT4_16_16_FLOAT = 6,
102 VFMT4_16_16_16_FLOAT = 7,
103 VFMT4_16_16_16_16_FLOAT = 8,
104 VFMT4_32_FIXED = 9,
105 VFMT4_32_32_FIXED = 10,
106 VFMT4_32_32_32_FIXED = 11,
107 VFMT4_32_32_32_32_FIXED = 12,
108 VFMT4_16_SINT = 16,
109 VFMT4_16_16_SINT = 17,
110 VFMT4_16_16_16_SINT = 18,
111 VFMT4_16_16_16_16_SINT = 19,
112 VFMT4_16_UINT = 20,
113 VFMT4_16_16_UINT = 21,
114 VFMT4_16_16_16_UINT = 22,
115 VFMT4_16_16_16_16_UINT = 23,
116 VFMT4_16_SNORM = 24,
117 VFMT4_16_16_SNORM = 25,
118 VFMT4_16_16_16_SNORM = 26,
119 VFMT4_16_16_16_16_SNORM = 27,
120 VFMT4_16_UNORM = 28,
121 VFMT4_16_16_UNORM = 29,
122 VFMT4_16_16_16_UNORM = 30,
123 VFMT4_16_16_16_16_UNORM = 31,
124 VFMT4_32_UINT = 32,
125 VFMT4_32_32_UINT = 33,
126 VFMT4_32_32_32_UINT = 34,
127 VFMT4_32_32_32_32_UINT = 35,
128 VFMT4_32_SINT = 36,
129 VFMT4_32_32_SINT = 37,
130 VFMT4_32_32_32_SINT = 38,
131 VFMT4_32_32_32_32_SINT = 39,
132 VFMT4_8_UINT = 40,
133 VFMT4_8_8_UINT = 41,
134 VFMT4_8_8_8_UINT = 42,
135 VFMT4_8_8_8_8_UINT = 43,
136 VFMT4_8_UNORM = 44,
137 VFMT4_8_8_UNORM = 45,
138 VFMT4_8_8_8_UNORM = 46,
139 VFMT4_8_8_8_8_UNORM = 47,
140 VFMT4_8_SINT = 48,
141 VFMT4_8_8_SINT = 49,
142 VFMT4_8_8_8_SINT = 50,
143 VFMT4_8_8_8_8_SINT = 51,
144 VFMT4_8_SNORM = 52,
145 VFMT4_8_8_SNORM = 53,
146 VFMT4_8_8_8_SNORM = 54,
147 VFMT4_8_8_8_8_SNORM = 55,
148 VFMT4_10_10_10_2_UINT = 60,
149 VFMT4_10_10_10_2_UNORM = 61,
150 VFMT4_10_10_10_2_SINT = 62,
151 VFMT4_10_10_10_2_SNORM = 63,
152 };
153
154 enum a4xx_tex_fmt {
155 TFMT4_5_6_5_UNORM = 11,
156 TFMT4_5_5_5_1_UNORM = 10,
157 TFMT4_4_4_4_4_UNORM = 8,
158 TFMT4_X8Z24_UNORM = 71,
159 TFMT4_10_10_10_2_UNORM = 33,
160 TFMT4_A8_UNORM = 3,
161 TFMT4_L8_A8_UNORM = 13,
162 TFMT4_8_UNORM = 4,
163 TFMT4_8_8_UNORM = 14,
164 TFMT4_8_8_8_8_UNORM = 28,
165 TFMT4_8_8_SNORM = 15,
166 TFMT4_8_8_8_8_SNORM = 29,
167 TFMT4_8_8_UINT = 16,
168 TFMT4_8_8_8_8_UINT = 30,
169 TFMT4_8_8_SINT = 17,
170 TFMT4_8_8_8_8_SINT = 31,
171 TFMT4_16_UINT = 21,
172 TFMT4_16_16_UINT = 41,
173 TFMT4_16_16_16_16_UINT = 54,
174 TFMT4_16_SINT = 22,
175 TFMT4_16_16_SINT = 42,
176 TFMT4_16_16_16_16_SINT = 55,
177 TFMT4_32_UINT = 44,
178 TFMT4_32_32_UINT = 57,
179 TFMT4_32_32_32_32_UINT = 64,
180 TFMT4_32_SINT = 45,
181 TFMT4_32_32_SINT = 58,
182 TFMT4_32_32_32_32_SINT = 65,
183 TFMT4_16_FLOAT = 20,
184 TFMT4_16_16_FLOAT = 40,
185 TFMT4_16_16_16_16_FLOAT = 53,
186 TFMT4_32_FLOAT = 43,
187 TFMT4_32_32_FLOAT = 56,
188 TFMT4_32_32_32_32_FLOAT = 63,
189 TFMT4_9_9_9_E5_FLOAT = 32,
190 TFMT4_11_11_10_FLOAT = 37,
191 TFMT4_ATC_RGB = 100,
192 TFMT4_ATC_RGBA_EXPLICIT = 101,
193 TFMT4_ATC_RGBA_INTERPOLATED = 102,
194 TFMT4_ETC2_RG11_UNORM = 103,
195 TFMT4_ETC2_RG11_SNORM = 104,
196 TFMT4_ETC2_R11_UNORM = 105,
197 TFMT4_ETC2_R11_SNORM = 106,
198 TFMT4_ETC1 = 107,
199 TFMT4_ETC2_RGB8 = 108,
200 TFMT4_ETC2_RGBA8 = 109,
201 TFMT4_ETC2_RGB8A1 = 110,
202 TFMT4_ASTC_4x4 = 111,
203 TFMT4_ASTC_5x4 = 112,
204 TFMT4_ASTC_5x5 = 113,
205 TFMT4_ASTC_6x5 = 114,
206 TFMT4_ASTC_6x6 = 115,
207 TFMT4_ASTC_8x5 = 116,
208 TFMT4_ASTC_8x6 = 117,
209 TFMT4_ASTC_8x8 = 118,
210 TFMT4_ASTC_10x5 = 119,
211 TFMT4_ASTC_10x6 = 120,
212 TFMT4_ASTC_10x8 = 121,
213 TFMT4_ASTC_10x10 = 122,
214 TFMT4_ASTC_12x10 = 123,
215 TFMT4_ASTC_12x12 = 124,
216 };
217
218 enum a4xx_tex_fetchsize {
219 TFETCH4_1_BYTE = 0,
220 TFETCH4_2_BYTE = 1,
221 TFETCH4_4_BYTE = 2,
222 TFETCH4_8_BYTE = 3,
223 TFETCH4_16_BYTE = 4,
224 };
225
226 enum a4xx_depth_format {
227 DEPTH4_NONE = 0,
228 DEPTH4_16 = 1,
229 DEPTH4_24_8 = 2,
230 };
231
232 enum a4xx_tess_spacing {
233 EQUAL_SPACING = 0,
234 ODD_SPACING = 2,
235 EVEN_SPACING = 3,
236 };
237
238 enum a4xx_tex_filter {
239 A4XX_TEX_NEAREST = 0,
240 A4XX_TEX_LINEAR = 1,
241 A4XX_TEX_ANISO = 2,
242 };
243
244 enum a4xx_tex_clamp {
245 A4XX_TEX_REPEAT = 0,
246 A4XX_TEX_CLAMP_TO_EDGE = 1,
247 A4XX_TEX_MIRROR_REPEAT = 2,
248 A4XX_TEX_CLAMP_NONE = 3,
249 };
250
251 enum a4xx_tex_aniso {
252 A4XX_TEX_ANISO_1 = 0,
253 A4XX_TEX_ANISO_2 = 1,
254 A4XX_TEX_ANISO_4 = 2,
255 A4XX_TEX_ANISO_8 = 3,
256 A4XX_TEX_ANISO_16 = 4,
257 };
258
259 enum a4xx_tex_swiz {
260 A4XX_TEX_X = 0,
261 A4XX_TEX_Y = 1,
262 A4XX_TEX_Z = 2,
263 A4XX_TEX_W = 3,
264 A4XX_TEX_ZERO = 4,
265 A4XX_TEX_ONE = 5,
266 };
267
268 enum a4xx_tex_type {
269 A4XX_TEX_1D = 0,
270 A4XX_TEX_2D = 1,
271 A4XX_TEX_CUBE = 2,
272 A4XX_TEX_3D = 3,
273 };
274
275 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
276 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
277 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
278 {
279 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
280 }
281 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
282 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
283 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
284 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
285 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
286 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
287 #define A4XX_INT0_VFD_ERROR 0x00000040
288 #define A4XX_INT0_CP_SW_INT 0x00000080
289 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
290 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
291 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
292 #define A4XX_INT0_CP_HW_FAULT 0x00000800
293 #define A4XX_INT0_CP_DMA 0x00001000
294 #define A4XX_INT0_CP_IB2_INT 0x00002000
295 #define A4XX_INT0_CP_IB1_INT 0x00004000
296 #define A4XX_INT0_CP_RB_INT 0x00008000
297 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
298 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000
299 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000
300 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000
301 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
302 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
303 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000
304 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
305 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
306
307 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
308
309 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
310
311 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
312
313 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
314
315 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
316
317 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
318
319 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
320
321 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
322
323 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
324
325 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
326 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
327 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
328 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
329 {
330 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
331 }
332 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
333 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
334 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
335 {
336 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
337 }
338
339 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
340
341 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
342
343 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
344
345 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
346
347 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0
348 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
349 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
350 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
351 {
352 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
353 }
354 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
355 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
356 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
357 {
358 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
359 }
360
361 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
362 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
363 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
364
365 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
366 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
367 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
368 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
369 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
370 {
371 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
372 }
373
374 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
375 #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
376 #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
377 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
378 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
379 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
380 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
381 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
382 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
383 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
384 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
385 {
386 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
387 }
388 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
389 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
390
391 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
392
393 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
394 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
395 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
396 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
397 #define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400
398 #define A4XX_RB_MRT_CONTROL_B11 0x00000800
399 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
400 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
401 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
402 {
403 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
404 }
405
406 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
407 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
408 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
409 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
410 {
411 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
412 }
413 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
414 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
415 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
416 {
417 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
418 }
419 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
420 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
421 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
422 {
423 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
424 }
425 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
426 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
427 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
428 {
429 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
430 }
431 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
432 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0x007fc000
433 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
434 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
435 {
436 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
437 }
438
439 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
440
441 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
442 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x0001fff8
443 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
444 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
445 {
446 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
447 }
448
449 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
450 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
451 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
452 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
453 {
454 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
455 }
456 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
457 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
458 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
459 {
460 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
461 }
462 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
463 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
464 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
465 {
466 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
467 }
468 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
469 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
470 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
471 {
472 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
473 }
474 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
475 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
476 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
477 {
478 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
479 }
480 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
481 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
482 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
483 {
484 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
485 }
486
487 #define REG_A4XX_RB_BLEND_RED 0x000020f3
488 #define A4XX_RB_BLEND_RED_UINT__MASK 0x00007fff
489 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0
490 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
491 {
492 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
493 }
494 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
495 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
496 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
497 {
498 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
499 }
500
501 #define REG_A4XX_RB_BLEND_GREEN 0x000020f4
502 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x00007fff
503 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
504 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
505 {
506 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
507 }
508 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
509 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
510 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
511 {
512 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
513 }
514
515 #define REG_A4XX_RB_BLEND_BLUE 0x000020f5
516 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x00007fff
517 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
518 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
519 {
520 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
521 }
522 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
523 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
524 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
525 {
526 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
527 }
528
529 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
530 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x00007fff
531 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
532 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
533 {
534 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
535 }
536 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
537 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
538 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
539 {
540 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
541 }
542
543 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
544 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
545 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
546 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
547 {
548 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
549 }
550 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
551 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
552 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
553 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
554 {
555 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
556 }
557
558 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9
559 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
560 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
561 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
562 {
563 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
564 }
565 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100
566 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
567 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
568 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
569 {
570 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
571 }
572
573 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
574 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
575 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
576 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
577 {
578 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
579 }
580 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
581 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
582 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
583 {
584 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
585 }
586 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
587 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
588 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
589 {
590 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
591 }
592 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
593 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
594 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
595 {
596 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
597 }
598 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
599 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
600 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
601 {
602 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
603 }
604 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
605 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
606 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
607 {
608 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
609 }
610 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
611 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
612 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
613 {
614 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
615 }
616 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
617 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
618 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
619 {
620 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
621 }
622
623 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc
624 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
625 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
626 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
627 {
628 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
629 }
630 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
631 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
632 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
633 {
634 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
635 }
636 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
637 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
638 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
639 {
640 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
641 }
642 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
643 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
644 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
645 {
646 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
647 }
648
649 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
650 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
651 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
652 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
653 {
654 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
655 }
656
657 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
658 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
659 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
660 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
661 {
662 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
663 }
664
665 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
666 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
667 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
668 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
669 {
670 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
671 }
672 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
673 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
674 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
675 {
676 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
677 }
678 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
679 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
680 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
681 {
682 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
683 }
684 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
685 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
686 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
687 {
688 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
689 }
690 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
691 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
692 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
693 {
694 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
695 }
696 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
697 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
698 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
699 {
700 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
701 }
702
703 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
704 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
705 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
706 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
707 {
708 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
709 }
710 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
711
712 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
713 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
714 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
715 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
716 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
717 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
718 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
719 {
720 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
721 }
722 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
723 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
724 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
725
726 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
727
728 #define REG_A4XX_RB_DEPTH_INFO 0x00002103
729 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
730 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
731 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
732 {
733 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
734 }
735 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
736 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
737 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
738 {
739 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
740 }
741
742 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104
743 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
744 #define A4XX_RB_DEPTH_PITCH__SHIFT 0
745 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
746 {
747 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
748 }
749
750 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
751 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
752 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0
753 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
754 {
755 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
756 }
757
758 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
759 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
760 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
761 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
762 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
763 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
764 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
765 {
766 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
767 }
768 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
769 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
770 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
771 {
772 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
773 }
774 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
775 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
776 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
777 {
778 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
779 }
780 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
781 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
782 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
783 {
784 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
785 }
786 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
787 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
788 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
789 {
790 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
791 }
792 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
793 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
794 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
795 {
796 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
797 }
798 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
799 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
800 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
801 {
802 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
803 }
804 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
805 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
806 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
807 {
808 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
809 }
810
811 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
812 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
813
814 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b
815 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
816 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
817 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
818 {
819 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
820 }
821 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
822 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
823 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
824 {
825 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
826 }
827 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
828 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
829 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
830 {
831 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
832 }
833
834 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
835 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
836 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
837 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
838 {
839 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
840 }
841 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
842 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
843 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
844 {
845 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
846 }
847 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
848 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
849 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
850 {
851 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
852 }
853
854 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d
855 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
856 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
857 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0
858 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
859 {
860 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
861 }
862 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
863 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
864 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
865 {
866 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
867 }
868
869 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
870
871 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
872
873 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
874
875 #define REG_A4XX_RBBM_HW_VERSION 0x00000000
876
877 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
878
879 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
880
881 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
882
883 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
884
885 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
886
887 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
888
889 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
890
891 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
892
893 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
894
895 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
896
897 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
898
899 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
900
901 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
902
903 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
904
905 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
906
907 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
908
909 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
910
911 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
912
913 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
914
915 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
916
917 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
918
919 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
920
921 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
922
923 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
924
925 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023
926
927 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024
928
929 #define REG_A4XX_RBBM_AHB_CMD 0x00000025
930
931 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
932
933 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
934
935 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
936
937 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
938
939 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
940
941 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
942
943 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037
944
945 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
946
947 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
948
949 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
950
951 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
952
953 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
954
955 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
956
957 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
958
959 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
960
961 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
962
963 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
964
965 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
966
967 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
968
969 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
970
971 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
972
973 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
974
975 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
976
977 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
978
979 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
980
981 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
982
983 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
984
985 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
986
987 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
988
989 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
990
991 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
992
993 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
994
995 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
996
997 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
998
999 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1000
1001 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
1002
1003 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
1004
1005 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
1006
1007 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
1008
1009 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
1010
1011 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
1012
1013 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1014
1015 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1016
1017 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
1018
1019 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
1020
1021 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
1022
1023 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
1024
1025 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
1026
1027 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
1028
1029 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
1030
1031 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
1032
1033 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
1034
1035 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
1036
1037 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189
1038
1039 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
1040
1041 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
1042
1043 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
1044
1045 #define REG_A4XX_RBBM_STATUS 0x00000191
1046 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
1047 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1048 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1049 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
1050 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
1051 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
1052 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
1053 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
1054 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1055 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1056 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
1057 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
1058 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
1059 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
1060 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
1061 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
1062 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
1063 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
1064 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1065 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
1066 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
1067
1068 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
1069
1070 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
1071
1072 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
1073
1074 #define REG_A4XX_CP_RB_BASE 0x00000200
1075
1076 #define REG_A4XX_CP_RB_CNTL 0x00000201
1077
1078 #define REG_A4XX_CP_RB_WPTR 0x00000205
1079
1080 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
1081
1082 #define REG_A4XX_CP_RB_RPTR 0x00000204
1083
1084 #define REG_A4XX_CP_IB1_BASE 0x00000206
1085
1086 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207
1087
1088 #define REG_A4XX_CP_IB2_BASE 0x00000208
1089
1090 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209
1091
1092 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
1093
1094 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
1095
1096 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
1097
1098 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
1099
1100 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
1101
1102 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c
1103
1104 #define REG_A4XX_CP_ROQ_DATA 0x0000021d
1105
1106 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e
1107
1108 #define REG_A4XX_CP_MEQ_DATA 0x0000021f
1109
1110 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220
1111
1112 #define REG_A4XX_CP_MERCIU_DATA 0x00000221
1113
1114 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222
1115
1116 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
1117
1118 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
1119
1120 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
1121
1122 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
1123
1124 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227
1125
1126 #define REG_A4XX_CP_PREEMPT 0x0000022a
1127
1128 #define REG_A4XX_CP_CNTL 0x0000022c
1129
1130 #define REG_A4XX_CP_ME_CNTL 0x0000022d
1131
1132 #define REG_A4XX_CP_DEBUG 0x0000022e
1133
1134 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
1135
1136 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
1137
1138 #define REG_A4XX_CP_PROTECT_REG_0 0x00000240
1139
1140 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1141
1142 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1143
1144 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250
1145
1146 #define REG_A4XX_CP_ST_BASE 0x000004c0
1147
1148 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce
1149
1150 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0
1151
1152 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
1153
1154 #define REG_A4XX_CP_HW_FAULT 0x000004d8
1155
1156 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da
1157
1158 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
1159
1160 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
1161
1162 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
1163
1164 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1165
1166 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1167
1168 #define REG_A4XX_SP_VS_STATUS 0x00000ec0
1169
1170 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
1171
1172 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
1173 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
1174
1175 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
1176 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
1177 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
1178 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
1179
1180 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
1181 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1182 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1183 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1184 {
1185 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
1186 }
1187 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
1188 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1189 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1190 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1191 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1192 {
1193 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1194 }
1195 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1196 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1197 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1198 {
1199 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1200 }
1201 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1202 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1203 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1204 {
1205 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1206 }
1207 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1208 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
1209 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1210 {
1211 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
1212 }
1213 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1214 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1215
1216 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
1217 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1218 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1219 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1220 {
1221 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
1222 }
1223 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
1224 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
1225 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
1226 {
1227 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
1228 }
1229
1230 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
1231 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
1232 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
1233 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
1234 {
1235 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
1236 }
1237 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
1238 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
1239 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
1240 {
1241 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
1242 }
1243 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
1244 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
1245 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
1246 {
1247 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
1248 }
1249
1250 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1251
1252 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1253 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
1254 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
1255 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
1256 {
1257 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
1258 }
1259 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1260 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
1261 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
1262 {
1263 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
1264 }
1265 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
1266 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
1267 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
1268 {
1269 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
1270 }
1271 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1272 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
1273 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
1274 {
1275 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
1276 }
1277
1278 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1279
1280 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1281 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1282 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
1283 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
1284 {
1285 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
1286 }
1287 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1288 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
1289 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
1290 {
1291 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
1292 }
1293 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1294 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
1295 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
1296 {
1297 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
1298 }
1299 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1300 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
1301 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
1302 {
1303 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
1304 }
1305
1306 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
1307 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1308 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1309 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1310 {
1311 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1312 }
1313 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1314 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1315 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1316 {
1317 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1318 }
1319
1320 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1
1321
1322 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
1323
1324 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
1325
1326 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
1327
1328 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
1329 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
1330 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
1331 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1332 {
1333 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
1334 }
1335 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
1336 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
1337 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1338 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1339 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1340 {
1341 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1342 }
1343 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1344 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1345 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1346 {
1347 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1348 }
1349 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1350 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1351 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1352 {
1353 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1354 }
1355 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1356 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
1357 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1358 {
1359 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
1360 }
1361 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1362 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1363
1364 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
1365 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1366 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1367 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1368 {
1369 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
1370 }
1371 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
1372 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
1373 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
1374
1375 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
1376 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1377 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1378 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1379 {
1380 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1381 }
1382 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1383 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1384 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1385 {
1386 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1387 }
1388
1389 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb
1390
1391 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
1392
1393 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
1394
1395 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
1396
1397 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
1398 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1399 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
1400 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
1401 {
1402 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
1403 }
1404 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
1405 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
1406 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
1407 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
1408 {
1409 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
1410 }
1411 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
1412 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
1413 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
1414 {
1415 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
1416 }
1417
1418 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1419
1420 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1421 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
1422 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
1423 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
1424 {
1425 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
1426 }
1427 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
1428 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
1429 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
1430 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
1431 {
1432 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
1433 }
1434
1435 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
1436 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1437 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1438 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1439 {
1440 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1441 }
1442 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1443 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1444 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1445 {
1446 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1447 }
1448
1449 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e
1450
1451 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
1452
1453 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
1454
1455 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
1456
1457 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
1458 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1459 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1460 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1461 {
1462 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1463 }
1464 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1465 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1466 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1467 {
1468 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1469 }
1470
1471 #define REG_A4XX_SP_DS_OBJ_START 0x00002335
1472
1473 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
1474
1475 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
1476
1477 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
1478
1479 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
1480 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1481 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1482 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1483 {
1484 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1485 }
1486 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1487 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1488 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1489 {
1490 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1491 }
1492
1493 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c
1494
1495 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
1496
1497 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
1498
1499 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
1500
1501 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
1502
1503 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
1504
1505 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
1506
1507 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
1508
1509 #define REG_A4XX_VPC_ATTR 0x00002140
1510 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1511 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
1512 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
1513 {
1514 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
1515 }
1516 #define A4XX_VPC_ATTR_PSIZE 0x00000200
1517 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
1518 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1519 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
1520 {
1521 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
1522 }
1523 #define A4XX_VPC_ATTR_ENABLE 0x02000000
1524
1525 #define REG_A4XX_VPC_PACK 0x00002141
1526 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
1527 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
1528 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
1529 {
1530 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
1531 }
1532 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1533 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1534 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
1535 {
1536 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
1537 }
1538 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1539 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1540 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
1541 {
1542 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
1543 }
1544
1545 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1546
1547 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1548
1549 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1550
1551 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1552
1553 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
1554
1555 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00
1556 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1557 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1558 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1559 {
1560 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
1561 }
1562 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1563 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1564 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1565 {
1566 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
1567 }
1568
1569 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
1570
1571 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
1572
1573 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
1574
1575 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1576
1577 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1578 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1579 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1580 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1581 {
1582 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
1583 }
1584 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1585 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1586 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1587 {
1588 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1589 }
1590 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1591 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1592 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1593 {
1594 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
1595 }
1596 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1597 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
1598 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1599 {
1600 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
1601 }
1602
1603 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1604
1605 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1606
1607 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1608
1609 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1610
1611 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
1612
1613 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
1614
1615 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
1616
1617 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
1618
1619 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
1620
1621 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
1622
1623 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
1624
1625 #define REG_A4XX_VFD_CONTROL_0 0x00002200
1626 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
1627 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1628 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1629 {
1630 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1631 }
1632 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
1633 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
1634 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
1635 {
1636 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
1637 }
1638 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
1639 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
1640 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1641 {
1642 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1643 }
1644 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
1645 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
1646 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1647 {
1648 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1649 }
1650
1651 #define REG_A4XX_VFD_CONTROL_1 0x00002201
1652 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1653 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1654 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1655 {
1656 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1657 }
1658 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1659 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1660 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1661 {
1662 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
1663 }
1664 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1665 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1666 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1667 {
1668 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
1669 }
1670
1671 #define REG_A4XX_VFD_CONTROL_2 0x00002202
1672
1673 #define REG_A4XX_VFD_CONTROL_3 0x00002203
1674 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
1675 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
1676 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
1677 {
1678 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
1679 }
1680
1681 #define REG_A4XX_VFD_CONTROL_4 0x00002204
1682
1683 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
1684
1685 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1686
1687 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1688 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1689 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1690 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1691 {
1692 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1693 }
1694 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
1695 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1696 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1697 {
1698 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1699 }
1700 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
1701 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
1702
1703 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
1704
1705 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
1706 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
1707 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
1708 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
1709 {
1710 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
1711 }
1712
1713 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
1714 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
1715 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
1716 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
1717 {
1718 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
1719 }
1720
1721 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1722
1723 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1724 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1725 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1726 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1727 {
1728 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
1729 }
1730 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
1731 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
1732 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
1733 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
1734 {
1735 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
1736 }
1737 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
1738 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
1739 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
1740 {
1741 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
1742 }
1743 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000
1744 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
1745 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
1746 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
1747 {
1748 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
1749 }
1750 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
1751 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
1752 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
1753 {
1754 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
1755 }
1756 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
1757 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
1758
1759 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
1760
1761 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
1762
1763 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
1764
1765 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
1766 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
1767 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
1768 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
1769 {
1770 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
1771 }
1772 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
1773 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
1774 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
1775 {
1776 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
1777 }
1778 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
1779 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
1780 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
1781 {
1782 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
1783 }
1784 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
1785 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
1786 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
1787 {
1788 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
1789 }
1790
1791 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
1792
1793 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
1794
1795 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
1796
1797 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
1798
1799 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
1800
1801 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
1802
1803 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
1804
1805 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
1806
1807 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
1808
1809 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
1810
1811 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
1812
1813 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
1814
1815 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
1816 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
1817
1818 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
1819 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
1820 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
1821 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
1822 {
1823 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
1824 }
1825 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
1826 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
1827 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
1828 {
1829 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
1830 }
1831
1832 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
1833 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
1834 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
1835 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
1836 {
1837 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
1838 }
1839
1840 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
1841 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
1842 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
1843 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
1844 {
1845 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
1846 }
1847
1848 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
1849 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
1850 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
1851 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
1852 {
1853 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
1854 }
1855
1856 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
1857 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
1858 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
1859 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
1860 {
1861 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
1862 }
1863
1864 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
1865 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
1866 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
1867 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
1868 {
1869 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
1870 }
1871
1872 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
1873 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
1874 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
1875 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
1876 {
1877 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
1878 }
1879
1880 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
1881 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
1882 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
1883 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
1884 {
1885 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
1886 }
1887 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
1888 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
1889 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
1890 {
1891 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
1892 }
1893
1894 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
1895 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
1896 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
1897 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
1898 {
1899 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
1900 }
1901
1902 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
1903 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
1904
1905 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
1906 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
1907 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
1908 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
1909 {
1910 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
1911 }
1912
1913 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
1914 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
1915 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
1916 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
1917 {
1918 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
1919 }
1920
1921 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
1922 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
1923 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
1924 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
1925 {
1926 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
1927 }
1928
1929 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
1930 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
1931 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
1932 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
1933 {
1934 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
1935 }
1936
1937 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
1938 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
1939 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
1940 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
1941 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
1942 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
1943 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
1944 {
1945 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
1946 }
1947 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
1948 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
1949
1950 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
1951 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
1952 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
1953 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
1954 {
1955 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
1956 }
1957 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
1958 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
1959 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
1960 {
1961 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
1962 }
1963 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
1964 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
1965 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
1966 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
1967 {
1968 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
1969 }
1970
1971 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
1972 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
1973 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
1974 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
1975 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
1976 {
1977 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
1978 }
1979 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
1980 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
1981 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
1982 {
1983 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
1984 }
1985
1986 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
1987 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
1988 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
1989 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
1990 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
1991 {
1992 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
1993 }
1994 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
1995 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
1996 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
1997 {
1998 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
1999 }
2000
2001 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
2002 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2003 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2004 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2005 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2006 {
2007 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2008 }
2009 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2010 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2011 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2012 {
2013 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2014 }
2015
2016 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
2017 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2018 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2019 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2020 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2021 {
2022 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2023 }
2024 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2025 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2026 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2027 {
2028 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2029 }
2030
2031 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
2032 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
2033 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
2034 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
2035 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
2036 {
2037 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
2038 }
2039 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
2040 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
2041 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
2042 {
2043 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
2044 }
2045
2046 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
2047 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
2048 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
2049 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
2050 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
2051 {
2052 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
2053 }
2054 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
2055 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
2056 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
2057 {
2058 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
2059 }
2060
2061 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
2062
2063 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
2064
2065 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
2066
2067 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
2068
2069 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
2070
2071 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
2072
2073 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
2074
2075 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
2076
2077 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
2078
2079 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
2080
2081 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
2082
2083 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
2084 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
2085 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
2086 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
2087 {
2088 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
2089 }
2090 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
2091 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
2092 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
2093 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
2094 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
2095 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
2096 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
2097 {
2098 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
2099 }
2100 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
2101 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
2102 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
2103 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
2104
2105 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
2106 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
2107 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
2108 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
2109 {
2110 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
2111 }
2112 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
2113 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
2114 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
2115 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
2116 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
2117 {
2118 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
2119 }
2120 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
2121 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
2122 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
2123 {
2124 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
2125 }
2126
2127 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
2128 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
2129 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
2130 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
2131 {
2132 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
2133 }
2134 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
2135 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
2136 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
2137 {
2138 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
2139 }
2140 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
2141 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
2142 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
2143 {
2144 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
2145 }
2146 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
2147 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
2148 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
2149 {
2150 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
2151 }
2152
2153 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
2154 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
2155 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
2156 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
2157 {
2158 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
2159 }
2160
2161 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
2162 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2163 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2164 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2165 {
2166 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
2167 }
2168 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2169 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2170 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2171 {
2172 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2173 }
2174 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
2175 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2176 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2177 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2178 {
2179 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2180 }
2181 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2182 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2183 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2184 {
2185 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
2186 }
2187
2188 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
2189 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2190 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2191 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2192 {
2193 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
2194 }
2195 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2196 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2197 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2198 {
2199 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2200 }
2201 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
2202 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2203 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2204 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2205 {
2206 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2207 }
2208 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2209 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2210 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2211 {
2212 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
2213 }
2214
2215 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
2216 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2217 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2218 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2219 {
2220 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
2221 }
2222 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2223 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2224 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2225 {
2226 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2227 }
2228 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
2229 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2230 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2231 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2232 {
2233 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2234 }
2235 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2236 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2237 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2238 {
2239 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
2240 }
2241
2242 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
2243 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2244 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2245 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2246 {
2247 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
2248 }
2249 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2250 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2251 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2252 {
2253 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2254 }
2255 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
2256 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2257 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2258 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2259 {
2260 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2261 }
2262 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2263 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2264 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2265 {
2266 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
2267 }
2268
2269 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
2270 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2271 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2272 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2273 {
2274 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
2275 }
2276 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2277 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2278 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2279 {
2280 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2281 }
2282 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
2283 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2284 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2285 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2286 {
2287 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2288 }
2289 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2290 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2291 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2292 {
2293 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
2294 }
2295
2296 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
2297
2298 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
2299 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
2300
2301 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
2302
2303 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2304
2305 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2306
2307 #define REG_A4XX_PC_BIN_BASE 0x000021c0
2308
2309 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
2310 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
2311 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
2312 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
2313 {
2314 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
2315 }
2316 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
2317 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
2318 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
2319
2320 #define REG_A4XX_UNKNOWN_21C5 0x000021c5
2321
2322 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6
2323
2324 #define REG_A4XX_PC_GS_PARAM 0x000021e5
2325 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
2326 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
2327 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
2328 {
2329 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
2330 }
2331 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
2332 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
2333 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
2334 {
2335 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
2336 }
2337 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
2338 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
2339 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2340 {
2341 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
2342 }
2343 #define A4XX_PC_GS_PARAM_LAYER 0x80000000
2344
2345 #define REG_A4XX_PC_HS_PARAM 0x000021e7
2346 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
2347 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
2348 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
2349 {
2350 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
2351 }
2352 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
2353 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
2354 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
2355 {
2356 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
2357 }
2358 #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000
2359 #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23
2360 static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2361 {
2362 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
2363 }
2364
2365 #define REG_A4XX_VBIF_VERSION 0x00003000
2366
2367 #define REG_A4XX_VBIF_CLKON 0x00003001
2368 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
2369
2370 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
2371
2372 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
2373
2374 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2375
2376 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2377
2378 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2379
2380 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
2381
2382 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
2383
2384 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2385
2386 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
2387
2388 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
2389
2390 #define REG_A4XX_UNKNOWN_0D01 0x00000d01
2391
2392 #define REG_A4XX_UNKNOWN_0E05 0x00000e05
2393
2394 #define REG_A4XX_UNKNOWN_0E42 0x00000e42
2395
2396 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
2397
2398 #define REG_A4XX_UNKNOWN_0EC3 0x00000ec3
2399
2400 #define REG_A4XX_UNKNOWN_0F03 0x00000f03
2401
2402 #define REG_A4XX_UNKNOWN_2001 0x00002001
2403
2404 #define REG_A4XX_UNKNOWN_209B 0x0000209b
2405
2406 #define REG_A4XX_UNKNOWN_20EF 0x000020ef
2407
2408 #define REG_A4XX_UNKNOWN_20F0 0x000020f0
2409
2410 #define REG_A4XX_UNKNOWN_20F1 0x000020f1
2411
2412 #define REG_A4XX_UNKNOWN_20F2 0x000020f2
2413
2414 #define REG_A4XX_UNKNOWN_20F7 0x000020f7
2415 #define A4XX_UNKNOWN_20F7__MASK 0xffffffff
2416 #define A4XX_UNKNOWN_20F7__SHIFT 0
2417 static inline uint32_t A4XX_UNKNOWN_20F7(float val)
2418 {
2419 return ((fui(val)) << A4XX_UNKNOWN_20F7__SHIFT) & A4XX_UNKNOWN_20F7__MASK;
2420 }
2421
2422 #define REG_A4XX_UNKNOWN_2152 0x00002152
2423
2424 #define REG_A4XX_UNKNOWN_2153 0x00002153
2425
2426 #define REG_A4XX_UNKNOWN_2154 0x00002154
2427
2428 #define REG_A4XX_UNKNOWN_2155 0x00002155
2429
2430 #define REG_A4XX_UNKNOWN_2156 0x00002156
2431
2432 #define REG_A4XX_UNKNOWN_2157 0x00002157
2433
2434 #define REG_A4XX_UNKNOWN_21C3 0x000021c3
2435
2436 #define REG_A4XX_UNKNOWN_21E6 0x000021e6
2437
2438 #define REG_A4XX_UNKNOWN_2209 0x00002209
2439
2440 #define REG_A4XX_UNKNOWN_22D7 0x000022d7
2441
2442 #define REG_A4XX_TEX_SAMP_0 0x00000000
2443 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
2444 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
2445 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
2446 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
2447 {
2448 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
2449 }
2450 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
2451 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
2452 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
2453 {
2454 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
2455 }
2456 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
2457 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
2458 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
2459 {
2460 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
2461 }
2462 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
2463 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
2464 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
2465 {
2466 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
2467 }
2468 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
2469 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
2470 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
2471 {
2472 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
2473 }
2474 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
2475 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
2476 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
2477 {
2478 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
2479 }
2480
2481 #define REG_A4XX_TEX_SAMP_1 0x00000001
2482 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
2483 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
2484 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
2485 {
2486 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
2487 }
2488 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
2489 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
2490 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
2491 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
2492 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
2493 {
2494 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
2495 }
2496 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
2497 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
2498 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
2499 {
2500 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
2501 }
2502
2503 #define REG_A4XX_TEX_CONST_0 0x00000000
2504 #define A4XX_TEX_CONST_0_TILED 0x00000001
2505 #define A4XX_TEX_CONST_0_SRGB 0x00000004
2506 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2507 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2508 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
2509 {
2510 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
2511 }
2512 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2513 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2514 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
2515 {
2516 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
2517 }
2518 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2519 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2520 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
2521 {
2522 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
2523 }
2524 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2525 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2526 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
2527 {
2528 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
2529 }
2530 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2531 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2532 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
2533 {
2534 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
2535 }
2536 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2537 #define A4XX_TEX_CONST_0_FMT__SHIFT 22
2538 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
2539 {
2540 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
2541 }
2542 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
2543 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29
2544 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
2545 {
2546 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
2547 }
2548
2549 #define REG_A4XX_TEX_CONST_1 0x00000001
2550 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
2551 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
2552 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
2553 {
2554 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
2555 }
2556 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000
2557 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
2558 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
2559 {
2560 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
2561 }
2562
2563 #define REG_A4XX_TEX_CONST_2 0x00000002
2564 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
2565 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
2566 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
2567 {
2568 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
2569 }
2570 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
2571 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9
2572 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
2573 {
2574 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
2575 }
2576 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2577 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30
2578 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
2579 {
2580 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
2581 }
2582
2583 #define REG_A4XX_TEX_CONST_3 0x00000003
2584 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
2585 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
2586 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
2587 {
2588 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
2589 }
2590 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
2591 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
2592 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
2593 {
2594 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
2595 }
2596
2597 #define REG_A4XX_TEX_CONST_4 0x00000004
2598 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
2599 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
2600 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
2601 {
2602 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
2603 }
2604 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
2605 #define A4XX_TEX_CONST_4_BASE__SHIFT 5
2606 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
2607 {
2608 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
2609 }
2610
2611 #define REG_A4XX_TEX_CONST_5 0x00000005
2612
2613 #define REG_A4XX_TEX_CONST_6 0x00000006
2614
2615 #define REG_A4XX_TEX_CONST_7 0x00000007
2616
2617
2618 #endif /* A4XX_XML */