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freedreno/a4xx: add 16-bit unorm/snorm format texturing/rendering
[mesa.git] / src / gallium / drivers / freedreno / a4xx / a4xx.xml.h
1 #ifndef A4XX_XML
2 #define A4XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 68291 bytes, from 2015-11-17 16:39:59)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 64038 bytes, from 2015-11-17 16:37:36)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19
20 Copyright (C) 2013-2015 by the following authors:
21 - Rob Clark <robdclark@gmail.com> (robclark)
22
23 Permission is hereby granted, free of charge, to any person obtaining
24 a copy of this software and associated documentation files (the
25 "Software"), to deal in the Software without restriction, including
26 without limitation the rights to use, copy, modify, merge, publish,
27 distribute, sublicense, and/or sell copies of the Software, and to
28 permit persons to whom the Software is furnished to do so, subject to
29 the following conditions:
30
31 The above copyright notice and this permission notice (including the
32 next paragraph) shall be included in all copies or substantial
33 portions of the Software.
34
35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44
45 enum a4xx_color_fmt {
46 RB4_A8_UNORM = 1,
47 RB4_R8_UNORM = 2,
48 RB4_R4G4B4A4_UNORM = 8,
49 RB4_R5G5B5A1_UNORM = 10,
50 RB4_R5G6R5_UNORM = 14,
51 RB4_R8G8_UNORM = 15,
52 RB4_R8G8_SNORM = 16,
53 RB4_R8G8_UINT = 17,
54 RB4_R8G8_SINT = 18,
55 RB4_R16_UNORM = 19,
56 RB4_R16_SNORM = 20,
57 RB4_R16_FLOAT = 21,
58 RB4_R16_UINT = 22,
59 RB4_R16_SINT = 23,
60 RB4_R8G8B8_UNORM = 25,
61 RB4_R8G8B8A8_UNORM = 26,
62 RB4_R8G8B8A8_SNORM = 28,
63 RB4_R8G8B8A8_UINT = 29,
64 RB4_R8G8B8A8_SINT = 30,
65 RB4_R10G10B10A2_UNORM = 31,
66 RB4_R10G10B10A2_UINT = 34,
67 RB4_R11G11B10_FLOAT = 39,
68 RB4_R16G16_UNORM = 40,
69 RB4_R16G16_SNORM = 41,
70 RB4_R16G16_FLOAT = 42,
71 RB4_R16G16_UINT = 43,
72 RB4_R16G16_SINT = 44,
73 RB4_R32_FLOAT = 45,
74 RB4_R32_UINT = 46,
75 RB4_R32_SINT = 47,
76 RB4_R16G16B16A16_UNORM = 52,
77 RB4_R16G16B16A16_SNORM = 53,
78 RB4_R16G16B16A16_FLOAT = 54,
79 RB4_R16G16B16A16_UINT = 55,
80 RB4_R16G16B16A16_SINT = 56,
81 RB4_R32G32_FLOAT = 57,
82 RB4_R32G32_UINT = 58,
83 RB4_R32G32_SINT = 59,
84 RB4_R32G32B32A32_FLOAT = 60,
85 RB4_R32G32B32A32_UINT = 61,
86 RB4_R32G32B32A32_SINT = 62,
87 };
88
89 enum a4xx_tile_mode {
90 TILE4_LINEAR = 0,
91 TILE4_3 = 3,
92 };
93
94 enum a4xx_rb_blend_opcode {
95 BLEND_DST_PLUS_SRC = 0,
96 BLEND_SRC_MINUS_DST = 1,
97 BLEND_DST_MINUS_SRC = 2,
98 BLEND_MIN_DST_SRC = 3,
99 BLEND_MAX_DST_SRC = 4,
100 };
101
102 enum a4xx_vtx_fmt {
103 VFMT4_32_FLOAT = 1,
104 VFMT4_32_32_FLOAT = 2,
105 VFMT4_32_32_32_FLOAT = 3,
106 VFMT4_32_32_32_32_FLOAT = 4,
107 VFMT4_16_FLOAT = 5,
108 VFMT4_16_16_FLOAT = 6,
109 VFMT4_16_16_16_FLOAT = 7,
110 VFMT4_16_16_16_16_FLOAT = 8,
111 VFMT4_32_FIXED = 9,
112 VFMT4_32_32_FIXED = 10,
113 VFMT4_32_32_32_FIXED = 11,
114 VFMT4_32_32_32_32_FIXED = 12,
115 VFMT4_16_SINT = 16,
116 VFMT4_16_16_SINT = 17,
117 VFMT4_16_16_16_SINT = 18,
118 VFMT4_16_16_16_16_SINT = 19,
119 VFMT4_16_UINT = 20,
120 VFMT4_16_16_UINT = 21,
121 VFMT4_16_16_16_UINT = 22,
122 VFMT4_16_16_16_16_UINT = 23,
123 VFMT4_16_SNORM = 24,
124 VFMT4_16_16_SNORM = 25,
125 VFMT4_16_16_16_SNORM = 26,
126 VFMT4_16_16_16_16_SNORM = 27,
127 VFMT4_16_UNORM = 28,
128 VFMT4_16_16_UNORM = 29,
129 VFMT4_16_16_16_UNORM = 30,
130 VFMT4_16_16_16_16_UNORM = 31,
131 VFMT4_32_UINT = 32,
132 VFMT4_32_32_UINT = 33,
133 VFMT4_32_32_32_UINT = 34,
134 VFMT4_32_32_32_32_UINT = 35,
135 VFMT4_32_SINT = 36,
136 VFMT4_32_32_SINT = 37,
137 VFMT4_32_32_32_SINT = 38,
138 VFMT4_32_32_32_32_SINT = 39,
139 VFMT4_8_UINT = 40,
140 VFMT4_8_8_UINT = 41,
141 VFMT4_8_8_8_UINT = 42,
142 VFMT4_8_8_8_8_UINT = 43,
143 VFMT4_8_UNORM = 44,
144 VFMT4_8_8_UNORM = 45,
145 VFMT4_8_8_8_UNORM = 46,
146 VFMT4_8_8_8_8_UNORM = 47,
147 VFMT4_8_SINT = 48,
148 VFMT4_8_8_SINT = 49,
149 VFMT4_8_8_8_SINT = 50,
150 VFMT4_8_8_8_8_SINT = 51,
151 VFMT4_8_SNORM = 52,
152 VFMT4_8_8_SNORM = 53,
153 VFMT4_8_8_8_SNORM = 54,
154 VFMT4_8_8_8_8_SNORM = 55,
155 VFMT4_10_10_10_2_UINT = 60,
156 VFMT4_10_10_10_2_UNORM = 61,
157 VFMT4_10_10_10_2_SINT = 62,
158 VFMT4_10_10_10_2_SNORM = 63,
159 };
160
161 enum a4xx_tex_fmt {
162 TFMT4_5_6_5_UNORM = 11,
163 TFMT4_5_5_5_1_UNORM = 9,
164 TFMT4_4_4_4_4_UNORM = 8,
165 TFMT4_X8Z24_UNORM = 71,
166 TFMT4_10_10_10_2_UNORM = 33,
167 TFMT4_A8_UNORM = 3,
168 TFMT4_L8_A8_UNORM = 13,
169 TFMT4_8_UNORM = 4,
170 TFMT4_8_8_UNORM = 14,
171 TFMT4_8_8_8_8_UNORM = 28,
172 TFMT4_8_SNORM = 5,
173 TFMT4_8_8_SNORM = 15,
174 TFMT4_8_8_8_8_SNORM = 29,
175 TFMT4_8_UINT = 6,
176 TFMT4_8_8_UINT = 16,
177 TFMT4_8_8_8_8_UINT = 30,
178 TFMT4_8_SINT = 7,
179 TFMT4_8_8_SINT = 17,
180 TFMT4_8_8_8_8_SINT = 31,
181 TFMT4_16_UNORM = 18,
182 TFMT4_16_16_UNORM = 38,
183 TFMT4_16_16_16_16_UNORM = 51,
184 TFMT4_16_SNORM = 19,
185 TFMT4_16_16_SNORM = 39,
186 TFMT4_16_16_16_16_SNORM = 52,
187 TFMT4_16_UINT = 21,
188 TFMT4_16_16_UINT = 41,
189 TFMT4_16_16_16_16_UINT = 54,
190 TFMT4_16_SINT = 22,
191 TFMT4_16_16_SINT = 42,
192 TFMT4_16_16_16_16_SINT = 55,
193 TFMT4_32_UINT = 44,
194 TFMT4_32_32_UINT = 57,
195 TFMT4_32_32_32_32_UINT = 64,
196 TFMT4_32_SINT = 45,
197 TFMT4_32_32_SINT = 58,
198 TFMT4_32_32_32_32_SINT = 65,
199 TFMT4_16_FLOAT = 20,
200 TFMT4_16_16_FLOAT = 40,
201 TFMT4_16_16_16_16_FLOAT = 53,
202 TFMT4_32_FLOAT = 43,
203 TFMT4_32_32_FLOAT = 56,
204 TFMT4_32_32_32_32_FLOAT = 63,
205 TFMT4_9_9_9_E5_FLOAT = 32,
206 TFMT4_11_11_10_FLOAT = 37,
207 TFMT4_DXT1 = 86,
208 TFMT4_DXT3 = 87,
209 TFMT4_DXT5 = 88,
210 TFMT4_BPTC_UFLOAT = 97,
211 TFMT4_BPTC_FLOAT = 98,
212 TFMT4_BPTC = 99,
213 TFMT4_ATC_RGB = 100,
214 TFMT4_ATC_RGBA_EXPLICIT = 101,
215 TFMT4_ATC_RGBA_INTERPOLATED = 102,
216 TFMT4_ETC2_RG11_UNORM = 103,
217 TFMT4_ETC2_RG11_SNORM = 104,
218 TFMT4_ETC2_R11_UNORM = 105,
219 TFMT4_ETC2_R11_SNORM = 106,
220 TFMT4_ETC1 = 107,
221 TFMT4_ETC2_RGB8 = 108,
222 TFMT4_ETC2_RGBA8 = 109,
223 TFMT4_ETC2_RGB8A1 = 110,
224 TFMT4_ASTC_4x4 = 111,
225 TFMT4_ASTC_5x4 = 112,
226 TFMT4_ASTC_5x5 = 113,
227 TFMT4_ASTC_6x5 = 114,
228 TFMT4_ASTC_6x6 = 115,
229 TFMT4_ASTC_8x5 = 116,
230 TFMT4_ASTC_8x6 = 117,
231 TFMT4_ASTC_8x8 = 118,
232 TFMT4_ASTC_10x5 = 119,
233 TFMT4_ASTC_10x6 = 120,
234 TFMT4_ASTC_10x8 = 121,
235 TFMT4_ASTC_10x10 = 122,
236 TFMT4_ASTC_12x10 = 123,
237 TFMT4_ASTC_12x12 = 124,
238 };
239
240 enum a4xx_tex_fetchsize {
241 TFETCH4_1_BYTE = 0,
242 TFETCH4_2_BYTE = 1,
243 TFETCH4_4_BYTE = 2,
244 TFETCH4_8_BYTE = 3,
245 TFETCH4_16_BYTE = 4,
246 };
247
248 enum a4xx_depth_format {
249 DEPTH4_NONE = 0,
250 DEPTH4_16 = 1,
251 DEPTH4_24_8 = 2,
252 DEPTH4_32 = 3,
253 };
254
255 enum a4xx_tess_spacing {
256 EQUAL_SPACING = 0,
257 ODD_SPACING = 2,
258 EVEN_SPACING = 3,
259 };
260
261 enum a4xx_tex_filter {
262 A4XX_TEX_NEAREST = 0,
263 A4XX_TEX_LINEAR = 1,
264 A4XX_TEX_ANISO = 2,
265 };
266
267 enum a4xx_tex_clamp {
268 A4XX_TEX_REPEAT = 0,
269 A4XX_TEX_CLAMP_TO_EDGE = 1,
270 A4XX_TEX_MIRROR_REPEAT = 2,
271 A4XX_TEX_CLAMP_TO_BORDER = 3,
272 A4XX_TEX_MIRROR_CLAMP = 4,
273 };
274
275 enum a4xx_tex_aniso {
276 A4XX_TEX_ANISO_1 = 0,
277 A4XX_TEX_ANISO_2 = 1,
278 A4XX_TEX_ANISO_4 = 2,
279 A4XX_TEX_ANISO_8 = 3,
280 A4XX_TEX_ANISO_16 = 4,
281 };
282
283 enum a4xx_tex_swiz {
284 A4XX_TEX_X = 0,
285 A4XX_TEX_Y = 1,
286 A4XX_TEX_Z = 2,
287 A4XX_TEX_W = 3,
288 A4XX_TEX_ZERO = 4,
289 A4XX_TEX_ONE = 5,
290 };
291
292 enum a4xx_tex_type {
293 A4XX_TEX_1D = 0,
294 A4XX_TEX_2D = 1,
295 A4XX_TEX_CUBE = 2,
296 A4XX_TEX_3D = 3,
297 };
298
299 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
300 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
301 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
302 {
303 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
304 }
305 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
306 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
307 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
308 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
309 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
310 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
311 #define A4XX_INT0_VFD_ERROR 0x00000040
312 #define A4XX_INT0_CP_SW_INT 0x00000080
313 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
314 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
315 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
316 #define A4XX_INT0_CP_HW_FAULT 0x00000800
317 #define A4XX_INT0_CP_DMA 0x00001000
318 #define A4XX_INT0_CP_IB2_INT 0x00002000
319 #define A4XX_INT0_CP_IB1_INT 0x00004000
320 #define A4XX_INT0_CP_RB_INT 0x00008000
321 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
322 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000
323 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000
324 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000
325 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
326 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
327 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000
328 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
329 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
330
331 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
332
333 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
334
335 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
336
337 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
338
339 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
340
341 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
342
343 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
344
345 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
346
347 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
348
349 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
350 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
351 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
352 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
353 {
354 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
355 }
356 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
357 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
358 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
359 {
360 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
361 }
362
363 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
364
365 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
366
367 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
368
369 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
370
371 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0
372 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
373 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
374 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
375 {
376 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
377 }
378 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
379 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
380 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
381 {
382 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
383 }
384
385 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
386 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
387 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
388
389 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
390 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
391 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
392 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
393 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
394 {
395 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
396 }
397
398 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
399 #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
400 #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
401 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
402 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
403 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
404 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
405 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
406 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
407 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
408 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
409 {
410 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
411 }
412 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
413 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
414
415 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
416
417 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
418 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
419 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
420 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
421 #define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400
422 #define A4XX_RB_MRT_CONTROL_B11 0x00000800
423 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
424 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
425 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
426 {
427 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
428 }
429
430 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
431 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
432 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
433 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
434 {
435 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
436 }
437 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
438 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
439 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
440 {
441 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
442 }
443 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
444 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
445 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
446 {
447 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
448 }
449 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
450 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
451 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
452 {
453 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
454 }
455 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
456 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
457 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
458 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
459 {
460 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
461 }
462
463 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
464
465 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
466 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
467 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
468 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
469 {
470 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
471 }
472
473 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
474 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
475 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
476 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
477 {
478 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
479 }
480 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
481 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
482 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
483 {
484 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
485 }
486 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
487 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
488 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
489 {
490 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
491 }
492 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
493 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
494 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
495 {
496 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
497 }
498 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
499 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
500 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
501 {
502 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
503 }
504 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
505 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
506 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
507 {
508 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
509 }
510
511 #define REG_A4XX_RB_BLEND_RED 0x000020f0
512 #define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff
513 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0
514 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
515 {
516 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
517 }
518 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
519 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
520 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
521 {
522 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
523 }
524
525 #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
526 #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
527 #define A4XX_RB_BLEND_RED_F32__SHIFT 0
528 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
529 {
530 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
531 }
532
533 #define REG_A4XX_RB_BLEND_GREEN 0x000020f2
534 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff
535 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
536 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
537 {
538 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
539 }
540 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
541 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
542 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
543 {
544 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
545 }
546
547 #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
548 #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
549 #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
550 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
551 {
552 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
553 }
554
555 #define REG_A4XX_RB_BLEND_BLUE 0x000020f4
556 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff
557 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
558 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
559 {
560 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
561 }
562 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
563 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
564 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
565 {
566 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
567 }
568
569 #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
570 #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
571 #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
572 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
573 {
574 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
575 }
576
577 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
578 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff
579 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
580 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
581 {
582 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
583 }
584 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
585 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
586 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
587 {
588 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
589 }
590
591 #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
592 #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
593 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
594 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
595 {
596 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
597 }
598
599 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
600 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
601 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
602 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
603 {
604 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
605 }
606 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
607 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
608 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
609 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
610 {
611 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
612 }
613
614 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9
615 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
616 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
617 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
618 {
619 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
620 }
621 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100
622 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
623 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
624 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
625 {
626 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
627 }
628
629 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
630 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
631 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
632 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
633 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
634 {
635 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
636 }
637
638 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
639 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
640 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
641 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
642 {
643 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
644 }
645 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
646 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
647 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
648 {
649 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
650 }
651 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
652 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
653 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
654 {
655 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
656 }
657 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
658 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
659 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
660 {
661 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
662 }
663 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
664 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
665 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
666 {
667 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
668 }
669 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
670 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
671 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
672 {
673 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
674 }
675 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
676 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
677 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
678 {
679 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
680 }
681 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
682 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
683 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
684 {
685 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
686 }
687
688 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc
689 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
690 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
691 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
692 {
693 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
694 }
695 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
696 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
697 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
698 {
699 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
700 }
701 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
702 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
703 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
704 {
705 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
706 }
707 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
708 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
709 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
710 {
711 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
712 }
713
714 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
715 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
716 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
717 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
718 {
719 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
720 }
721
722 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
723 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
724 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
725 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
726 {
727 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
728 }
729
730 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
731 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
732 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
733 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
734 {
735 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
736 }
737 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
738 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
739 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
740 {
741 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
742 }
743 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
744 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
745 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
746 {
747 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
748 }
749 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
750 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
751 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
752 {
753 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
754 }
755 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
756 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
757 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
758 {
759 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
760 }
761 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
762 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
763 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
764 {
765 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
766 }
767
768 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
769 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
770 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
771 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
772 {
773 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
774 }
775 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
776
777 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
778 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
779 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
780 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
781 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
782 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
783 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
784 {
785 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
786 }
787 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
788 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
789 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
790
791 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
792
793 #define REG_A4XX_RB_DEPTH_INFO 0x00002103
794 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
795 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
796 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
797 {
798 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
799 }
800 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
801 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
802 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
803 {
804 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
805 }
806
807 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104
808 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
809 #define A4XX_RB_DEPTH_PITCH__SHIFT 0
810 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
811 {
812 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
813 }
814
815 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
816 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
817 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0
818 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
819 {
820 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
821 }
822
823 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
824 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
825 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
826 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
827 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
828 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
829 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
830 {
831 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
832 }
833 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
834 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
835 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
836 {
837 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
838 }
839 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
840 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
841 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
842 {
843 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
844 }
845 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
846 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
847 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
848 {
849 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
850 }
851 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
852 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
853 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
854 {
855 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
856 }
857 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
858 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
859 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
860 {
861 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
862 }
863 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
864 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
865 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
866 {
867 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
868 }
869 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
870 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
871 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
872 {
873 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
874 }
875
876 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
877 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
878
879 #define REG_A4XX_RB_STENCIL_INFO 0x00002108
880 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
881 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
882 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
883 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
884 {
885 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
886 }
887
888 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109
889 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
890 #define A4XX_RB_STENCIL_PITCH__SHIFT 0
891 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
892 {
893 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
894 }
895
896 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b
897 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
898 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
899 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
900 {
901 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
902 }
903 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
904 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
905 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
906 {
907 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
908 }
909 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
910 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
911 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
912 {
913 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
914 }
915
916 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
917 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
918 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
919 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
920 {
921 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
922 }
923 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
924 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
925 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
926 {
927 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
928 }
929 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
930 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
931 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
932 {
933 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
934 }
935
936 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d
937 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
938 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
939 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0
940 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
941 {
942 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
943 }
944 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
945 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
946 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
947 {
948 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
949 }
950
951 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
952
953 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
954
955 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
956
957 #define REG_A4XX_RBBM_HW_VERSION 0x00000000
958
959 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
960
961 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
962
963 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
964
965 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
966
967 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
968
969 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
970
971 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
972
973 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
974
975 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
976
977 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
978
979 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
980
981 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
982
983 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
984
985 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
986
987 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
988
989 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
990
991 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
992
993 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
994
995 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
996
997 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
998
999 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
1000
1001 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
1002
1003 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
1004
1005 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
1006
1007 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023
1008
1009 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024
1010
1011 #define REG_A4XX_RBBM_AHB_CMD 0x00000025
1012
1013 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
1014
1015 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
1016
1017 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
1018
1019 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
1020
1021 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
1022
1023 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
1024
1025 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037
1026
1027 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
1028
1029 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
1030
1031 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
1032
1033 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
1034
1035 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1036
1037 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
1038
1039 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
1040
1041 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1042
1043 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1044
1045 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1046
1047 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1048
1049 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1050
1051 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1052
1053 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1054
1055 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1056
1057 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1058
1059 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1060
1061 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1062
1063 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1064
1065 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1066
1067 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1068
1069 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1070
1071 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1072
1073 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1074
1075 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1076
1077 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1078
1079 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1080
1081 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1082
1083 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
1084
1085 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
1086
1087 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
1088
1089 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
1090
1091 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
1092
1093 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
1094
1095 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1096
1097 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1098
1099 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
1100
1101 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
1102
1103 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
1104
1105 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
1106
1107 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
1108
1109 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
1110
1111 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
1112
1113 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
1114
1115 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
1116
1117 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
1118
1119 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189
1120
1121 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
1122
1123 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
1124
1125 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
1126
1127 #define REG_A4XX_RBBM_STATUS 0x00000191
1128 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
1129 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1130 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1131 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
1132 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
1133 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
1134 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
1135 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
1136 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1137 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1138 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
1139 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
1140 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
1141 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
1142 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
1143 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
1144 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
1145 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
1146 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1147 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
1148 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
1149
1150 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
1151
1152 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
1153
1154 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
1155
1156 #define REG_A4XX_CP_RB_BASE 0x00000200
1157
1158 #define REG_A4XX_CP_RB_CNTL 0x00000201
1159
1160 #define REG_A4XX_CP_RB_WPTR 0x00000205
1161
1162 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
1163
1164 #define REG_A4XX_CP_RB_RPTR 0x00000204
1165
1166 #define REG_A4XX_CP_IB1_BASE 0x00000206
1167
1168 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207
1169
1170 #define REG_A4XX_CP_IB2_BASE 0x00000208
1171
1172 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209
1173
1174 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
1175
1176 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
1177
1178 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
1179
1180 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
1181
1182 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
1183
1184 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c
1185
1186 #define REG_A4XX_CP_ROQ_DATA 0x0000021d
1187
1188 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e
1189
1190 #define REG_A4XX_CP_MEQ_DATA 0x0000021f
1191
1192 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220
1193
1194 #define REG_A4XX_CP_MERCIU_DATA 0x00000221
1195
1196 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222
1197
1198 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
1199
1200 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
1201
1202 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
1203
1204 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
1205
1206 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227
1207
1208 #define REG_A4XX_CP_PREEMPT 0x0000022a
1209
1210 #define REG_A4XX_CP_CNTL 0x0000022c
1211
1212 #define REG_A4XX_CP_ME_CNTL 0x0000022d
1213
1214 #define REG_A4XX_CP_DEBUG 0x0000022e
1215
1216 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
1217
1218 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
1219
1220 #define REG_A4XX_CP_PROTECT_REG_0 0x00000240
1221
1222 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1223
1224 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1225
1226 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250
1227
1228 #define REG_A4XX_CP_ST_BASE 0x000004c0
1229
1230 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce
1231
1232 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0
1233
1234 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
1235
1236 #define REG_A4XX_CP_HW_FAULT 0x000004d8
1237
1238 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da
1239
1240 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
1241
1242 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
1243
1244 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
1245
1246 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1247
1248 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1249
1250 #define REG_A4XX_SP_VS_STATUS 0x00000ec0
1251
1252 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
1253
1254 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
1255
1256 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
1257 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
1258
1259 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
1260 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
1261 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
1262 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
1263
1264 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
1265 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1266 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1267 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1268 {
1269 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
1270 }
1271 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
1272 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1273 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1274 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1275 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1276 {
1277 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1278 }
1279 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1280 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1281 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1282 {
1283 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1284 }
1285 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1286 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1287 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1288 {
1289 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1290 }
1291 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1292 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
1293 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1294 {
1295 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
1296 }
1297 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1298 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1299
1300 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
1301 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1302 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1303 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1304 {
1305 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
1306 }
1307 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
1308 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
1309 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
1310 {
1311 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
1312 }
1313
1314 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
1315 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
1316 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
1317 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
1318 {
1319 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
1320 }
1321 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
1322 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
1323 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
1324 {
1325 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
1326 }
1327 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
1328 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
1329 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
1330 {
1331 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
1332 }
1333
1334 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1335
1336 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1337 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
1338 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
1339 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
1340 {
1341 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
1342 }
1343 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1344 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
1345 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
1346 {
1347 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
1348 }
1349 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
1350 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
1351 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
1352 {
1353 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
1354 }
1355 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1356 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
1357 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
1358 {
1359 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
1360 }
1361
1362 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1363
1364 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1365 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1366 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
1367 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
1368 {
1369 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
1370 }
1371 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1372 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
1373 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
1374 {
1375 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
1376 }
1377 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1378 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
1379 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
1380 {
1381 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
1382 }
1383 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1384 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
1385 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
1386 {
1387 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
1388 }
1389
1390 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
1391 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1392 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1393 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1394 {
1395 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1396 }
1397 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1398 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1399 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1400 {
1401 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1402 }
1403
1404 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1
1405
1406 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
1407
1408 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
1409
1410 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
1411
1412 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
1413 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
1414 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
1415 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1416 {
1417 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
1418 }
1419 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
1420 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
1421 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1422 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1423 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1424 {
1425 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1426 }
1427 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1428 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1429 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1430 {
1431 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1432 }
1433 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1434 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1435 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1436 {
1437 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1438 }
1439 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1440 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
1441 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1442 {
1443 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
1444 }
1445 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1446 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1447
1448 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
1449 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1450 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1451 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1452 {
1453 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
1454 }
1455 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
1456 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
1457 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
1458
1459 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
1460 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1461 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1462 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1463 {
1464 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1465 }
1466 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1467 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1468 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1469 {
1470 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1471 }
1472
1473 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb
1474
1475 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
1476
1477 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
1478
1479 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
1480
1481 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
1482 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1483 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
1484 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
1485 {
1486 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
1487 }
1488 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
1489 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
1490 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
1491 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
1492 {
1493 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
1494 }
1495 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
1496 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
1497 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
1498 {
1499 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
1500 }
1501
1502 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1503
1504 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1505 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
1506 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
1507 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
1508 {
1509 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
1510 }
1511 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
1512 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
1513 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
1514 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
1515 {
1516 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
1517 }
1518 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
1519
1520 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
1521
1522 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
1523
1524 #define REG_A4XX_SP_CS_OBJ_START 0x00002302
1525
1526 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
1527
1528 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
1529
1530 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
1531
1532 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
1533
1534 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
1535 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1536 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1537 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1538 {
1539 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1540 }
1541 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1542 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1543 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1544 {
1545 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1546 }
1547
1548 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e
1549
1550 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
1551
1552 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
1553
1554 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
1555
1556 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
1557 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
1558 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
1559 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
1560 {
1561 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
1562 }
1563 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1564 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1565 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1566 {
1567 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
1568 }
1569
1570 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1571
1572 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1573 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
1574 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
1575 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
1576 {
1577 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
1578 }
1579 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1580 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
1581 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
1582 {
1583 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
1584 }
1585 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
1586 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
1587 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
1588 {
1589 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
1590 }
1591 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1592 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
1593 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
1594 {
1595 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
1596 }
1597
1598 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1599
1600 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1601 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1602 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
1603 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
1604 {
1605 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
1606 }
1607 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1608 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
1609 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
1610 {
1611 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
1612 }
1613 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1614 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
1615 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
1616 {
1617 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
1618 }
1619 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1620 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
1621 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
1622 {
1623 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
1624 }
1625
1626 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
1627 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1628 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1629 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1630 {
1631 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1632 }
1633 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1634 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1635 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1636 {
1637 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1638 }
1639
1640 #define REG_A4XX_SP_DS_OBJ_START 0x00002335
1641
1642 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
1643
1644 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
1645
1646 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
1647
1648 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341
1649 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
1650 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
1651 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
1652 {
1653 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
1654 }
1655 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
1656 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
1657 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
1658 {
1659 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
1660 }
1661 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1662 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1663 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1664 {
1665 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
1666 }
1667
1668 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1669
1670 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1671 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
1672 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
1673 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
1674 {
1675 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
1676 }
1677 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1678 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
1679 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
1680 {
1681 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
1682 }
1683 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
1684 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
1685 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
1686 {
1687 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
1688 }
1689 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1690 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
1691 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
1692 {
1693 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
1694 }
1695
1696 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1697
1698 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1699 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1700 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
1701 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
1702 {
1703 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
1704 }
1705 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1706 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
1707 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
1708 {
1709 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
1710 }
1711 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1712 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
1713 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
1714 {
1715 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
1716 }
1717 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1718 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
1719 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
1720 {
1721 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
1722 }
1723
1724 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
1725 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1726 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1727 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1728 {
1729 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1730 }
1731 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1732 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1733 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1734 {
1735 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1736 }
1737
1738 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c
1739
1740 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
1741
1742 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
1743
1744 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
1745
1746 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
1747
1748 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
1749
1750 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
1751
1752 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
1753
1754 #define REG_A4XX_VPC_ATTR 0x00002140
1755 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1756 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
1757 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
1758 {
1759 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
1760 }
1761 #define A4XX_VPC_ATTR_PSIZE 0x00000200
1762 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
1763 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1764 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
1765 {
1766 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
1767 }
1768 #define A4XX_VPC_ATTR_ENABLE 0x02000000
1769
1770 #define REG_A4XX_VPC_PACK 0x00002141
1771 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
1772 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
1773 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
1774 {
1775 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
1776 }
1777 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1778 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1779 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
1780 {
1781 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
1782 }
1783 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1784 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1785 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
1786 {
1787 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
1788 }
1789
1790 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1791
1792 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1793
1794 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1795
1796 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1797
1798 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
1799
1800 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00
1801 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1802 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1803 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1804 {
1805 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
1806 }
1807 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1808 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1809 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1810 {
1811 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
1812 }
1813
1814 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
1815
1816 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
1817
1818 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
1819
1820 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1821
1822 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1823 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1824 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1825 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1826 {
1827 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
1828 }
1829 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1830 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1831 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1832 {
1833 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1834 }
1835 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1836 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1837 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1838 {
1839 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
1840 }
1841 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1842 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
1843 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1844 {
1845 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
1846 }
1847
1848 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1849
1850 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1851
1852 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1853
1854 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1855
1856 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
1857
1858 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
1859
1860 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
1861
1862 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
1863
1864 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
1865
1866 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
1867
1868 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
1869
1870 #define REG_A4XX_VFD_CONTROL_0 0x00002200
1871 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
1872 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1873 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1874 {
1875 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1876 }
1877 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
1878 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
1879 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
1880 {
1881 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
1882 }
1883 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
1884 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
1885 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1886 {
1887 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1888 }
1889 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
1890 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
1891 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1892 {
1893 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1894 }
1895
1896 #define REG_A4XX_VFD_CONTROL_1 0x00002201
1897 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1898 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1899 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1900 {
1901 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1902 }
1903 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1904 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1905 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1906 {
1907 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
1908 }
1909 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1910 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1911 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1912 {
1913 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
1914 }
1915
1916 #define REG_A4XX_VFD_CONTROL_2 0x00002202
1917
1918 #define REG_A4XX_VFD_CONTROL_3 0x00002203
1919 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
1920 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
1921 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
1922 {
1923 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
1924 }
1925 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
1926 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
1927 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
1928 {
1929 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
1930 }
1931 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
1932 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
1933 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
1934 {
1935 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
1936 }
1937
1938 #define REG_A4XX_VFD_CONTROL_4 0x00002204
1939
1940 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
1941
1942 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1943
1944 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1945 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1946 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1947 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1948 {
1949 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1950 }
1951 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
1952 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1953 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1954 {
1955 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1956 }
1957 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
1958 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
1959
1960 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
1961
1962 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
1963 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
1964 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
1965 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
1966 {
1967 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
1968 }
1969
1970 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
1971 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
1972 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
1973 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
1974 {
1975 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
1976 }
1977
1978 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1979
1980 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1981 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1982 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1983 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1984 {
1985 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
1986 }
1987 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
1988 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
1989 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
1990 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
1991 {
1992 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
1993 }
1994 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
1995 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
1996 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
1997 {
1998 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
1999 }
2000 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000
2001 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
2002 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
2003 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
2004 {
2005 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
2006 }
2007 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
2008 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
2009 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
2010 {
2011 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
2012 }
2013 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
2014 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
2015
2016 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
2017
2018 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
2019
2020 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
2021
2022 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
2023
2024 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
2025 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
2026 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
2027 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
2028 {
2029 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
2030 }
2031 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
2032 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
2033 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
2034 {
2035 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
2036 }
2037 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
2038 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
2039 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
2040 {
2041 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
2042 }
2043 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
2044 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
2045 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
2046 {
2047 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
2048 }
2049
2050 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
2051
2052 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
2053
2054 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
2055
2056 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
2057
2058 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
2059
2060 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
2061
2062 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
2063
2064 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
2065
2066 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
2067
2068 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
2069
2070 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
2071
2072 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
2073
2074 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
2075
2076 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
2077 #define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
2078 #define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
2079
2080 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
2081 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
2082
2083 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
2084 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
2085 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
2086 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
2087 {
2088 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
2089 }
2090 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
2091 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
2092 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
2093 {
2094 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
2095 }
2096
2097 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
2098 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2099 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2100 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2101 {
2102 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2103 }
2104
2105 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
2106 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2107 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2108 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
2109 {
2110 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2111 }
2112
2113 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
2114 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2115 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2116 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2117 {
2118 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2119 }
2120
2121 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
2122 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2123 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2124 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
2125 {
2126 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2127 }
2128
2129 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
2130 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2131 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2132 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2133 {
2134 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2135 }
2136
2137 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
2138 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2139 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2140 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2141 {
2142 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2143 }
2144
2145 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
2146 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2147 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2148 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2149 {
2150 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2151 }
2152 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2153 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2154 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2155 {
2156 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2157 }
2158
2159 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
2160 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2161 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
2162 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
2163 {
2164 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
2165 }
2166
2167 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
2168 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
2169
2170 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
2171 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2172 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2173 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2174 {
2175 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2176 }
2177
2178 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
2179 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2180 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2181 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2182 {
2183 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2184 }
2185
2186 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
2187 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
2188 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
2189 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
2190 {
2191 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
2192 }
2193
2194 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
2195 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
2196 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
2197 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
2198 {
2199 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
2200 }
2201
2202 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
2203 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
2204 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
2205 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
2206 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
2207 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
2208 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
2209 {
2210 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
2211 }
2212 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
2213 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
2214
2215 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
2216 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
2217 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
2218 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
2219 {
2220 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
2221 }
2222 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
2223 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
2224 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
2225 {
2226 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
2227 }
2228 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
2229 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
2230 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
2231 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
2232 {
2233 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
2234 }
2235
2236 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
2237 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2238 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
2239 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
2240 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
2241 {
2242 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
2243 }
2244 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
2245 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
2246 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
2247 {
2248 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
2249 }
2250
2251 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
2252 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2253 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
2254 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
2255 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
2256 {
2257 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
2258 }
2259 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
2260 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
2261 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
2262 {
2263 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
2264 }
2265
2266 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
2267 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2268 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2269 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2270 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2271 {
2272 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2273 }
2274 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2275 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2276 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2277 {
2278 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2279 }
2280
2281 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
2282 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2283 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2284 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2285 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2286 {
2287 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2288 }
2289 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2290 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2291 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2292 {
2293 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2294 }
2295
2296 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
2297 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
2298 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
2299 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
2300 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
2301 {
2302 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
2303 }
2304 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
2305 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
2306 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
2307 {
2308 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
2309 }
2310
2311 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
2312 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
2313 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
2314 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
2315 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
2316 {
2317 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
2318 }
2319 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
2320 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
2321 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
2322 {
2323 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
2324 }
2325
2326 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
2327
2328 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
2329
2330 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
2331
2332 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
2333
2334 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
2335
2336 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
2337
2338 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
2339
2340 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
2341
2342 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
2343
2344 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
2345
2346 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
2347
2348 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
2349
2350 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
2351 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
2352 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
2353 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
2354 {
2355 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
2356 }
2357 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
2358 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
2359 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
2360 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
2361 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
2362 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
2363 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
2364 {
2365 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
2366 }
2367 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
2368 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
2369 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
2370 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
2371
2372 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
2373 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
2374 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
2375 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
2376 {
2377 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
2378 }
2379 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
2380 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
2381 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
2382 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
2383 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
2384 {
2385 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
2386 }
2387 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
2388 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
2389 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
2390 {
2391 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
2392 }
2393
2394 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
2395 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
2396 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
2397 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
2398 {
2399 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
2400 }
2401 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
2402 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
2403 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
2404 {
2405 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
2406 }
2407 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
2408 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
2409 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
2410 {
2411 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
2412 }
2413 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
2414 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
2415 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
2416 {
2417 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
2418 }
2419
2420 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
2421 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
2422 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
2423 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
2424 {
2425 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
2426 }
2427
2428 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
2429
2430 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
2431 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2432 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2433 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2434 {
2435 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
2436 }
2437 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2438 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2439 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2440 {
2441 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2442 }
2443 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
2444 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2445 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2446 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2447 {
2448 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2449 }
2450 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2451 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2452 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2453 {
2454 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
2455 }
2456
2457 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
2458 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2459 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2460 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2461 {
2462 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
2463 }
2464 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2465 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2466 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2467 {
2468 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2469 }
2470 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
2471 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2472 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2473 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2474 {
2475 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2476 }
2477 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2478 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2479 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2480 {
2481 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
2482 }
2483
2484 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
2485 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2486 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2487 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2488 {
2489 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
2490 }
2491 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2492 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2493 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2494 {
2495 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2496 }
2497 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
2498 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2499 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2500 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2501 {
2502 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2503 }
2504 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2505 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2506 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2507 {
2508 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
2509 }
2510
2511 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
2512 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2513 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2514 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2515 {
2516 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
2517 }
2518 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2519 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2520 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2521 {
2522 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2523 }
2524 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
2525 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2526 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2527 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2528 {
2529 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2530 }
2531 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2532 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2533 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2534 {
2535 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
2536 }
2537
2538 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
2539 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2540 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2541 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2542 {
2543 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
2544 }
2545 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2546 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2547 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2548 {
2549 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2550 }
2551 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
2552 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2553 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2554 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2555 {
2556 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2557 }
2558 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2559 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2560 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2561 {
2562 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
2563 }
2564
2565 #define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca
2566
2567 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
2568
2569 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
2570
2571 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
2572
2573 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
2574
2575 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
2576
2577 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
2578
2579 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
2580
2581 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
2582
2583 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
2584
2585 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
2586
2587 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
2588
2589 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
2590
2591 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
2592
2593 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
2594
2595 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
2596
2597 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
2598 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
2599
2600 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
2601
2602 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2603
2604 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2605
2606 #define REG_A4XX_PC_BIN_BASE 0x000021c0
2607
2608 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
2609 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
2610 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
2611 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
2612 {
2613 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
2614 }
2615 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
2616 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
2617 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
2618
2619 #define REG_A4XX_UNKNOWN_21C5 0x000021c5
2620
2621 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6
2622
2623 #define REG_A4XX_PC_GS_PARAM 0x000021e5
2624 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
2625 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
2626 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
2627 {
2628 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
2629 }
2630 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
2631 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
2632 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
2633 {
2634 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
2635 }
2636 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
2637 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
2638 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2639 {
2640 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
2641 }
2642 #define A4XX_PC_GS_PARAM_LAYER 0x80000000
2643
2644 #define REG_A4XX_PC_HS_PARAM 0x000021e7
2645 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
2646 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
2647 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
2648 {
2649 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
2650 }
2651 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
2652 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
2653 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
2654 {
2655 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
2656 }
2657 #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000
2658 #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23
2659 static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2660 {
2661 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
2662 }
2663
2664 #define REG_A4XX_VBIF_VERSION 0x00003000
2665
2666 #define REG_A4XX_VBIF_CLKON 0x00003001
2667 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
2668
2669 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
2670
2671 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
2672
2673 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2674
2675 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2676
2677 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2678
2679 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
2680
2681 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
2682
2683 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2684
2685 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
2686
2687 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
2688
2689 #define REG_A4XX_UNKNOWN_0D01 0x00000d01
2690
2691 #define REG_A4XX_UNKNOWN_0E42 0x00000e42
2692
2693 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
2694
2695 #define REG_A4XX_UNKNOWN_2001 0x00002001
2696
2697 #define REG_A4XX_UNKNOWN_209B 0x0000209b
2698
2699 #define REG_A4XX_UNKNOWN_20EF 0x000020ef
2700
2701 #define REG_A4XX_UNKNOWN_2152 0x00002152
2702
2703 #define REG_A4XX_UNKNOWN_2153 0x00002153
2704
2705 #define REG_A4XX_UNKNOWN_2154 0x00002154
2706
2707 #define REG_A4XX_UNKNOWN_2155 0x00002155
2708
2709 #define REG_A4XX_UNKNOWN_2156 0x00002156
2710
2711 #define REG_A4XX_UNKNOWN_2157 0x00002157
2712
2713 #define REG_A4XX_UNKNOWN_21C3 0x000021c3
2714
2715 #define REG_A4XX_UNKNOWN_21E6 0x000021e6
2716
2717 #define REG_A4XX_UNKNOWN_2209 0x00002209
2718
2719 #define REG_A4XX_UNKNOWN_22D7 0x000022d7
2720
2721 #define REG_A4XX_UNKNOWN_2352 0x00002352
2722
2723 #define REG_A4XX_TEX_SAMP_0 0x00000000
2724 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
2725 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
2726 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
2727 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
2728 {
2729 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
2730 }
2731 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
2732 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
2733 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
2734 {
2735 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
2736 }
2737 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
2738 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
2739 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
2740 {
2741 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
2742 }
2743 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
2744 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
2745 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
2746 {
2747 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
2748 }
2749 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
2750 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
2751 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
2752 {
2753 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
2754 }
2755 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
2756 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
2757 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
2758 {
2759 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
2760 }
2761 #define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
2762 #define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
2763 static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
2764 {
2765 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
2766 }
2767
2768 #define REG_A4XX_TEX_SAMP_1 0x00000001
2769 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
2770 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
2771 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
2772 {
2773 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
2774 }
2775 #define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
2776 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
2777 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
2778 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
2779 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
2780 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
2781 {
2782 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
2783 }
2784 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
2785 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
2786 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
2787 {
2788 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
2789 }
2790
2791 #define REG_A4XX_TEX_CONST_0 0x00000000
2792 #define A4XX_TEX_CONST_0_TILED 0x00000001
2793 #define A4XX_TEX_CONST_0_SRGB 0x00000004
2794 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2795 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2796 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
2797 {
2798 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
2799 }
2800 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2801 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2802 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
2803 {
2804 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
2805 }
2806 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2807 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2808 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
2809 {
2810 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
2811 }
2812 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2813 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2814 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
2815 {
2816 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
2817 }
2818 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2819 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2820 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
2821 {
2822 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
2823 }
2824 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2825 #define A4XX_TEX_CONST_0_FMT__SHIFT 22
2826 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
2827 {
2828 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
2829 }
2830 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
2831 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29
2832 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
2833 {
2834 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
2835 }
2836
2837 #define REG_A4XX_TEX_CONST_1 0x00000001
2838 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
2839 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
2840 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
2841 {
2842 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
2843 }
2844 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000
2845 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
2846 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
2847 {
2848 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
2849 }
2850
2851 #define REG_A4XX_TEX_CONST_2 0x00000002
2852 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
2853 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
2854 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
2855 {
2856 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
2857 }
2858 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
2859 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9
2860 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
2861 {
2862 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
2863 }
2864 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2865 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30
2866 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
2867 {
2868 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
2869 }
2870
2871 #define REG_A4XX_TEX_CONST_3 0x00000003
2872 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
2873 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
2874 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
2875 {
2876 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
2877 }
2878 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
2879 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
2880 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
2881 {
2882 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
2883 }
2884
2885 #define REG_A4XX_TEX_CONST_4 0x00000004
2886 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
2887 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
2888 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
2889 {
2890 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
2891 }
2892 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
2893 #define A4XX_TEX_CONST_4_BASE__SHIFT 5
2894 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
2895 {
2896 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
2897 }
2898
2899 #define REG_A4XX_TEX_CONST_5 0x00000005
2900
2901 #define REG_A4XX_TEX_CONST_6 0x00000006
2902
2903 #define REG_A4XX_TEX_CONST_7 0x00000007
2904
2905
2906 #endif /* A4XX_XML */