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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a4xx / a4xx.xml.h
1 #ifndef A4XX_XML
2 #define A4XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 68291 bytes, from 2015-11-17 16:39:59)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 64038 bytes, from 2015-11-17 16:37:36)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
19
20 Copyright (C) 2013-2015 by the following authors:
21 - Rob Clark <robdclark@gmail.com> (robclark)
22
23 Permission is hereby granted, free of charge, to any person obtaining
24 a copy of this software and associated documentation files (the
25 "Software"), to deal in the Software without restriction, including
26 without limitation the rights to use, copy, modify, merge, publish,
27 distribute, sublicense, and/or sell copies of the Software, and to
28 permit persons to whom the Software is furnished to do so, subject to
29 the following conditions:
30
31 The above copyright notice and this permission notice (including the
32 next paragraph) shall be included in all copies or substantial
33 portions of the Software.
34
35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44
45 enum a4xx_color_fmt {
46 RB4_A8_UNORM = 1,
47 RB4_R8_UNORM = 2,
48 RB4_R4G4B4A4_UNORM = 8,
49 RB4_R5G5B5A1_UNORM = 10,
50 RB4_R5G6R5_UNORM = 14,
51 RB4_R8G8_UNORM = 15,
52 RB4_R8G8_SNORM = 16,
53 RB4_R8G8_UINT = 17,
54 RB4_R8G8_SINT = 18,
55 RB4_R16_FLOAT = 21,
56 RB4_R16_UINT = 22,
57 RB4_R16_SINT = 23,
58 RB4_R8G8B8_UNORM = 25,
59 RB4_R8G8B8A8_UNORM = 26,
60 RB4_R8G8B8A8_SNORM = 28,
61 RB4_R8G8B8A8_UINT = 29,
62 RB4_R8G8B8A8_SINT = 30,
63 RB4_R10G10B10A2_UNORM = 31,
64 RB4_R10G10B10A2_UINT = 34,
65 RB4_R11G11B10_FLOAT = 39,
66 RB4_R16G16_FLOAT = 42,
67 RB4_R16G16_UINT = 43,
68 RB4_R16G16_SINT = 44,
69 RB4_R32_FLOAT = 45,
70 RB4_R32_UINT = 46,
71 RB4_R32_SINT = 47,
72 RB4_R16G16B16A16_FLOAT = 54,
73 RB4_R16G16B16A16_UINT = 55,
74 RB4_R16G16B16A16_SINT = 56,
75 RB4_R32G32_FLOAT = 57,
76 RB4_R32G32_UINT = 58,
77 RB4_R32G32_SINT = 59,
78 RB4_R32G32B32A32_FLOAT = 60,
79 RB4_R32G32B32A32_UINT = 61,
80 RB4_R32G32B32A32_SINT = 62,
81 };
82
83 enum a4xx_tile_mode {
84 TILE4_LINEAR = 0,
85 TILE4_3 = 3,
86 };
87
88 enum a4xx_rb_blend_opcode {
89 BLEND_DST_PLUS_SRC = 0,
90 BLEND_SRC_MINUS_DST = 1,
91 BLEND_DST_MINUS_SRC = 2,
92 BLEND_MIN_DST_SRC = 3,
93 BLEND_MAX_DST_SRC = 4,
94 };
95
96 enum a4xx_vtx_fmt {
97 VFMT4_32_FLOAT = 1,
98 VFMT4_32_32_FLOAT = 2,
99 VFMT4_32_32_32_FLOAT = 3,
100 VFMT4_32_32_32_32_FLOAT = 4,
101 VFMT4_16_FLOAT = 5,
102 VFMT4_16_16_FLOAT = 6,
103 VFMT4_16_16_16_FLOAT = 7,
104 VFMT4_16_16_16_16_FLOAT = 8,
105 VFMT4_32_FIXED = 9,
106 VFMT4_32_32_FIXED = 10,
107 VFMT4_32_32_32_FIXED = 11,
108 VFMT4_32_32_32_32_FIXED = 12,
109 VFMT4_16_SINT = 16,
110 VFMT4_16_16_SINT = 17,
111 VFMT4_16_16_16_SINT = 18,
112 VFMT4_16_16_16_16_SINT = 19,
113 VFMT4_16_UINT = 20,
114 VFMT4_16_16_UINT = 21,
115 VFMT4_16_16_16_UINT = 22,
116 VFMT4_16_16_16_16_UINT = 23,
117 VFMT4_16_SNORM = 24,
118 VFMT4_16_16_SNORM = 25,
119 VFMT4_16_16_16_SNORM = 26,
120 VFMT4_16_16_16_16_SNORM = 27,
121 VFMT4_16_UNORM = 28,
122 VFMT4_16_16_UNORM = 29,
123 VFMT4_16_16_16_UNORM = 30,
124 VFMT4_16_16_16_16_UNORM = 31,
125 VFMT4_32_UINT = 32,
126 VFMT4_32_32_UINT = 33,
127 VFMT4_32_32_32_UINT = 34,
128 VFMT4_32_32_32_32_UINT = 35,
129 VFMT4_32_SINT = 36,
130 VFMT4_32_32_SINT = 37,
131 VFMT4_32_32_32_SINT = 38,
132 VFMT4_32_32_32_32_SINT = 39,
133 VFMT4_8_UINT = 40,
134 VFMT4_8_8_UINT = 41,
135 VFMT4_8_8_8_UINT = 42,
136 VFMT4_8_8_8_8_UINT = 43,
137 VFMT4_8_UNORM = 44,
138 VFMT4_8_8_UNORM = 45,
139 VFMT4_8_8_8_UNORM = 46,
140 VFMT4_8_8_8_8_UNORM = 47,
141 VFMT4_8_SINT = 48,
142 VFMT4_8_8_SINT = 49,
143 VFMT4_8_8_8_SINT = 50,
144 VFMT4_8_8_8_8_SINT = 51,
145 VFMT4_8_SNORM = 52,
146 VFMT4_8_8_SNORM = 53,
147 VFMT4_8_8_8_SNORM = 54,
148 VFMT4_8_8_8_8_SNORM = 55,
149 VFMT4_10_10_10_2_UINT = 60,
150 VFMT4_10_10_10_2_UNORM = 61,
151 VFMT4_10_10_10_2_SINT = 62,
152 VFMT4_10_10_10_2_SNORM = 63,
153 };
154
155 enum a4xx_tex_fmt {
156 TFMT4_5_6_5_UNORM = 11,
157 TFMT4_5_5_5_1_UNORM = 10,
158 TFMT4_4_4_4_4_UNORM = 8,
159 TFMT4_X8Z24_UNORM = 71,
160 TFMT4_10_10_10_2_UNORM = 33,
161 TFMT4_A8_UNORM = 3,
162 TFMT4_L8_A8_UNORM = 13,
163 TFMT4_8_UNORM = 4,
164 TFMT4_8_8_UNORM = 14,
165 TFMT4_8_8_8_8_UNORM = 28,
166 TFMT4_8_SNORM = 5,
167 TFMT4_8_8_SNORM = 15,
168 TFMT4_8_8_8_8_SNORM = 29,
169 TFMT4_8_UINT = 6,
170 TFMT4_8_8_UINT = 16,
171 TFMT4_8_8_8_8_UINT = 30,
172 TFMT4_8_SINT = 7,
173 TFMT4_8_8_SINT = 17,
174 TFMT4_8_8_8_8_SINT = 31,
175 TFMT4_16_UINT = 21,
176 TFMT4_16_16_UINT = 41,
177 TFMT4_16_16_16_16_UINT = 54,
178 TFMT4_16_SINT = 22,
179 TFMT4_16_16_SINT = 42,
180 TFMT4_16_16_16_16_SINT = 55,
181 TFMT4_32_UINT = 44,
182 TFMT4_32_32_UINT = 57,
183 TFMT4_32_32_32_32_UINT = 64,
184 TFMT4_32_SINT = 45,
185 TFMT4_32_32_SINT = 58,
186 TFMT4_32_32_32_32_SINT = 65,
187 TFMT4_16_FLOAT = 20,
188 TFMT4_16_16_FLOAT = 40,
189 TFMT4_16_16_16_16_FLOAT = 53,
190 TFMT4_32_FLOAT = 43,
191 TFMT4_32_32_FLOAT = 56,
192 TFMT4_32_32_32_32_FLOAT = 63,
193 TFMT4_9_9_9_E5_FLOAT = 32,
194 TFMT4_11_11_10_FLOAT = 37,
195 TFMT4_DXT1 = 86,
196 TFMT4_DXT3 = 87,
197 TFMT4_DXT5 = 88,
198 TFMT4_ATC_RGB = 100,
199 TFMT4_ATC_RGBA_EXPLICIT = 101,
200 TFMT4_ATC_RGBA_INTERPOLATED = 102,
201 TFMT4_ETC2_RG11_UNORM = 103,
202 TFMT4_ETC2_RG11_SNORM = 104,
203 TFMT4_ETC2_R11_UNORM = 105,
204 TFMT4_ETC2_R11_SNORM = 106,
205 TFMT4_ETC1 = 107,
206 TFMT4_ETC2_RGB8 = 108,
207 TFMT4_ETC2_RGBA8 = 109,
208 TFMT4_ETC2_RGB8A1 = 110,
209 TFMT4_ASTC_4x4 = 111,
210 TFMT4_ASTC_5x4 = 112,
211 TFMT4_ASTC_5x5 = 113,
212 TFMT4_ASTC_6x5 = 114,
213 TFMT4_ASTC_6x6 = 115,
214 TFMT4_ASTC_8x5 = 116,
215 TFMT4_ASTC_8x6 = 117,
216 TFMT4_ASTC_8x8 = 118,
217 TFMT4_ASTC_10x5 = 119,
218 TFMT4_ASTC_10x6 = 120,
219 TFMT4_ASTC_10x8 = 121,
220 TFMT4_ASTC_10x10 = 122,
221 TFMT4_ASTC_12x10 = 123,
222 TFMT4_ASTC_12x12 = 124,
223 };
224
225 enum a4xx_tex_fetchsize {
226 TFETCH4_1_BYTE = 0,
227 TFETCH4_2_BYTE = 1,
228 TFETCH4_4_BYTE = 2,
229 TFETCH4_8_BYTE = 3,
230 TFETCH4_16_BYTE = 4,
231 };
232
233 enum a4xx_depth_format {
234 DEPTH4_NONE = 0,
235 DEPTH4_16 = 1,
236 DEPTH4_24_8 = 2,
237 DEPTH4_32 = 3,
238 };
239
240 enum a4xx_tess_spacing {
241 EQUAL_SPACING = 0,
242 ODD_SPACING = 2,
243 EVEN_SPACING = 3,
244 };
245
246 enum a4xx_tex_filter {
247 A4XX_TEX_NEAREST = 0,
248 A4XX_TEX_LINEAR = 1,
249 A4XX_TEX_ANISO = 2,
250 };
251
252 enum a4xx_tex_clamp {
253 A4XX_TEX_REPEAT = 0,
254 A4XX_TEX_CLAMP_TO_EDGE = 1,
255 A4XX_TEX_MIRROR_REPEAT = 2,
256 A4XX_TEX_CLAMP_TO_BORDER = 3,
257 A4XX_TEX_MIRROR_CLAMP = 4,
258 };
259
260 enum a4xx_tex_aniso {
261 A4XX_TEX_ANISO_1 = 0,
262 A4XX_TEX_ANISO_2 = 1,
263 A4XX_TEX_ANISO_4 = 2,
264 A4XX_TEX_ANISO_8 = 3,
265 A4XX_TEX_ANISO_16 = 4,
266 };
267
268 enum a4xx_tex_swiz {
269 A4XX_TEX_X = 0,
270 A4XX_TEX_Y = 1,
271 A4XX_TEX_Z = 2,
272 A4XX_TEX_W = 3,
273 A4XX_TEX_ZERO = 4,
274 A4XX_TEX_ONE = 5,
275 };
276
277 enum a4xx_tex_type {
278 A4XX_TEX_1D = 0,
279 A4XX_TEX_2D = 1,
280 A4XX_TEX_CUBE = 2,
281 A4XX_TEX_3D = 3,
282 };
283
284 #define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
285 #define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
286 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
287 {
288 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
289 }
290 #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
291 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
292 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
293 #define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
294 #define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
295 #define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
296 #define A4XX_INT0_VFD_ERROR 0x00000040
297 #define A4XX_INT0_CP_SW_INT 0x00000080
298 #define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
299 #define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
300 #define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
301 #define A4XX_INT0_CP_HW_FAULT 0x00000800
302 #define A4XX_INT0_CP_DMA 0x00001000
303 #define A4XX_INT0_CP_IB2_INT 0x00002000
304 #define A4XX_INT0_CP_IB1_INT 0x00004000
305 #define A4XX_INT0_CP_RB_INT 0x00008000
306 #define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
307 #define A4XX_INT0_CP_RB_DONE_TS 0x00020000
308 #define A4XX_INT0_CP_VS_DONE_TS 0x00040000
309 #define A4XX_INT0_CP_PS_DONE_TS 0x00080000
310 #define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
311 #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
312 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000
313 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
314 #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
315
316 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
317
318 #define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
319
320 #define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
321
322 #define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
323
324 #define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
325
326 #define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
327
328 #define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
329
330 #define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
331
332 #define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
333
334 #define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
335 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
336 #define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
337 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
338 {
339 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
340 }
341 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
342 #define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
343 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
344 {
345 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
346 }
347
348 #define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
349
350 #define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
351
352 #define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
353
354 #define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
355
356 #define REG_A4XX_RB_MODE_CONTROL 0x000020a0
357 #define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
358 #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
359 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
360 {
361 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
362 }
363 #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
364 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
365 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
366 {
367 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
368 }
369
370 #define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
371 #define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
372 #define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
373
374 #define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
375 #define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
376 #define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
377 #define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
378 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
379 {
380 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
381 }
382
383 #define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
384 #define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
385 #define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
386 #define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
387 #define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
388 #define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
389 #define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
390 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
391 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
392 #define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
393 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
394 {
395 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
396 }
397 #define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
398 #define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
399
400 static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
401
402 static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
403 #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
404 #define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
405 #define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
406 #define A4XX_RB_MRT_CONTROL_FASTCLEAR 0x00000400
407 #define A4XX_RB_MRT_CONTROL_B11 0x00000800
408 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
409 #define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
410 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
411 {
412 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
413 }
414
415 static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
416 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
417 #define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
418 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
419 {
420 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
421 }
422 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
423 #define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
424 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
425 {
426 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
427 }
428 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
429 #define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
430 static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
431 {
432 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
433 }
434 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
435 #define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
436 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
437 {
438 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
439 }
440 #define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
441 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
442 #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
443 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
444 {
445 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
446 }
447
448 static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
449
450 static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
451 #define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
452 #define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
453 static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
454 {
455 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
456 }
457
458 static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
459 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
460 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
461 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
462 {
463 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
464 }
465 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
466 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
467 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
468 {
469 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
470 }
471 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
472 #define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
473 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
474 {
475 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
476 }
477 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
478 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
479 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
480 {
481 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
482 }
483 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
484 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
485 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
486 {
487 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
488 }
489 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
490 #define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
491 static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
492 {
493 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
494 }
495
496 #define REG_A4XX_RB_BLEND_RED 0x000020f0
497 #define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff
498 #define A4XX_RB_BLEND_RED_UINT__SHIFT 0
499 static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
500 {
501 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
502 }
503 #define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
504 #define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
505 static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
506 {
507 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
508 }
509
510 #define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
511 #define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
512 #define A4XX_RB_BLEND_RED_F32__SHIFT 0
513 static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
514 {
515 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
516 }
517
518 #define REG_A4XX_RB_BLEND_GREEN 0x000020f2
519 #define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff
520 #define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
521 static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
522 {
523 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
524 }
525 #define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
526 #define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
527 static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
528 {
529 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
530 }
531
532 #define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
533 #define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
534 #define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
535 static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
536 {
537 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
538 }
539
540 #define REG_A4XX_RB_BLEND_BLUE 0x000020f4
541 #define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff
542 #define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
543 static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
544 {
545 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
546 }
547 #define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
548 #define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
549 static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
550 {
551 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
552 }
553
554 #define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
555 #define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
556 #define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
557 static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
558 {
559 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
560 }
561
562 #define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
563 #define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff
564 #define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
565 static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
566 {
567 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
568 }
569 #define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
570 #define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
571 static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
572 {
573 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
574 }
575
576 #define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
577 #define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
578 #define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
579 static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
580 {
581 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
582 }
583
584 #define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
585 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
586 #define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
587 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
588 {
589 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
590 }
591 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
592 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
593 #define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
594 static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
595 {
596 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
597 }
598
599 #define REG_A4XX_RB_FS_OUTPUT 0x000020f9
600 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
601 #define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
602 static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
603 {
604 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
605 }
606 #define A4XX_RB_FS_OUTPUT_FAST_CLEAR 0x00000100
607 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
608 #define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
609 static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
610 {
611 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
612 }
613
614 #define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
615 #define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
616 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
617 #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
618 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
619 {
620 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
621 }
622
623 #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
624 #define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
625 #define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
626 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
627 {
628 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
629 }
630 #define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
631 #define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
632 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
633 {
634 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
635 }
636 #define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
637 #define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
638 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
639 {
640 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
641 }
642 #define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
643 #define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
644 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
645 {
646 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
647 }
648 #define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
649 #define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
650 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
651 {
652 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
653 }
654 #define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
655 #define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
656 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
657 {
658 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
659 }
660 #define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
661 #define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
662 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
663 {
664 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
665 }
666 #define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
667 #define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
668 static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
669 {
670 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
671 }
672
673 #define REG_A4XX_RB_COPY_CONTROL 0x000020fc
674 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
675 #define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
676 static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
677 {
678 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
679 }
680 #define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
681 #define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
682 static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
683 {
684 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
685 }
686 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
687 #define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
688 static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
689 {
690 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
691 }
692 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
693 #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
694 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
695 {
696 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
697 }
698
699 #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
700 #define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
701 #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
702 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
703 {
704 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
705 }
706
707 #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
708 #define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
709 #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
710 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
711 {
712 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
713 }
714
715 #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
716 #define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
717 #define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
718 static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
719 {
720 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
721 }
722 #define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
723 #define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
724 static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
725 {
726 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
727 }
728 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
729 #define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
730 static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
731 {
732 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
733 }
734 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
735 #define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
736 static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
737 {
738 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
739 }
740 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
741 #define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
742 static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
743 {
744 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
745 }
746 #define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
747 #define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
748 static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
749 {
750 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
751 }
752
753 #define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
754 #define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
755 #define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
756 static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
757 {
758 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
759 }
760 #define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
761
762 #define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
763 #define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
764 #define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
765 #define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
766 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
767 #define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
768 static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
769 {
770 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
771 }
772 #define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
773 #define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
774 #define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
775
776 #define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
777
778 #define REG_A4XX_RB_DEPTH_INFO 0x00002103
779 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
780 #define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
781 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
782 {
783 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
784 }
785 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
786 #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
787 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
788 {
789 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
790 }
791
792 #define REG_A4XX_RB_DEPTH_PITCH 0x00002104
793 #define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
794 #define A4XX_RB_DEPTH_PITCH__SHIFT 0
795 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
796 {
797 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
798 }
799
800 #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
801 #define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
802 #define A4XX_RB_DEPTH_PITCH2__SHIFT 0
803 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
804 {
805 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
806 }
807
808 #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
809 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
810 #define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
811 #define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
812 #define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
813 #define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
814 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
815 {
816 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
817 }
818 #define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
819 #define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
820 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
821 {
822 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
823 }
824 #define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
825 #define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
826 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
827 {
828 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
829 }
830 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
831 #define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
832 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
833 {
834 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
835 }
836 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
837 #define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
838 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
839 {
840 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
841 }
842 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
843 #define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
844 static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
845 {
846 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
847 }
848 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
849 #define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
850 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
851 {
852 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
853 }
854 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
855 #define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
856 static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
857 {
858 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
859 }
860
861 #define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
862 #define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
863
864 #define REG_A4XX_RB_STENCIL_INFO 0x00002108
865 #define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
866 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
867 #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
868 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
869 {
870 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
871 }
872
873 #define REG_A4XX_RB_STENCIL_PITCH 0x00002109
874 #define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
875 #define A4XX_RB_STENCIL_PITCH__SHIFT 0
876 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
877 {
878 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
879 }
880
881 #define REG_A4XX_RB_STENCILREFMASK 0x0000210b
882 #define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
883 #define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
884 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
885 {
886 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
887 }
888 #define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
889 #define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
890 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
891 {
892 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
893 }
894 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
895 #define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
896 static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
897 {
898 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
899 }
900
901 #define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
902 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
903 #define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
904 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
905 {
906 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
907 }
908 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
909 #define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
910 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
911 {
912 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
913 }
914 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
915 #define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
916 static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
917 {
918 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
919 }
920
921 #define REG_A4XX_RB_BIN_OFFSET 0x0000210d
922 #define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
923 #define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
924 #define A4XX_RB_BIN_OFFSET_X__SHIFT 0
925 static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
926 {
927 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
928 }
929 #define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
930 #define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
931 static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
932 {
933 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
934 }
935
936 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
937
938 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
939
940 static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
941
942 #define REG_A4XX_RBBM_HW_VERSION 0x00000000
943
944 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
945
946 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
947
948 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
949
950 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
951
952 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
953
954 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
955
956 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
957
958 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
959
960 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
961
962 #define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
963
964 #define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
965
966 #define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
967
968 #define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
969
970 #define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
971
972 #define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
973
974 #define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
975
976 #define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
977
978 #define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
979
980 #define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
981
982 #define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
983
984 #define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
985
986 #define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
987
988 #define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
989
990 #define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
991
992 #define REG_A4XX_RBBM_AHB_CTL0 0x00000023
993
994 #define REG_A4XX_RBBM_AHB_CTL1 0x00000024
995
996 #define REG_A4XX_RBBM_AHB_CMD 0x00000025
997
998 #define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
999
1000 #define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
1001
1002 #define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
1003
1004 #define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
1005
1006 #define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
1007
1008 #define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
1009
1010 #define REG_A4XX_RBBM_INT_0_MASK 0x00000037
1011
1012 #define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
1013
1014 #define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
1015
1016 #define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
1017
1018 #define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
1019
1020 #define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1021
1022 #define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
1023
1024 #define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
1025
1026 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1027
1028 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1029
1030 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1031
1032 #define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1033
1034 #define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1035
1036 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1037
1038 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1039
1040 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1041
1042 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1043
1044 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1045
1046 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
1047
1048 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1049
1050 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
1051
1052 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1053
1054 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
1055
1056 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1057
1058 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
1059
1060 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1061
1062 static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
1063
1064 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1065
1066 static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
1067
1068 #define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
1069
1070 #define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
1071
1072 #define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
1073
1074 #define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
1075
1076 #define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
1077
1078 #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
1079
1080 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1081
1082 static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
1083
1084 #define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
1085
1086 #define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
1087
1088 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
1089
1090 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
1091
1092 #define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
1093
1094 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
1095
1096 #define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
1097
1098 #define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
1099
1100 #define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
1101
1102 #define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
1103
1104 #define REG_A4XX_RBBM_AHB_STATUS 0x00000189
1105
1106 #define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
1107
1108 #define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
1109
1110 #define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
1111
1112 #define REG_A4XX_RBBM_STATUS 0x00000191
1113 #define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
1114 #define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1115 #define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1116 #define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
1117 #define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
1118 #define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
1119 #define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
1120 #define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
1121 #define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1122 #define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1123 #define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
1124 #define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
1125 #define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
1126 #define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
1127 #define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
1128 #define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
1129 #define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
1130 #define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
1131 #define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1132 #define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
1133 #define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
1134
1135 #define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
1136
1137 #define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
1138
1139 #define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
1140
1141 #define REG_A4XX_CP_RB_BASE 0x00000200
1142
1143 #define REG_A4XX_CP_RB_CNTL 0x00000201
1144
1145 #define REG_A4XX_CP_RB_WPTR 0x00000205
1146
1147 #define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
1148
1149 #define REG_A4XX_CP_RB_RPTR 0x00000204
1150
1151 #define REG_A4XX_CP_IB1_BASE 0x00000206
1152
1153 #define REG_A4XX_CP_IB1_BUFSZ 0x00000207
1154
1155 #define REG_A4XX_CP_IB2_BASE 0x00000208
1156
1157 #define REG_A4XX_CP_IB2_BUFSZ 0x00000209
1158
1159 #define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
1160
1161 #define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
1162
1163 #define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
1164
1165 #define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
1166
1167 #define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
1168
1169 #define REG_A4XX_CP_ROQ_ADDR 0x0000021c
1170
1171 #define REG_A4XX_CP_ROQ_DATA 0x0000021d
1172
1173 #define REG_A4XX_CP_MEQ_ADDR 0x0000021e
1174
1175 #define REG_A4XX_CP_MEQ_DATA 0x0000021f
1176
1177 #define REG_A4XX_CP_MERCIU_ADDR 0x00000220
1178
1179 #define REG_A4XX_CP_MERCIU_DATA 0x00000221
1180
1181 #define REG_A4XX_CP_MERCIU_DATA2 0x00000222
1182
1183 #define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
1184
1185 #define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
1186
1187 #define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
1188
1189 #define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
1190
1191 #define REG_A4XX_CP_ME_RAM_DATA 0x00000227
1192
1193 #define REG_A4XX_CP_PREEMPT 0x0000022a
1194
1195 #define REG_A4XX_CP_CNTL 0x0000022c
1196
1197 #define REG_A4XX_CP_ME_CNTL 0x0000022d
1198
1199 #define REG_A4XX_CP_DEBUG 0x0000022e
1200
1201 #define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
1202
1203 #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
1204
1205 #define REG_A4XX_CP_PROTECT_REG_0 0x00000240
1206
1207 static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1208
1209 static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
1210
1211 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250
1212
1213 #define REG_A4XX_CP_ST_BASE 0x000004c0
1214
1215 #define REG_A4XX_CP_STQ_AVAIL 0x000004ce
1216
1217 #define REG_A4XX_CP_MERCIU_STAT 0x000004d0
1218
1219 #define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
1220
1221 #define REG_A4XX_CP_HW_FAULT 0x000004d8
1222
1223 #define REG_A4XX_CP_PROTECT_STATUS 0x000004da
1224
1225 #define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
1226
1227 #define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
1228
1229 #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
1230
1231 static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1232
1233 static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
1234
1235 #define REG_A4XX_SP_VS_STATUS 0x00000ec0
1236
1237 #define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
1238
1239 #define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
1240
1241 #define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
1242 #define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
1243
1244 #define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
1245 #define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
1246 #define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
1247 #define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
1248
1249 #define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
1250 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
1251 #define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
1252 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1253 {
1254 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
1255 }
1256 #define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
1257 #define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
1258 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1259 #define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1260 static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1261 {
1262 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1263 }
1264 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1265 #define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1266 static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1267 {
1268 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1269 }
1270 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1271 #define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1272 static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1273 {
1274 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1275 }
1276 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1277 #define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
1278 static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1279 {
1280 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
1281 }
1282 #define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1283 #define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1284
1285 #define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
1286 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1287 #define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1288 static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1289 {
1290 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
1291 }
1292 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
1293 #define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
1294 static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
1295 {
1296 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
1297 }
1298
1299 #define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
1300 #define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
1301 #define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
1302 static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
1303 {
1304 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
1305 }
1306 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
1307 #define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
1308 static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
1309 {
1310 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
1311 }
1312 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
1313 #define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
1314 static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
1315 {
1316 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
1317 }
1318
1319 static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1320
1321 static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
1322 #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
1323 #define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
1324 static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
1325 {
1326 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
1327 }
1328 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1329 #define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
1330 static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
1331 {
1332 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
1333 }
1334 #define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
1335 #define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
1336 static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
1337 {
1338 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
1339 }
1340 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1341 #define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
1342 static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
1343 {
1344 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
1345 }
1346
1347 static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1348
1349 static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
1350 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1351 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
1352 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
1353 {
1354 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
1355 }
1356 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1357 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
1358 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
1359 {
1360 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
1361 }
1362 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1363 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
1364 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
1365 {
1366 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
1367 }
1368 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1369 #define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
1370 static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
1371 {
1372 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
1373 }
1374
1375 #define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
1376 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1377 #define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1378 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1379 {
1380 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1381 }
1382 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1383 #define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1384 static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1385 {
1386 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1387 }
1388
1389 #define REG_A4XX_SP_VS_OBJ_START 0x000022e1
1390
1391 #define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
1392
1393 #define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
1394
1395 #define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
1396
1397 #define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
1398 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
1399 #define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
1400 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
1401 {
1402 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
1403 }
1404 #define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
1405 #define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
1406 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
1407 #define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
1408 static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
1409 {
1410 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
1411 }
1412 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
1413 #define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
1414 static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
1415 {
1416 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
1417 }
1418 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
1419 #define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
1420 static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
1421 {
1422 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
1423 }
1424 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
1425 #define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
1426 static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1427 {
1428 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
1429 }
1430 #define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1431 #define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1432
1433 #define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
1434 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
1435 #define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
1436 static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
1437 {
1438 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
1439 }
1440 #define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
1441 #define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
1442 #define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
1443
1444 #define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
1445 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1446 #define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1447 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1448 {
1449 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1450 }
1451 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1452 #define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1453 static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1454 {
1455 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1456 }
1457
1458 #define REG_A4XX_SP_FS_OBJ_START 0x000022eb
1459
1460 #define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
1461
1462 #define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
1463
1464 #define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
1465
1466 #define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
1467 #define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1468 #define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
1469 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
1470 {
1471 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
1472 }
1473 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
1474 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
1475 #define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
1476 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
1477 {
1478 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
1479 }
1480 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
1481 #define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
1482 static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
1483 {
1484 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
1485 }
1486
1487 static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1488
1489 static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
1490 #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
1491 #define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
1492 static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
1493 {
1494 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
1495 }
1496 #define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
1497 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
1498 #define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
1499 static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
1500 {
1501 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
1502 }
1503 #define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
1504
1505 #define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
1506
1507 #define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
1508
1509 #define REG_A4XX_SP_CS_OBJ_START 0x00002302
1510
1511 #define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
1512
1513 #define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
1514
1515 #define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
1516
1517 #define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
1518
1519 #define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
1520 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1521 #define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1522 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1523 {
1524 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1525 }
1526 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1527 #define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1528 static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1529 {
1530 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1531 }
1532
1533 #define REG_A4XX_SP_HS_OBJ_START 0x0000230e
1534
1535 #define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
1536
1537 #define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
1538
1539 #define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
1540
1541 #define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
1542 #define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
1543 #define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
1544 static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
1545 {
1546 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
1547 }
1548 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1549 #define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1550 static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1551 {
1552 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
1553 }
1554
1555 static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1556
1557 static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
1558 #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
1559 #define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
1560 static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
1561 {
1562 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
1563 }
1564 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1565 #define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
1566 static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
1567 {
1568 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
1569 }
1570 #define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
1571 #define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
1572 static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
1573 {
1574 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
1575 }
1576 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1577 #define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
1578 static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
1579 {
1580 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
1581 }
1582
1583 static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1584
1585 static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
1586 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1587 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
1588 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
1589 {
1590 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
1591 }
1592 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1593 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
1594 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
1595 {
1596 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
1597 }
1598 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1599 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
1600 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
1601 {
1602 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
1603 }
1604 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1605 #define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
1606 static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
1607 {
1608 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
1609 }
1610
1611 #define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
1612 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1613 #define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1614 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1615 {
1616 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1617 }
1618 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1619 #define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1620 static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1621 {
1622 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1623 }
1624
1625 #define REG_A4XX_SP_DS_OBJ_START 0x00002335
1626
1627 #define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
1628
1629 #define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
1630
1631 #define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
1632
1633 #define REG_A4XX_SP_GS_PARAM_REG 0x00002341
1634 #define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
1635 #define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
1636 static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
1637 {
1638 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
1639 }
1640 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
1641 #define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
1642 static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
1643 {
1644 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
1645 }
1646 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
1647 #define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
1648 static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
1649 {
1650 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
1651 }
1652
1653 static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1654
1655 static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
1656 #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
1657 #define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
1658 static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
1659 {
1660 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
1661 }
1662 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
1663 #define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
1664 static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
1665 {
1666 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
1667 }
1668 #define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
1669 #define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
1670 static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
1671 {
1672 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
1673 }
1674 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
1675 #define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
1676 static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
1677 {
1678 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
1679 }
1680
1681 static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1682
1683 static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
1684 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
1685 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
1686 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
1687 {
1688 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
1689 }
1690 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
1691 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
1692 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
1693 {
1694 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
1695 }
1696 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
1697 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
1698 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
1699 {
1700 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
1701 }
1702 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
1703 #define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
1704 static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
1705 {
1706 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
1707 }
1708
1709 #define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
1710 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
1711 #define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
1712 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
1713 {
1714 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
1715 }
1716 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
1717 #define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
1718 static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1719 {
1720 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
1721 }
1722
1723 #define REG_A4XX_SP_GS_OBJ_START 0x0000235c
1724
1725 #define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
1726
1727 #define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
1728
1729 #define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
1730
1731 #define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
1732
1733 #define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
1734
1735 #define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
1736
1737 #define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
1738
1739 #define REG_A4XX_VPC_ATTR 0x00002140
1740 #define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1741 #define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
1742 static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
1743 {
1744 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
1745 }
1746 #define A4XX_VPC_ATTR_PSIZE 0x00000200
1747 #define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
1748 #define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1749 static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
1750 {
1751 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
1752 }
1753 #define A4XX_VPC_ATTR_ENABLE 0x02000000
1754
1755 #define REG_A4XX_VPC_PACK 0x00002141
1756 #define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
1757 #define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
1758 static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
1759 {
1760 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
1761 }
1762 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
1763 #define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
1764 static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
1765 {
1766 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
1767 }
1768 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
1769 #define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
1770 static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
1771 {
1772 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
1773 }
1774
1775 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1776
1777 static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
1778
1779 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1780
1781 static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
1782
1783 #define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
1784
1785 #define REG_A4XX_VSC_BIN_SIZE 0x00000c00
1786 #define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1787 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1788 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1789 {
1790 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
1791 }
1792 #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
1793 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
1794 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1795 {
1796 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
1797 }
1798
1799 #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
1800
1801 #define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
1802
1803 #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
1804
1805 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1806
1807 static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
1808 #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1809 #define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1810 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1811 {
1812 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
1813 }
1814 #define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1815 #define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1816 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1817 {
1818 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1819 }
1820 #define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1821 #define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1822 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1823 {
1824 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
1825 }
1826 #define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1827 #define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
1828 static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1829 {
1830 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
1831 }
1832
1833 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1834
1835 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
1836
1837 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1838
1839 static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
1840
1841 #define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
1842
1843 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
1844
1845 #define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
1846
1847 #define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
1848
1849 #define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
1850
1851 #define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
1852
1853 #define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
1854
1855 #define REG_A4XX_VFD_CONTROL_0 0x00002200
1856 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
1857 #define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1858 static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1859 {
1860 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1861 }
1862 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
1863 #define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
1864 static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
1865 {
1866 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
1867 }
1868 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
1869 #define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
1870 static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1871 {
1872 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1873 }
1874 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
1875 #define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
1876 static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1877 {
1878 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1879 }
1880
1881 #define REG_A4XX_VFD_CONTROL_1 0x00002201
1882 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
1883 #define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1884 static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1885 {
1886 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1887 }
1888 #define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1889 #define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1890 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1891 {
1892 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
1893 }
1894 #define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1895 #define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1896 static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1897 {
1898 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
1899 }
1900
1901 #define REG_A4XX_VFD_CONTROL_2 0x00002202
1902
1903 #define REG_A4XX_VFD_CONTROL_3 0x00002203
1904 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
1905 #define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
1906 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
1907 {
1908 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
1909 }
1910 #define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
1911 #define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
1912 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
1913 {
1914 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
1915 }
1916 #define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
1917 #define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
1918 static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
1919 {
1920 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
1921 }
1922
1923 #define REG_A4XX_VFD_CONTROL_4 0x00002204
1924
1925 #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
1926
1927 static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1928
1929 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
1930 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1931 #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1932 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1933 {
1934 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1935 }
1936 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
1937 #define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1938 static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1939 {
1940 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1941 }
1942 #define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
1943 #define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
1944
1945 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
1946
1947 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
1948 #define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
1949 #define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
1950 static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
1951 {
1952 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
1953 }
1954
1955 static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
1956 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
1957 #define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
1958 static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
1959 {
1960 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
1961 }
1962
1963 static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1964
1965 static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
1966 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1967 #define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1968 static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1969 {
1970 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
1971 }
1972 #define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
1973 #define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
1974 #define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
1975 static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
1976 {
1977 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
1978 }
1979 #define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
1980 #define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
1981 static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
1982 {
1983 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
1984 }
1985 #define A4XX_VFD_DECODE_INSTR_INT 0x00100000
1986 #define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
1987 #define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
1988 static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
1989 {
1990 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
1991 }
1992 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
1993 #define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
1994 static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
1995 {
1996 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
1997 }
1998 #define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
1999 #define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
2000
2001 #define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
2002
2003 #define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
2004
2005 #define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
2006
2007 #define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
2008
2009 #define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
2010 #define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
2011 #define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
2012 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
2013 {
2014 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
2015 }
2016 #define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
2017 #define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
2018 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
2019 {
2020 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
2021 }
2022 #define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
2023 #define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
2024 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
2025 {
2026 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
2027 }
2028 #define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
2029 #define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
2030 static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
2031 {
2032 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
2033 }
2034
2035 #define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
2036
2037 #define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
2038
2039 #define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
2040
2041 #define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
2042
2043 #define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
2044
2045 #define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
2046
2047 #define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
2048
2049 #define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
2050
2051 #define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
2052
2053 #define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
2054
2055 #define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
2056
2057 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
2058
2059 #define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
2060
2061 #define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
2062
2063 #define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
2064 #define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
2065
2066 #define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
2067 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
2068 #define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
2069 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
2070 {
2071 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
2072 }
2073 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
2074 #define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
2075 static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
2076 {
2077 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
2078 }
2079
2080 #define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
2081 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2082 #define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2083 static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2084 {
2085 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2086 }
2087
2088 #define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
2089 #define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2090 #define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2091 static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
2092 {
2093 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2094 }
2095
2096 #define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
2097 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2098 #define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2099 static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2100 {
2101 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2102 }
2103
2104 #define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
2105 #define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2106 #define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2107 static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
2108 {
2109 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2110 }
2111
2112 #define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
2113 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2114 #define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2115 static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2116 {
2117 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2118 }
2119
2120 #define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
2121 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2122 #define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2123 static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2124 {
2125 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2126 }
2127
2128 #define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
2129 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2130 #define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2131 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2132 {
2133 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2134 }
2135 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2136 #define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2137 static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2138 {
2139 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2140 }
2141
2142 #define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
2143 #define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2144 #define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
2145 static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
2146 {
2147 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
2148 }
2149
2150 #define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
2151 #define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
2152
2153 #define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
2154 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2155 #define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2156 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2157 {
2158 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2159 }
2160
2161 #define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
2162 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2163 #define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2164 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2165 {
2166 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2167 }
2168
2169 #define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
2170 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
2171 #define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
2172 static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
2173 {
2174 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
2175 }
2176
2177 #define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
2178 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
2179 #define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
2180 static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
2181 {
2182 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
2183 }
2184
2185 #define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
2186 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
2187 #define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
2188 #define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
2189 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
2190 #define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
2191 static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
2192 {
2193 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
2194 }
2195 #define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
2196 #define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
2197
2198 #define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
2199 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
2200 #define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
2201 static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
2202 {
2203 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
2204 }
2205 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
2206 #define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
2207 static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
2208 {
2209 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
2210 }
2211 #define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
2212 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
2213 #define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
2214 static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
2215 {
2216 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
2217 }
2218
2219 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
2220 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2221 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
2222 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
2223 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
2224 {
2225 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
2226 }
2227 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
2228 #define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
2229 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
2230 {
2231 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
2232 }
2233
2234 #define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
2235 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2236 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
2237 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
2238 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
2239 {
2240 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
2241 }
2242 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
2243 #define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
2244 static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
2245 {
2246 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
2247 }
2248
2249 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
2250 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2251 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2252 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2253 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2254 {
2255 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2256 }
2257 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2258 #define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2259 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2260 {
2261 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2262 }
2263
2264 #define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
2265 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2266 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2267 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2268 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2269 {
2270 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2271 }
2272 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2273 #define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2274 static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2275 {
2276 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2277 }
2278
2279 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
2280 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
2281 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
2282 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
2283 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
2284 {
2285 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
2286 }
2287 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
2288 #define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
2289 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
2290 {
2291 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
2292 }
2293
2294 #define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
2295 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
2296 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
2297 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
2298 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
2299 {
2300 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
2301 }
2302 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
2303 #define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
2304 static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
2305 {
2306 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
2307 }
2308
2309 #define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
2310
2311 #define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
2312
2313 #define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
2314
2315 #define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
2316
2317 #define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
2318
2319 #define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
2320
2321 #define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
2322
2323 #define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
2324
2325 #define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
2326
2327 #define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
2328
2329 #define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
2330
2331 #define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
2332
2333 #define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
2334 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
2335 #define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
2336 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
2337 {
2338 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
2339 }
2340 #define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
2341 #define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
2342 #define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
2343 #define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
2344 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
2345 #define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
2346 static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
2347 {
2348 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
2349 }
2350 #define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
2351 #define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
2352 #define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
2353 #define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
2354
2355 #define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
2356 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
2357 #define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
2358 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
2359 {
2360 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
2361 }
2362 #define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
2363 #define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
2364 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
2365 #define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
2366 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
2367 {
2368 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
2369 }
2370 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
2371 #define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
2372 static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
2373 {
2374 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
2375 }
2376
2377 #define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
2378 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
2379 #define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
2380 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
2381 {
2382 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
2383 }
2384 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
2385 #define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
2386 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
2387 {
2388 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
2389 }
2390 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
2391 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
2392 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
2393 {
2394 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
2395 }
2396 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
2397 #define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
2398 static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
2399 {
2400 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
2401 }
2402
2403 #define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
2404 #define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
2405 #define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
2406 static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
2407 {
2408 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
2409 }
2410
2411 #define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
2412
2413 #define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
2414 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2415 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2416 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2417 {
2418 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
2419 }
2420 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2421 #define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2422 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2423 {
2424 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2425 }
2426 #define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
2427 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2428 #define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2429 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2430 {
2431 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2432 }
2433 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2434 #define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2435 static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2436 {
2437 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
2438 }
2439
2440 #define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
2441 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2442 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2443 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2444 {
2445 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
2446 }
2447 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2448 #define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2449 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2450 {
2451 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2452 }
2453 #define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
2454 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2455 #define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2456 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2457 {
2458 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2459 }
2460 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2461 #define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2462 static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2463 {
2464 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
2465 }
2466
2467 #define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
2468 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2469 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2470 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2471 {
2472 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
2473 }
2474 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2475 #define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2476 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2477 {
2478 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2479 }
2480 #define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
2481 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2482 #define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2483 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2484 {
2485 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2486 }
2487 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2488 #define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2489 static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2490 {
2491 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
2492 }
2493
2494 #define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
2495 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2496 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2497 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2498 {
2499 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
2500 }
2501 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2502 #define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2503 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2504 {
2505 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2506 }
2507 #define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
2508 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2509 #define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2510 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2511 {
2512 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2513 }
2514 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2515 #define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2516 static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2517 {
2518 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
2519 }
2520
2521 #define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
2522 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
2523 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
2524 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
2525 {
2526 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
2527 }
2528 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
2529 #define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
2530 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
2531 {
2532 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
2533 }
2534 #define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
2535 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
2536 #define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
2537 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
2538 {
2539 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
2540 }
2541 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
2542 #define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
2543 static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
2544 {
2545 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
2546 }
2547
2548 #define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca
2549
2550 #define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
2551
2552 #define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
2553
2554 #define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
2555
2556 #define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
2557
2558 #define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
2559
2560 #define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
2561
2562 #define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
2563
2564 #define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
2565
2566 #define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
2567
2568 #define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
2569
2570 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
2571
2572 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
2573
2574 #define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
2575
2576 #define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
2577
2578 #define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
2579
2580 #define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
2581 #define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
2582
2583 #define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
2584
2585 #define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2586
2587 #define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2588
2589 #define REG_A4XX_PC_BIN_BASE 0x000021c0
2590
2591 #define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
2592 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
2593 #define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
2594 static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
2595 {
2596 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
2597 }
2598 #define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
2599 #define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
2600 #define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
2601
2602 #define REG_A4XX_UNKNOWN_21C5 0x000021c5
2603
2604 #define REG_A4XX_PC_RESTART_INDEX 0x000021c6
2605
2606 #define REG_A4XX_PC_GS_PARAM 0x000021e5
2607 #define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
2608 #define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
2609 static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
2610 {
2611 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
2612 }
2613 #define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
2614 #define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
2615 static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
2616 {
2617 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
2618 }
2619 #define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
2620 #define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
2621 static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2622 {
2623 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
2624 }
2625 #define A4XX_PC_GS_PARAM_LAYER 0x80000000
2626
2627 #define REG_A4XX_PC_HS_PARAM 0x000021e7
2628 #define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
2629 #define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
2630 static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
2631 {
2632 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
2633 }
2634 #define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
2635 #define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
2636 static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
2637 {
2638 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
2639 }
2640 #define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000
2641 #define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23
2642 static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
2643 {
2644 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
2645 }
2646
2647 #define REG_A4XX_VBIF_VERSION 0x00003000
2648
2649 #define REG_A4XX_VBIF_CLKON 0x00003001
2650 #define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
2651
2652 #define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
2653
2654 #define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
2655
2656 #define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2657
2658 #define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2659
2660 #define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2661
2662 #define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
2663
2664 #define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
2665
2666 #define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2667
2668 #define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
2669
2670 #define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
2671
2672 #define REG_A4XX_UNKNOWN_0D01 0x00000d01
2673
2674 #define REG_A4XX_UNKNOWN_0E42 0x00000e42
2675
2676 #define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
2677
2678 #define REG_A4XX_UNKNOWN_2001 0x00002001
2679
2680 #define REG_A4XX_UNKNOWN_209B 0x0000209b
2681
2682 #define REG_A4XX_UNKNOWN_20EF 0x000020ef
2683
2684 #define REG_A4XX_UNKNOWN_2152 0x00002152
2685
2686 #define REG_A4XX_UNKNOWN_2153 0x00002153
2687
2688 #define REG_A4XX_UNKNOWN_2154 0x00002154
2689
2690 #define REG_A4XX_UNKNOWN_2155 0x00002155
2691
2692 #define REG_A4XX_UNKNOWN_2156 0x00002156
2693
2694 #define REG_A4XX_UNKNOWN_2157 0x00002157
2695
2696 #define REG_A4XX_UNKNOWN_21C3 0x000021c3
2697
2698 #define REG_A4XX_UNKNOWN_21E6 0x000021e6
2699
2700 #define REG_A4XX_UNKNOWN_2209 0x00002209
2701
2702 #define REG_A4XX_UNKNOWN_22D7 0x000022d7
2703
2704 #define REG_A4XX_UNKNOWN_2352 0x00002352
2705
2706 #define REG_A4XX_TEX_SAMP_0 0x00000000
2707 #define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
2708 #define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
2709 #define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
2710 static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
2711 {
2712 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
2713 }
2714 #define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
2715 #define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
2716 static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
2717 {
2718 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
2719 }
2720 #define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
2721 #define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
2722 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
2723 {
2724 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
2725 }
2726 #define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
2727 #define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
2728 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
2729 {
2730 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
2731 }
2732 #define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
2733 #define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
2734 static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
2735 {
2736 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
2737 }
2738 #define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
2739 #define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
2740 static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
2741 {
2742 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
2743 }
2744
2745 #define REG_A4XX_TEX_SAMP_1 0x00000001
2746 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
2747 #define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
2748 static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
2749 {
2750 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
2751 }
2752 #define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
2753 #define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
2754 #define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
2755 #define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
2756 static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
2757 {
2758 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
2759 }
2760 #define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
2761 #define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
2762 static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
2763 {
2764 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
2765 }
2766
2767 #define REG_A4XX_TEX_CONST_0 0x00000000
2768 #define A4XX_TEX_CONST_0_TILED 0x00000001
2769 #define A4XX_TEX_CONST_0_SRGB 0x00000004
2770 #define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2771 #define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2772 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
2773 {
2774 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
2775 }
2776 #define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
2777 #define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
2778 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
2779 {
2780 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
2781 }
2782 #define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
2783 #define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
2784 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
2785 {
2786 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
2787 }
2788 #define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
2789 #define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
2790 static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
2791 {
2792 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
2793 }
2794 #define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
2795 #define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
2796 static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
2797 {
2798 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
2799 }
2800 #define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
2801 #define A4XX_TEX_CONST_0_FMT__SHIFT 22
2802 static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
2803 {
2804 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
2805 }
2806 #define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
2807 #define A4XX_TEX_CONST_0_TYPE__SHIFT 29
2808 static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
2809 {
2810 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
2811 }
2812
2813 #define REG_A4XX_TEX_CONST_1 0x00000001
2814 #define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
2815 #define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
2816 static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
2817 {
2818 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
2819 }
2820 #define A4XX_TEX_CONST_1_WIDTH__MASK 0x1fff8000
2821 #define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
2822 static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
2823 {
2824 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
2825 }
2826
2827 #define REG_A4XX_TEX_CONST_2 0x00000002
2828 #define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
2829 #define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
2830 static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
2831 {
2832 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
2833 }
2834 #define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
2835 #define A4XX_TEX_CONST_2_PITCH__SHIFT 9
2836 static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
2837 {
2838 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
2839 }
2840 #define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
2841 #define A4XX_TEX_CONST_2_SWAP__SHIFT 30
2842 static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
2843 {
2844 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
2845 }
2846
2847 #define REG_A4XX_TEX_CONST_3 0x00000003
2848 #define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
2849 #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
2850 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
2851 {
2852 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
2853 }
2854 #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
2855 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
2856 static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
2857 {
2858 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
2859 }
2860
2861 #define REG_A4XX_TEX_CONST_4 0x00000004
2862 #define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
2863 #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
2864 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
2865 {
2866 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
2867 }
2868 #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
2869 #define A4XX_TEX_CONST_4_BASE__SHIFT 5
2870 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
2871 {
2872 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
2873 }
2874
2875 #define REG_A4XX_TEX_CONST_5 0x00000005
2876
2877 #define REG_A4XX_TEX_CONST_6 0x00000006
2878
2879 #define REG_A4XX_TEX_CONST_7 0x00000007
2880
2881
2882 #endif /* A4XX_XML */