1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_prim.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
38 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_format.h"
46 draw_impl(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
47 struct fd4_emit
*emit
)
49 const struct pipe_draw_info
*info
= emit
->info
;
51 if (!(fd4_emit_get_vp(emit
) && fd4_emit_get_fp(emit
)))
54 fd4_emit_state(ctx
, ring
, emit
);
56 if (emit
->dirty
& (FD_DIRTY_VTXBUF
| FD_DIRTY_VTXSTATE
))
57 fd4_emit_vertex_bufs(ring
, emit
);
59 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
60 OUT_RING(ring
, info
->indexed
? info
->index_bias
: info
->start
); /* VFD_INDEX_OFFSET */
61 OUT_RING(ring
, info
->start_instance
); /* ??? UNKNOWN_2209 */
63 OUT_PKT0(ring
, REG_A4XX_PC_RESTART_INDEX
, 1);
64 OUT_RING(ring
, info
->primitive_restart
? /* PC_RESTART_INDEX */
65 info
->restart_index
: 0xffffffff);
67 fd4_draw_emit(ctx
, ring
,
68 emit
->key
.binning_pass
? IGNORE_VISIBILITY
: USE_VISIBILITY
,
72 /* fixup dirty shader state in case some "unrelated" (from the state-
73 * tracker's perspective) state change causes us to switch to a
77 fixup_shader_state(struct fd_context
*ctx
, struct ir3_shader_key
*key
)
79 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
80 struct ir3_shader_key
*last_key
= &fd4_ctx
->last_key
;
82 if (!ir3_shader_key_equal(last_key
, key
)) {
83 ctx
->dirty
|= FD_DIRTY_PROG
;
85 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
86 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
87 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
88 (last_key
->vsaturate_r
!= key
->vsaturate_r
))
89 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_VP
;
91 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
92 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
93 (last_key
->fsaturate_r
!= key
->fsaturate_r
))
94 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
97 if (last_key
->color_two_side
!= key
->color_two_side
)
98 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
100 if (last_key
->half_precision
!= key
->half_precision
)
101 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
103 if (last_key
->rasterflat
!= key
->rasterflat
)
104 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
106 fd4_ctx
->last_key
= *key
;
111 fd4_draw_vbo(struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
113 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
114 struct fd4_emit emit
= {
119 /* do binning pass first: */
120 .binning_pass
= true,
121 .color_two_side
= ctx
->rasterizer
? ctx
->rasterizer
->light_twoside
: false,
122 .rasterflat
= ctx
->rasterizer
&& ctx
->rasterizer
->flatshade
,
123 // TODO set .half_precision based on render target format,
124 // ie. float16 and smaller use half, float32 use full..
125 .half_precision
= !!(fd_mesa_debug
& FD_DBG_FRAGHALF
),
126 .ucp_enables
= ctx
->rasterizer
? ctx
->rasterizer
->clip_plane_enable
: 0,
127 .has_per_samp
= (fd4_ctx
->fsaturate
|| fd4_ctx
->vsaturate
),
128 .vsaturate_s
= fd4_ctx
->vsaturate_s
,
129 .vsaturate_t
= fd4_ctx
->vsaturate_t
,
130 .vsaturate_r
= fd4_ctx
->vsaturate_r
,
131 .fsaturate_s
= fd4_ctx
->fsaturate_s
,
132 .fsaturate_t
= fd4_ctx
->fsaturate_t
,
133 .fsaturate_r
= fd4_ctx
->fsaturate_r
,
135 .rasterflat
= ctx
->rasterizer
&& ctx
->rasterizer
->flatshade
,
136 .sprite_coord_enable
= ctx
->rasterizer
? ctx
->rasterizer
->sprite_coord_enable
: false,
137 .sprite_coord_mode
= ctx
->rasterizer
? ctx
->rasterizer
->sprite_coord_mode
: false,
141 fixup_shader_state(ctx
, &emit
.key
);
144 emit
.dirty
= dirty
& ~(FD_DIRTY_BLEND
);
145 draw_impl(ctx
, ctx
->binning_ring
, &emit
);
147 /* and now regular (non-binning) pass: */
148 emit
.key
.binning_pass
= false;
150 emit
.vp
= NULL
; /* we changed key so need to refetch vp */
151 draw_impl(ctx
, ctx
->ring
, &emit
);
154 /* clear operations ignore viewport state, so we need to reset it
155 * based on framebuffer state:
158 reset_viewport(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
)
160 float half_width
= pfb
->width
* 0.5f
;
161 float half_height
= pfb
->height
* 0.5f
;
163 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 4);
164 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width
));
165 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width
));
166 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height
));
167 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height
));
171 fd4_clear(struct fd_context
*ctx
, unsigned buffers
,
172 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
174 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
175 struct fd_ringbuffer
*ring
= ctx
->ring
;
176 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
177 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
178 unsigned dirty
= ctx
->dirty
;
180 struct fd4_emit emit
= {
181 .vtx
= &fd4_ctx
->solid_vbuf_state
,
182 .prog
= &ctx
->solid_prog
,
184 .half_precision
= fd_half_precision(pfb
),
188 dirty
&= FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_SCISSOR
;
189 dirty
|= FD_DIRTY_PROG
;
192 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 1);
193 OUT_RING(ring
, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
195 /* emit generic state now: */
196 fd4_emit_state(ctx
, ring
, &emit
);
197 reset_viewport(ring
, pfb
);
199 if (buffers
& PIPE_CLEAR_DEPTH
) {
200 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
201 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
202 A4XX_RB_DEPTH_CONTROL_Z_ENABLE
|
203 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
));
206 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0
, 2);
207 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
208 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth
));
209 ctx
->dirty
|= FD_DIRTY_VIEWPORT
;
211 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
212 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
215 if (buffers
& PIPE_CLEAR_STENCIL
) {
216 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
217 OUT_RING(ring
, A4XX_RB_STENCILREFMASK_STENCILREF(stencil
) |
218 A4XX_RB_STENCILREFMASK_STENCILMASK(stencil
) |
219 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
220 OUT_RING(ring
, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
221 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
222 0xff000000 | // XXX ???
223 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
225 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
226 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
227 A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
228 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
229 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE
) |
230 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
231 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
232 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
233 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
234 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
235 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER
);
237 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
238 OUT_RING(ring
, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
239 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
240 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
241 OUT_RING(ring
, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
242 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
243 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
245 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
246 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
247 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
248 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
249 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
250 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
251 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
252 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
253 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
254 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_CONTROL2 */
257 if (buffers
& PIPE_CLEAR_COLOR
) {
258 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
259 OUT_RING(ring
, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
));
262 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
263 mrt_comp
[i
] = (buffers
& (PIPE_CLEAR_COLOR0
<< i
)) ? 0xf : 0x0;
265 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
266 OUT_RING(ring
, A4XX_RB_MRT_CONTROL_FASTCLEAR
|
267 A4XX_RB_MRT_CONTROL_B11
|
268 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
270 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
271 OUT_RING(ring
, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
272 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
273 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
274 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
275 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
276 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
));
279 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
280 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
281 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
282 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
283 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
284 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
285 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
286 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
287 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
289 fd4_emit_vertex_bufs(ring
, &emit
);
291 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
292 OUT_RING(ring
, 0x0); /* XXX GRAS_ALPHA_CONTROL */
294 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
295 OUT_RING(ring
, 0x00000000);
297 /* until fastclear works: */
298 fd4_emit_const(ring
, SHADER_FRAGMENT
, 0, 0, 4, color
->ui
, NULL
);
300 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
301 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
302 OUT_RING(ring
, 0); /* ??? UNKNOWN_2209 */
304 OUT_PKT0(ring
, REG_A4XX_PC_RESTART_INDEX
, 1);
305 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
307 OUT_PKT3(ring
, CP_UNKNOWN_1A
, 1);
308 OUT_RING(ring
, 0x00000001);
310 fd4_draw(ctx
, ring
, DI_PT_RECTLIST
, USE_VISIBILITY
,
311 DI_SRC_SEL_AUTO_INDEX
, 2, 1, INDEX_SIZE_IGN
, 0, 0, NULL
);
313 OUT_PKT3(ring
, CP_UNKNOWN_1A
, 1);
314 OUT_RING(ring
, 0x00000000);
316 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
317 OUT_RING(ring
, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR
);
319 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
320 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
321 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
322 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
323 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
327 fd4_draw_init(struct pipe_context
*pctx
)
329 struct fd_context
*ctx
= fd_context(pctx
);
330 ctx
->draw_vbo
= fd4_draw_vbo
;
331 ctx
->clear
= fd4_clear
;