src/gallium/drivers/freedreno/a4xx/fd4_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd4_draw.h"
  38 #include "fd4_context.h"
  39 #include "fd4_emit.h"
  40 #include "fd4_program.h"
  41 #include "fd4_format.h"
  42 #include "fd4_zsa.h"
  43
  44
  45 static void
  46 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  47                 struct fd4_emit *emit)
  48 {
  49         const struct pipe_draw_info *info = emit->info;
  50         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  51
  52         fd4_emit_state(ctx, ring, emit);
  53
  54         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  55                 fd4_emit_vertex_bufs(ring, emit);
  56
  57         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
  58         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  59         OUT_RING(ring, info->start_instance);   /* ??? UNKNOWN_2209 */
  60
  61         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
  62         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  63                         info->restart_index : 0xffffffff);
  64
  65         /* points + psize -> spritelist: */
  66         if (ctx->rasterizer->point_size_per_vertex &&
  67                         fd4_emit_get_vp(emit)->writes_psize &&
  68                         (info->mode == PIPE_PRIM_POINTS))
  69                 primtype = DI_PT_POINTLIST_PSIZE;
  70
  71         fd4_draw_emit(ctx, ring,
  72                         primtype,
  73                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  74                         info);
  75 }
  76
  77 /* fixup dirty shader state in case some "unrelated" (from the state-
  78  * tracker's perspective) state change causes us to switch to a
  79  * different variant.
  80  */
  81 static void
  82 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  83 {
  84         struct fd4_context *fd4_ctx = fd4_context(ctx);
  85         struct ir3_shader_key *last_key = &fd4_ctx->last_key;
  86
  87         if (!ir3_shader_key_equal(last_key, key)) {
  88                 if (last_key->has_per_samp || key->has_per_samp) {
  89                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
  90                                         (last_key->vsaturate_t != key->vsaturate_t) ||
  91                                         (last_key->vsaturate_r != key->vsaturate_r) ||
  92                                         (last_key->vastc_srgb != key->vastc_srgb))
  93                                 ctx->dirty |= FD_SHADER_DIRTY_VP;
  94
  95                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
  96                                         (last_key->fsaturate_t != key->fsaturate_t) ||
  97                                         (last_key->fsaturate_r != key->fsaturate_r) ||
  98                                         (last_key->fastc_srgb != key->fastc_srgb))
  99                                 ctx->dirty |= FD_SHADER_DIRTY_FP;
 100                 }
 101
 102                 if (last_key->vclamp_color != key->vclamp_color)
 103                         ctx->dirty |= FD_SHADER_DIRTY_VP;
 104
 105                 if (last_key->fclamp_color != key->fclamp_color)
 106                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 107
 108                 if (last_key->color_two_side != key->color_two_side)
 109                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 110
 111                 if (last_key->half_precision != key->half_precision)
 112                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 113
 114                 if (last_key->rasterflat != key->rasterflat)
 115                         ctx->dirty |= FD_SHADER_DIRTY_FP;
 116
 117                 fd4_ctx->last_key = *key;
 118         }
 119 }
 120
 121 static bool
 122 fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 123 {
 124         struct fd4_context *fd4_ctx = fd4_context(ctx);
 125         struct fd4_emit emit = {
 126                 .debug = &ctx->debug,
 127                 .vtx  = &ctx->vtx,
 128                 .prog = &ctx->prog,
 129                 .info = info,
 130                 .key = {
 131                         .color_two_side = ctx->rasterizer->light_twoside,
 132                         .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 133                         .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 134                         .rasterflat = ctx->rasterizer->flatshade,
 135                         // TODO set .half_precision based on render target format,
 136                         // ie. float16 and smaller use half, float32 use full..
 137                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 138                         .ucp_enables = ctx->rasterizer->clip_plane_enable,
 139                         .has_per_samp = (fd4_ctx->fsaturate || fd4_ctx->vsaturate ||
 140                                         fd4_ctx->fastc_srgb || fd4_ctx->vastc_srgb),
 141                         .vsaturate_s = fd4_ctx->vsaturate_s,
 142                         .vsaturate_t = fd4_ctx->vsaturate_t,
 143                         .vsaturate_r = fd4_ctx->vsaturate_r,
 144                         .fsaturate_s = fd4_ctx->fsaturate_s,
 145                         .fsaturate_t = fd4_ctx->fsaturate_t,
 146                         .fsaturate_r = fd4_ctx->fsaturate_r,
 147                         .vastc_srgb = fd4_ctx->vastc_srgb,
 148                         .fastc_srgb = fd4_ctx->fastc_srgb,
 149                 },
 150                 .rasterflat = ctx->rasterizer->flatshade,
 151                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 152                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 153         };
 154
 155         fixup_shader_state(ctx, &emit.key);
 156
 157         unsigned dirty = ctx->dirty;
 158
 159         /* do regular pass first, since that is more likely to fail compiling: */
 160
 161         if (!(fd4_emit_get_vp(&emit) && fd4_emit_get_fp(&emit)))
 162                 return false;
 163
 164         emit.key.binning_pass = false;
 165         emit.dirty = dirty;
 166
 167         if (ctx->rasterizer->rasterizer_discard) {
 168                 fd_wfi(ctx, ctx->ring);
 169                 OUT_PKT3(ctx->ring, CP_REG_RMW, 3);
 170                 OUT_RING(ctx->ring, REG_A4XX_RB_RENDER_CONTROL);
 171                 OUT_RING(ctx->ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 172                 OUT_RING(ctx->ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 173         }
 174
 175         draw_impl(ctx, ctx->ring, &emit);
 176
 177         if (ctx->rasterizer->rasterizer_discard) {
 178                 fd_wfi(ctx, ctx->ring);
 179                 OUT_PKT3(ctx->ring, CP_REG_RMW, 3);
 180                 OUT_RING(ctx->ring, REG_A4XX_RB_RENDER_CONTROL);
 181                 OUT_RING(ctx->ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 182                 OUT_RING(ctx->ring, 0);
 183         }
 184
 185         /* and now binning pass: */
 186         emit.key.binning_pass = true;
 187         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 188         emit.vp = NULL;   /* we changed key so need to refetch vp */
 189         emit.fp = NULL;
 190         draw_impl(ctx, ctx->binning_ring, &emit);
 191
 192         return true;
 193 }
 194
 195 /* clear operations ignore viewport state, so we need to reset it
 196  * based on framebuffer state:
 197  */
 198 static void
 199 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 200 {
 201         float half_width = pfb->width * 0.5f;
 202         float half_height = pfb->height * 0.5f;
 203
 204         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 4);
 205         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width));
 206         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width));
 207         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height));
 208         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height));
 209 }
 210
 211 /* TODO maybe we should just migrate u_blitter for clear and do it in
 212  * core (so we get normal draw pass state mgmt and binning).. That should
 213  * work well enough for a3xx/a4xx (but maybe not a2xx?)
 214  */
 215
 216 static void
 217 fd4_clear_binning(struct fd_context *ctx, unsigned dirty)
 218 {
 219         struct fd4_context *fd4_ctx = fd4_context(ctx);
 220         struct fd_ringbuffer *ring = ctx->binning_ring;
 221         struct fd4_emit emit = {
 222                 .debug = &ctx->debug,
 223                 .vtx  = &fd4_ctx->solid_vbuf_state,
 224                 .prog = &ctx->solid_prog,
 225                 .key = {
 226                         .binning_pass = true,
 227                         .half_precision = true,
 228                 },
 229                 .dirty = dirty,
 230         };
 231
 232         fd4_emit_state(ctx, ring, &emit);
 233         fd4_emit_vertex_bufs(ring, &emit);
 234         reset_viewport(ring, &ctx->framebuffer);
 235
 236         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
 237         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_VAROUT(0) |
 238                         A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 239         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 240                         A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES));
 241
 242         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 243         OUT_RING(ring, 0x00000002);
 244
 245         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 246                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 247 }
 248
 249 static void
 250 fd4_clear(struct fd_context *ctx, unsigned buffers,
 251                 const union pipe_color_union *color, double depth, unsigned stencil)
 252 {
 253         struct fd4_context *fd4_ctx = fd4_context(ctx);
 254         struct fd_ringbuffer *ring = ctx->ring;
 255         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 256         unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 257         unsigned dirty = ctx->dirty;
 258         unsigned i;
 259         struct fd4_emit emit = {
 260                 .debug = &ctx->debug,
 261                 .vtx  = &fd4_ctx->solid_vbuf_state,
 262                 .prog = &ctx->solid_prog,
 263                 .key = {
 264                         .half_precision = fd_half_precision(pfb),
 265                 },
 266         };
 267
 268         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 269         dirty |= FD_DIRTY_PROG;
 270         emit.dirty = dirty;
 271
 272         fd4_clear_binning(ctx, dirty);
 273
 274         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 275         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 276
 277         /* emit generic state now: */
 278         fd4_emit_state(ctx, ring, &emit);
 279         reset_viewport(ring, pfb);
 280
 281         if (buffers & PIPE_CLEAR_DEPTH) {
 282                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 283                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 284                                 A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
 285                                 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 286
 287                 fd_wfi(ctx, ring);
 288                 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2);
 289                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 290                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth));
 291                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 292         } else {
 293                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 294                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 295         }
 296
 297         if (buffers & PIPE_CLEAR_STENCIL) {
 298                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 299                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 300                                 A4XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 301                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 302                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 303                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 304                                 0xff000000 | // XXX ???
 305                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 306
 307                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 308                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 309                                 A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 310                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 311                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 312                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 313                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 314                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 315                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 316                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 317                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER);
 318         } else {
 319                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 320                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 321                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 322                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 323                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 324                                 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 325                                 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 326
 327                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 328                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 329                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 330                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 331                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 332                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 333                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 334                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 335                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 336                 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 337         }
 338
 339         if (buffers & PIPE_CLEAR_COLOR) {
 340                 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
 341                 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
 342         }
 343
 344         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 345                 mrt_comp[i] = (buffers & (PIPE_CLEAR_COLOR0 << i)) ? 0xf : 0x0;
 346
 347                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 348                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 349                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 350
 351                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 352                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 353                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 354                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 355                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 356                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 357                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 358         }
 359
 360         OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
 361         OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 362                         A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 363                         A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 364                         A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 365                         A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 366                         A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 367                         A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 368                         A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 369
 370         fd4_emit_vertex_bufs(ring, &emit);
 371
 372         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 373         OUT_RING(ring, 0x0);          /* XXX GRAS_ALPHA_CONTROL */
 374
 375         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 376         OUT_RING(ring, 0x00000000);
 377
 378         /* until fastclear works: */
 379         fd4_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL);
 380
 381         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 382         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 383         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 384
 385         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
 386         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 387
 388         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 389         OUT_RING(ring, 0x00000001);
 390
 391         fd4_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 392                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 393
 394         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 395         OUT_RING(ring, 0x00000000);
 396
 397         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 398         OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
 399
 400         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 401         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 402                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 403                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 404                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 405 }
 406
 407 void
 408 fd4_draw_init(struct pipe_context *pctx)
 409 {
 410         struct fd_context *ctx = fd_context(pctx);
 411         ctx->draw_vbo = fd4_draw_vbo;
 412         ctx->clear = fd4_clear;
 413 }