1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_prim.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
38 #include "fd4_context.h"
40 #include "fd4_program.h"
46 draw_impl(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
47 struct fd4_emit
*emit
)
49 const struct pipe_draw_info
*info
= emit
->info
;
51 fd4_emit_state(ctx
, ring
, emit
);
53 if (emit
->dirty
& (FD_DIRTY_VTXBUF
| FD_DIRTY_VTXSTATE
))
54 fd4_emit_vertex_bufs(ring
, emit
);
56 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
57 OUT_RING(ring
, info
->start
); /* VFD_INDEX_OFFSET */
58 OUT_RING(ring
, info
->start_instance
); /* ??? UNKNOWN_2209 */
60 OUT_PKT0(ring
, REG_A4XX_PC_RESTART_INDEX
, 1);
61 OUT_RING(ring
, info
->primitive_restart
? /* PC_RESTART_INDEX */
62 info
->restart_index
: 0xffffffff);
64 fd4_draw_emit(ctx
, ring
,
65 emit
->key
.binning_pass
? IGNORE_VISIBILITY
: USE_VISIBILITY
,
69 /* fixup dirty shader state in case some "unrelated" (from the state-
70 * tracker's perspective) state change causes us to switch to a
74 fixup_shader_state(struct fd_context
*ctx
, struct ir3_shader_key
*key
)
76 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
77 struct ir3_shader_key
*last_key
= &fd4_ctx
->last_key
;
79 if (!ir3_shader_key_equal(last_key
, key
)) {
80 ctx
->dirty
|= FD_DIRTY_PROG
;
82 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
83 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
84 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
85 (last_key
->vsaturate_r
!= key
->vsaturate_r
))
86 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_VP
;
88 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
89 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
90 (last_key
->fsaturate_r
!= key
->fsaturate_r
))
91 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
94 if (last_key
->color_two_side
!= key
->color_two_side
)
95 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
97 if (last_key
->half_precision
!= key
->half_precision
)
98 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
100 if (last_key
->alpha
!= key
->alpha
)
101 ctx
->prog
.dirty
|= FD_SHADER_DIRTY_FP
;
103 fd4_ctx
->last_key
= *key
;
108 fd4_draw_vbo(struct fd_context
*ctx
, const struct pipe_draw_info
*info
)
110 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
111 struct fd4_emit emit
= {
116 /* do binning pass first: */
117 .binning_pass
= true,
118 .color_two_side
= ctx
->rasterizer
? ctx
->rasterizer
->light_twoside
: false,
119 .alpha
= util_format_is_alpha(pipe_surface_format(ctx
->framebuffer
.cbufs
[0])),
120 // TODO set .half_precision based on render target format,
121 // ie. float16 and smaller use half, float32 use full..
122 .half_precision
= !!(fd_mesa_debug
& FD_DBG_FRAGHALF
),
123 .has_per_samp
= fd4_ctx
->fsaturate
|| fd4_ctx
->vsaturate
,
124 .vsaturate_s
= fd4_ctx
->vsaturate_s
,
125 .vsaturate_t
= fd4_ctx
->vsaturate_t
,
126 .vsaturate_r
= fd4_ctx
->vsaturate_r
,
127 .fsaturate_s
= fd4_ctx
->fsaturate_s
,
128 .fsaturate_t
= fd4_ctx
->fsaturate_t
,
129 .fsaturate_r
= fd4_ctx
->fsaturate_r
,
131 .rasterflat
= ctx
->rasterizer
&& ctx
->rasterizer
->flatshade
,
135 fixup_shader_state(ctx
, &emit
.key
);
138 emit
.dirty
= dirty
& ~(FD_DIRTY_BLEND
);
139 draw_impl(ctx
, ctx
->binning_ring
, &emit
);
141 /* and now regular (non-binning) pass: */
142 emit
.key
.binning_pass
= false;
144 emit
.vp
= NULL
; /* we changed key so need to refetch vp */
145 draw_impl(ctx
, ctx
->ring
, &emit
);
148 /* clear operations ignore viewport state, so we need to reset it
149 * based on framebuffer state:
152 reset_viewport(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
)
154 float half_width
= pfb
->width
* 0.5f
;
155 float half_height
= pfb
->height
* 0.5f
;
157 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 4);
158 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width
));
159 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width
));
160 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height
));
161 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height
));
165 fd4_clear(struct fd_context
*ctx
, unsigned buffers
,
166 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
168 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
169 struct fd_ringbuffer
*ring
= ctx
->ring
;
170 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
171 unsigned dirty
= ctx
->dirty
;
173 struct fd4_emit emit
= {
174 .vtx
= &fd4_ctx
->solid_vbuf_state
,
175 .prog
= &ctx
->solid_prog
,
177 .half_precision
= true,
182 if ((buffers
& PIPE_CLEAR_COLOR
) && pfb
->nr_cbufs
)
183 colr
= pack_rgba(pfb
->cbufs
[0]->format
, color
->f
);
185 dirty
&= FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_SCISSOR
;
186 dirty
|= FD_DIRTY_PROG
;
189 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 1);
190 OUT_RING(ring
, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
192 /* emit generic state now: */
193 fd4_emit_state(ctx
, ring
, &emit
);
194 reset_viewport(ring
, pfb
);
196 if (buffers
& PIPE_CLEAR_DEPTH
) {
197 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
198 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
199 A4XX_RB_DEPTH_CONTROL_Z_ENABLE
|
200 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
));
203 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0
, 2);
204 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
205 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth
));
206 ctx
->dirty
|= FD_DIRTY_VIEWPORT
;
208 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
209 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
212 if (buffers
& PIPE_CLEAR_STENCIL
) {
213 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
214 OUT_RING(ring
, A4XX_RB_STENCILREFMASK_STENCILREF(stencil
) |
215 A4XX_RB_STENCILREFMASK_STENCILMASK(stencil
) |
216 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
217 OUT_RING(ring
, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
218 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
219 0xff000000 | // XXX ???
220 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
222 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
223 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE
|
224 A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
225 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
226 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE
) |
227 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
228 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
229 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
230 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
231 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
232 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_CONTROL2 */
234 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
235 OUT_RING(ring
, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
236 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
237 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
238 OUT_RING(ring
, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
239 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
240 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
242 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
243 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
244 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
245 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
246 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
247 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
248 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
249 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
250 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
251 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_CONTROL2 */
254 if (buffers
& PIPE_CLEAR_COLOR
) {
255 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
256 OUT_RING(ring
, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER
));
262 for (i
= 0; i
< 8; i
++) {
263 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
264 OUT_RING(ring
, A4XX_RB_MRT_CONTROL_FASTCLEAR
|
265 A4XX_RB_MRT_CONTROL_B11
|
266 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce
));
268 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
269 OUT_RING(ring
, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
270 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
271 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
272 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
273 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
274 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
));
277 fd4_emit_vertex_bufs(ring
, &emit
);
279 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
280 OUT_RING(ring
, 0x0); /* XXX GRAS_ALPHA_CONTROL */
282 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
283 OUT_RING(ring
, 0x00000000);
285 OUT_PKT0(ring
, REG_A4XX_RB_CLEAR_COLOR_DW0
, 4);
286 OUT_RING(ring
, colr
); /* RB_CLEAR_COLOR_DW0 */
287 OUT_RING(ring
, colr
); /* RB_CLEAR_COLOR_DW1 */
288 OUT_RING(ring
, colr
); /* RB_CLEAR_COLOR_DW2 */
289 OUT_RING(ring
, colr
); /* RB_CLEAR_COLOR_DW3 */
291 /* until fastclear works: */
292 fd4_emit_constant(ring
, SB_FRAG_SHADER
, 0, 0, 4, color
->ui
, NULL
);
294 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
295 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
296 OUT_RING(ring
, 0); /* ??? UNKNOWN_2209 */
298 OUT_PKT0(ring
, REG_A4XX_PC_RESTART_INDEX
, 1);
299 OUT_RING(ring
, 0xffffffff); /* PC_RESTART_INDEX */
301 OUT_PKT3(ring
, CP_UNKNOWN_1A
, 1);
302 OUT_RING(ring
, 0x00000001);
304 fd4_draw(ctx
, ring
, DI_PT_RECTLIST
, USE_VISIBILITY
,
305 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
307 OUT_PKT3(ring
, CP_UNKNOWN_1A
, 1);
308 OUT_RING(ring
, 0x00000000);
310 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
311 OUT_RING(ring
, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR
);
313 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
314 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
315 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
316 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
317 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
321 fd4_draw_init(struct pipe_context
*pctx
)
323 struct fd_context
*ctx
= fd_context(pctx
);
324 ctx
->draw_vbo
= fd4_draw_vbo
;
325 ctx
->clear
= fd4_clear
;