src/gallium/drivers/freedreno/a4xx/fd4_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd4_draw.h"
  38 #include "fd4_context.h"
  39 #include "fd4_emit.h"
  40 #include "fd4_program.h"
  41 #include "fd4_format.h"
  42 #include "fd4_zsa.h"
  43
  44
  45 static void
  46 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  47                 struct fd4_emit *emit)
  48 {
  49         const struct pipe_draw_info *info = emit->info;
  50         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  51
  52         if (!(fd4_emit_get_vp(emit) && fd4_emit_get_fp(emit)))
  53                 return;
  54
  55         fd4_emit_state(ctx, ring, emit);
  56
  57         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  58                 fd4_emit_vertex_bufs(ring, emit);
  59
  60         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
  61         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  62         OUT_RING(ring, info->start_instance);   /* ??? UNKNOWN_2209 */
  63
  64         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
  65         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  66                         info->restart_index : 0xffffffff);
  67
  68         /* points + psize -> spritelist: */
  69         if (ctx->rasterizer->point_size_per_vertex &&
  70                         fd4_emit_get_vp(emit)->writes_psize &&
  71                         (info->mode == PIPE_PRIM_POINTS))
  72                 primtype = DI_PT_POINTLIST_PSIZE;
  73
  74         fd4_draw_emit(ctx, ring,
  75                         primtype,
  76                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  77                         info);
  78 }
  79
  80 /* fixup dirty shader state in case some "unrelated" (from the state-
  81  * tracker's perspective) state change causes us to switch to a
  82  * different variant.
  83  */
  84 static void
  85 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  86 {
  87         struct fd4_context *fd4_ctx = fd4_context(ctx);
  88         struct ir3_shader_key *last_key = &fd4_ctx->last_key;
  89
  90         if (!ir3_shader_key_equal(last_key, key)) {
  91                 ctx->dirty |= FD_DIRTY_PROG;
  92
  93                 if (last_key->has_per_samp || key->has_per_samp) {
  94                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
  95                                         (last_key->vsaturate_t != key->vsaturate_t) ||
  96                                         (last_key->vsaturate_r != key->vsaturate_r) ||
  97                                         (last_key->vlower_srgb != key->vlower_srgb))
  98                                 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
  99
 100                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
 101                                         (last_key->fsaturate_t != key->fsaturate_t) ||
 102                                         (last_key->fsaturate_r != key->fsaturate_r) ||
 103                                         (last_key->flower_srgb != key->flower_srgb))
 104                                 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 105                 }
 106
 107                 if (last_key->color_two_side != key->color_two_side)
 108                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 109
 110                 if (last_key->half_precision != key->half_precision)
 111                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 112
 113                 if (last_key->rasterflat != key->rasterflat)
 114                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 115
 116                 fd4_ctx->last_key = *key;
 117         }
 118 }
 119
 120 static void
 121 fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 122 {
 123         struct fd4_context *fd4_ctx = fd4_context(ctx);
 124         struct fd4_emit emit = {
 125                 .vtx  = &ctx->vtx,
 126                 .prog = &ctx->prog,
 127                 .info = info,
 128                 .key = {
 129                         /* do binning pass first: */
 130                         .binning_pass = true,
 131                         .color_two_side = ctx->rasterizer->light_twoside,
 132                         .rasterflat = ctx->rasterizer->flatshade,
 133                         // TODO set .half_precision based on render target format,
 134                         // ie. float16 and smaller use half, float32 use full..
 135                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 136                         .ucp_enables = ctx->rasterizer->clip_plane_enable,
 137                         .has_per_samp = (fd4_ctx->fsaturate || fd4_ctx->vsaturate ||
 138                                         fd4_ctx->flower_srgb || fd4_ctx->vlower_srgb),
 139                         .vsaturate_s = fd4_ctx->vsaturate_s,
 140                         .vsaturate_t = fd4_ctx->vsaturate_t,
 141                         .vsaturate_r = fd4_ctx->vsaturate_r,
 142                         .fsaturate_s = fd4_ctx->fsaturate_s,
 143                         .fsaturate_t = fd4_ctx->fsaturate_t,
 144                         .fsaturate_r = fd4_ctx->fsaturate_r,
 145                         .vlower_srgb = fd4_ctx->vlower_srgb,
 146                         .flower_srgb = fd4_ctx->flower_srgb,
 147                 },
 148                 .rasterflat = ctx->rasterizer->flatshade,
 149                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 150                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 151         };
 152         unsigned dirty;
 153
 154         fixup_shader_state(ctx, &emit.key);
 155
 156         dirty = ctx->dirty;
 157         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 158         draw_impl(ctx, ctx->binning_ring, &emit);
 159
 160         /* and now regular (non-binning) pass: */
 161         emit.key.binning_pass = false;
 162         emit.dirty = dirty;
 163         emit.vp = NULL;   /* we changed key so need to refetch vp */
 164         emit.fp = NULL;
 165
 166         if (ctx->rasterizer->rasterizer_discard) {
 167                 fd_wfi(ctx, ctx->ring);
 168                 OUT_PKT3(ctx->ring, CP_REG_RMW, 3);
 169                 OUT_RING(ctx->ring, REG_A4XX_RB_RENDER_CONTROL);
 170                 OUT_RING(ctx->ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 171                 OUT_RING(ctx->ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 172         }
 173
 174         draw_impl(ctx, ctx->ring, &emit);
 175
 176         if (ctx->rasterizer->rasterizer_discard) {
 177                 fd_wfi(ctx, ctx->ring);
 178                 OUT_PKT3(ctx->ring, CP_REG_RMW, 3);
 179                 OUT_RING(ctx->ring, REG_A4XX_RB_RENDER_CONTROL);
 180                 OUT_RING(ctx->ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 181                 OUT_RING(ctx->ring, 0);
 182         }
 183 }
 184
 185 /* clear operations ignore viewport state, so we need to reset it
 186  * based on framebuffer state:
 187  */
 188 static void
 189 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 190 {
 191         float half_width = pfb->width * 0.5f;
 192         float half_height = pfb->height * 0.5f;
 193
 194         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 4);
 195         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width));
 196         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width));
 197         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height));
 198         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height));
 199 }
 200
 201 /* TODO maybe we should just migrate u_blitter for clear and do it in
 202  * core (so we get normal draw pass state mgmt and binning).. That should
 203  * work well enough for a3xx/a4xx (but maybe not a2xx?)
 204  */
 205
 206 static void
 207 fd4_clear_binning(struct fd_context *ctx, unsigned dirty)
 208 {
 209         struct fd4_context *fd4_ctx = fd4_context(ctx);
 210         struct fd_ringbuffer *ring = ctx->binning_ring;
 211         struct fd4_emit emit = {
 212                 .vtx  = &fd4_ctx->solid_vbuf_state,
 213                 .prog = &ctx->solid_prog,
 214                 .key = {
 215                         .binning_pass = true,
 216                         .half_precision = true,
 217                 },
 218                 .dirty = dirty,
 219         };
 220
 221         fd4_emit_state(ctx, ring, &emit);
 222         fd4_emit_vertex_bufs(ring, &emit);
 223         reset_viewport(ring, &ctx->framebuffer);
 224
 225         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
 226         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_VAROUT(0) |
 227                         A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 228         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
 229                         A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES));
 230
 231         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 232         OUT_RING(ring, 0x00000002);
 233
 234         fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 235                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 236 }
 237
 238 static void
 239 fd4_clear(struct fd_context *ctx, unsigned buffers,
 240                 const union pipe_color_union *color, double depth, unsigned stencil)
 241 {
 242         struct fd4_context *fd4_ctx = fd4_context(ctx);
 243         struct fd_ringbuffer *ring = ctx->ring;
 244         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 245         unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 246         unsigned dirty = ctx->dirty;
 247         unsigned i;
 248         struct fd4_emit emit = {
 249                 .vtx  = &fd4_ctx->solid_vbuf_state,
 250                 .prog = &ctx->solid_prog,
 251                 .key = {
 252                         .half_precision = fd_half_precision(pfb),
 253                 },
 254         };
 255
 256         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 257         dirty |= FD_DIRTY_PROG;
 258         emit.dirty = dirty;
 259
 260         fd4_clear_binning(ctx, dirty);
 261
 262         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 263         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 264
 265         /* emit generic state now: */
 266         fd4_emit_state(ctx, ring, &emit);
 267         reset_viewport(ring, pfb);
 268
 269         if (buffers & PIPE_CLEAR_DEPTH) {
 270                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 271                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 272                                 A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
 273                                 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 274
 275                 fd_wfi(ctx, ring);
 276                 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2);
 277                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 278                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth));
 279                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 280         } else {
 281                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 282                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 283         }
 284
 285         if (buffers & PIPE_CLEAR_STENCIL) {
 286                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 287                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 288                                 A4XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 289                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 290                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 291                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 292                                 0xff000000 | // XXX ???
 293                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 294
 295                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 296                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 297                                 A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 298                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 299                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 300                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 301                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 302                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 303                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 304                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 305                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER);
 306         } else {
 307                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 308                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 309                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 310                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 311                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 312                                 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 313                                 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 314
 315                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 316                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 317                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 318                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 319                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 320                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 321                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 322                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 323                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 324                 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 325         }
 326
 327         if (buffers & PIPE_CLEAR_COLOR) {
 328                 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
 329                 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
 330         }
 331
 332         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 333                 mrt_comp[i] = (buffers & (PIPE_CLEAR_COLOR0 << i)) ? 0xf : 0x0;
 334
 335                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 336                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 337                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 338
 339                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 340                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 341                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 342                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 343                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 344                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 345                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 346         }
 347
 348         OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
 349         OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 350                         A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 351                         A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 352                         A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 353                         A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 354                         A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 355                         A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 356                         A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 357
 358         fd4_emit_vertex_bufs(ring, &emit);
 359
 360         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 361         OUT_RING(ring, 0x0);          /* XXX GRAS_ALPHA_CONTROL */
 362
 363         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 364         OUT_RING(ring, 0x00000000);
 365
 366         /* until fastclear works: */
 367         fd4_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL);
 368
 369         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 370         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 371         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 372
 373         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
 374         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 375
 376         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 377         OUT_RING(ring, 0x00000001);
 378
 379         fd4_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 380                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 381
 382         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 383         OUT_RING(ring, 0x00000000);
 384
 385         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 386         OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
 387
 388         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 389         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 390                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 391                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 392                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 393 }
 394
 395 void
 396 fd4_draw_init(struct pipe_context *pctx)
 397 {
 398         struct fd_context *ctx = fd_context(pctx);
 399         ctx->draw_vbo = fd4_draw_vbo;
 400         ctx->clear = fd4_clear;
 401 }