src/gallium/drivers/freedreno/a4xx/fd4_draw.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_prim.h"
  33
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd4_draw.h"
  38 #include "fd4_context.h"
  39 #include "fd4_emit.h"
  40 #include "fd4_program.h"
  41 #include "fd4_format.h"
  42 #include "fd4_zsa.h"
  43
  44
  45 static void
  46 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  47                 struct fd4_emit *emit)
  48 {
  49         const struct pipe_draw_info *info = emit->info;
  50
  51         fd4_emit_state(ctx, ring, emit);
  52
  53         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  54                 fd4_emit_vertex_bufs(ring, emit);
  55
  56         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
  57         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  58         OUT_RING(ring, info->start_instance);   /* ??? UNKNOWN_2209 */
  59
  60         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
  61         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  62                         info->restart_index : 0xffffffff);
  63
  64         fd4_draw_emit(ctx, ring,
  65                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  66                         info);
  67 }
  68
  69 /* fixup dirty shader state in case some "unrelated" (from the state-
  70  * tracker's perspective) state change causes us to switch to a
  71  * different variant.
  72  */
  73 static void
  74 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  75 {
  76         struct fd4_context *fd4_ctx = fd4_context(ctx);
  77         struct ir3_shader_key *last_key = &fd4_ctx->last_key;
  78
  79         if (!ir3_shader_key_equal(last_key, key)) {
  80                 ctx->dirty |= FD_DIRTY_PROG;
  81
  82                 if (last_key->has_per_samp || key->has_per_samp) {
  83                         if ((last_key->vsaturate_s != key->vsaturate_s) ||
  84                                         (last_key->vsaturate_t != key->vsaturate_t) ||
  85                                         (last_key->vsaturate_r != key->vsaturate_r))
  86                                 ctx->prog.dirty |= FD_SHADER_DIRTY_VP;
  87
  88                         if ((last_key->fsaturate_s != key->fsaturate_s) ||
  89                                         (last_key->fsaturate_t != key->fsaturate_t) ||
  90                                         (last_key->fsaturate_r != key->fsaturate_r))
  91                                 ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
  92                 }
  93
  94                 if (last_key->color_two_side != key->color_two_side)
  95                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
  96
  97                 if (last_key->half_precision != key->half_precision)
  98                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
  99
 100                 if (last_key->alpha != key->alpha)
 101                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 102
 103                 if (last_key->rasterflat != key->rasterflat)
 104                         ctx->prog.dirty |= FD_SHADER_DIRTY_FP;
 105
 106                 fd4_ctx->last_key = *key;
 107         }
 108 }
 109
 110 static void
 111 fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 112 {
 113         struct fd4_context *fd4_ctx = fd4_context(ctx);
 114         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 115         struct fd4_emit emit = {
 116                 .vtx  = &ctx->vtx,
 117                 .prog = &ctx->prog,
 118                 .info = info,
 119                 .key = {
 120                         /* do binning pass first: */
 121                         .binning_pass = true,
 122                         .color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false,
 123                         .alpha = util_format_is_alpha(pipe_surface_format(pfb->cbufs[0])),
 124                         .rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade,
 125                         // TODO set .half_precision based on render target format,
 126                         // ie. float16 and smaller use half, float32 use full..
 127                         .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
 128                         .has_per_samp = fd4_ctx->fsaturate || fd4_ctx->vsaturate,
 129                         .vsaturate_s = fd4_ctx->vsaturate_s,
 130                         .vsaturate_t = fd4_ctx->vsaturate_t,
 131                         .vsaturate_r = fd4_ctx->vsaturate_r,
 132                         .fsaturate_s = fd4_ctx->fsaturate_s,
 133                         .fsaturate_t = fd4_ctx->fsaturate_t,
 134                         .fsaturate_r = fd4_ctx->fsaturate_r,
 135                 },
 136                 .format = fd4_emit_format(pfb->cbufs[0]),
 137         };
 138         unsigned dirty;
 139
 140         fixup_shader_state(ctx, &emit.key);
 141
 142         dirty = ctx->dirty;
 143         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 144         draw_impl(ctx, ctx->binning_ring, &emit);
 145
 146         /* and now regular (non-binning) pass: */
 147         emit.key.binning_pass = false;
 148         emit.dirty = dirty;
 149         emit.vp = NULL;   /* we changed key so need to refetch vp */
 150         draw_impl(ctx, ctx->ring, &emit);
 151 }
 152
 153 /* clear operations ignore viewport state, so we need to reset it
 154  * based on framebuffer state:
 155  */
 156 static void
 157 reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
 158 {
 159         float half_width = pfb->width * 0.5f;
 160         float half_height = pfb->height * 0.5f;
 161
 162         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 4);
 163         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width));
 164         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width));
 165         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height));
 166         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height));
 167 }
 168
 169 static void
 170 fd4_clear(struct fd_context *ctx, unsigned buffers,
 171                 const union pipe_color_union *color, double depth, unsigned stencil)
 172 {
 173         struct fd4_context *fd4_ctx = fd4_context(ctx);
 174         struct fd_ringbuffer *ring = ctx->ring;
 175         struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
 176         unsigned dirty = ctx->dirty;
 177         unsigned ce, i;
 178         struct fd4_emit emit = {
 179                 .vtx  = &fd4_ctx->solid_vbuf_state,
 180                 .prog = &ctx->solid_prog,
 181                 .key = {
 182                         .half_precision = true,
 183                 },
 184                 .format = fd4_emit_format(pfb->cbufs[0]),
 185         };
 186         uint32_t colr = 0;
 187
 188         if ((buffers & PIPE_CLEAR_COLOR) && pfb->nr_cbufs)
 189                 colr  = pack_rgba(pfb->cbufs[0]->format, color->f);
 190
 191         dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
 192         dirty |= FD_DIRTY_PROG;
 193         emit.dirty = dirty;
 194
 195         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 196         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 197
 198         /* emit generic state now: */
 199         fd4_emit_state(ctx, ring, &emit);
 200         reset_viewport(ring, pfb);
 201
 202         if (buffers & PIPE_CLEAR_DEPTH) {
 203                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 204                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 205                                 A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
 206                                 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
 207
 208                 fd_wfi(ctx, ring);
 209                 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2);
 210                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 211                 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth));
 212                 ctx->dirty |= FD_DIRTY_VIEWPORT;
 213         } else {
 214                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 215                 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 216         }
 217
 218         if (buffers & PIPE_CLEAR_STENCIL) {
 219                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 220                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(stencil) |
 221                                 A4XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
 222                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 223                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 224                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 225                                 0xff000000 | // XXX ???
 226                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 227
 228                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 229                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 230                                 A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 231                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 232                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
 233                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 234                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 235                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 236                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 237                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 238                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER);
 239         } else {
 240                 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 241                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 242                                 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 243                                 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
 244                 OUT_RING(ring, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 245                                 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 246                                 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
 247
 248                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 249                 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 250                                 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 251                                 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 252                                 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 253                                 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 254                                 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 255                                 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 256                                 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 257                 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 258         }
 259
 260         if (buffers & PIPE_CLEAR_COLOR) {
 261                 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
 262                 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
 263                 ce = 0xf;
 264         } else {
 265                 ce = 0x0;
 266         }
 267
 268         for (i = 0; i < 8; i++) {
 269                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 270                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR |
 271                                 A4XX_RB_MRT_CONTROL_B11 |
 272                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce));
 273
 274                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 275                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 276                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 277                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 278                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 279                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 280                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 281         }
 282
 283         fd4_emit_vertex_bufs(ring, &emit);
 284
 285         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 286         OUT_RING(ring, 0x0);          /* XXX GRAS_ALPHA_CONTROL */
 287
 288         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 289         OUT_RING(ring, 0x00000000);
 290
 291         OUT_PKT0(ring, REG_A4XX_RB_CLEAR_COLOR_DW0, 4);
 292         OUT_RING(ring, colr);         /* RB_CLEAR_COLOR_DW0 */
 293         OUT_RING(ring, colr);         /* RB_CLEAR_COLOR_DW1 */
 294         OUT_RING(ring, colr);         /* RB_CLEAR_COLOR_DW2 */
 295         OUT_RING(ring, colr);         /* RB_CLEAR_COLOR_DW3 */
 296
 297         /* until fastclear works: */
 298         fd4_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL);
 299
 300         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 301         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 302         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 303
 304         OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
 305         OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
 306
 307         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 308         OUT_RING(ring, 0x00000001);
 309
 310         fd4_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
 311                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
 312
 313         OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
 314         OUT_RING(ring, 0x00000000);
 315
 316         OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
 317         OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
 318
 319         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 320         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 321                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 322                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 323                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 324 }
 325
 326 void
 327 fd4_draw_init(struct pipe_context *pctx)
 328 {
 329         struct fd_context *ctx = fd_context(pctx);
 330         ctx->draw_vbo = fd4_draw_vbo;
 331         ctx->clear = fd4_clear;
 332 }