1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
39 #include "fd4_blend.h"
40 #include "fd4_context.h"
41 #include "fd4_program.h"
42 #include "fd4_rasterizer.h"
43 #include "fd4_texture.h"
44 #include "fd4_format.h"
47 static const enum adreno_state_block sb
[] = {
48 [SHADER_VERTEX
] = SB_VERT_SHADER
,
49 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
52 /* regid: base const register
53 * prsc or dwords: buffer containing constant values
54 * sizedwords: size of const value buffer
57 fd4_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
58 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
59 const uint32_t *dwords
, struct pipe_resource
*prsc
)
62 enum adreno_state_src src
;
64 debug_assert((regid
% 4) == 0);
65 debug_assert((sizedwords
% 4) == 0);
75 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
76 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
77 CP_LOAD_STATE_0_STATE_SRC(src
) |
78 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
79 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/4));
81 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
82 OUT_RELOC(ring
, bo
, offset
,
83 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
85 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
86 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
87 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
89 for (i
= 0; i
< sz
; i
++) {
90 OUT_RING(ring
, dwords
[i
]);
95 fd4_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
96 uint32_t regid
, uint32_t num
, struct fd_bo
**bos
, uint32_t *offsets
)
100 debug_assert((regid
% 4) == 0);
101 debug_assert((num
% 4) == 0);
103 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + num
);
104 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
107 CP_LOAD_STATE_0_NUM_UNIT(num
/4));
108 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
111 for (i
= 0; i
< num
; i
++) {
114 OUT_RELOCW(ring
, bos
[i
], offsets
[i
], 0, 0);
116 OUT_RELOC(ring
, bos
[i
], offsets
[i
], 0, 0);
119 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
125 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
126 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
,
127 const struct ir3_shader_variant
*v
)
129 static const uint32_t bcolor_reg
[] = {
130 [SB_VERT_TEX
] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
131 [SB_FRAG_TEX
] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
133 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
137 u_upload_alloc(fd4_ctx
->border_color_uploader
,
138 0, BORDER_COLOR_UPLOAD_SIZE
,
139 BORDER_COLOR_UPLOAD_SIZE
, &off
,
140 &fd4_ctx
->border_color_buf
,
143 fd_setup_border_colors(tex
, ptr
, 0);
145 if (tex
->num_samplers
> 0) {
148 /* not sure if this is an a420.0 workaround, but we seem
149 * to need to emit these in pairs.. emit a final dummy
150 * entry if odd # of samplers:
152 num_samplers
= align(tex
->num_samplers
, 2);
154 /* output sampler state: */
155 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * num_samplers
));
156 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
157 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
158 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
159 CP_LOAD_STATE_0_NUM_UNIT(num_samplers
));
160 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
161 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
162 for (i
= 0; i
< tex
->num_samplers
; i
++) {
163 static const struct fd4_sampler_stateobj dummy_sampler
= {};
164 const struct fd4_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
165 fd4_sampler_stateobj(tex
->samplers
[i
]) :
167 OUT_RING(ring
, sampler
->texsamp0
);
168 OUT_RING(ring
, sampler
->texsamp1
);
171 for (; i
< num_samplers
; i
++) {
172 OUT_RING(ring
, 0x00000000);
173 OUT_RING(ring
, 0x00000000);
177 if (tex
->num_textures
> 0) {
178 unsigned num_textures
= tex
->num_textures
+ v
->astc_srgb
.count
;
180 /* emit texture state: */
181 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (8 * num_textures
));
182 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
183 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
184 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
185 CP_LOAD_STATE_0_NUM_UNIT(num_textures
));
186 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
187 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
188 for (i
= 0; i
< tex
->num_textures
; i
++) {
189 static const struct fd4_pipe_sampler_view dummy_view
= {};
190 const struct fd4_pipe_sampler_view
*view
= tex
->textures
[i
] ?
191 fd4_pipe_sampler_view(tex
->textures
[i
]) :
194 OUT_RING(ring
, view
->texconst0
);
195 OUT_RING(ring
, view
->texconst1
);
196 OUT_RING(ring
, view
->texconst2
);
197 OUT_RING(ring
, view
->texconst3
);
198 if (view
->base
.texture
) {
199 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
200 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
202 OUT_RING(ring
, 0x00000000);
204 OUT_RING(ring
, 0x00000000);
205 OUT_RING(ring
, 0x00000000);
206 OUT_RING(ring
, 0x00000000);
209 for (i
= 0; i
< v
->astc_srgb
.count
; i
++) {
210 static const struct fd4_pipe_sampler_view dummy_view
= {};
211 const struct fd4_pipe_sampler_view
*view
;
212 unsigned idx
= v
->astc_srgb
.orig_idx
[i
];
214 view
= tex
->textures
[idx
] ?
215 fd4_pipe_sampler_view(tex
->textures
[idx
]) :
218 debug_assert(view
->texconst0
& A4XX_TEX_CONST_0_SRGB
);
220 OUT_RING(ring
, view
->texconst0
& ~A4XX_TEX_CONST_0_SRGB
);
221 OUT_RING(ring
, view
->texconst1
);
222 OUT_RING(ring
, view
->texconst2
);
223 OUT_RING(ring
, view
->texconst3
);
224 if (view
->base
.texture
) {
225 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
226 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
228 OUT_RING(ring
, 0x00000000);
230 OUT_RING(ring
, 0x00000000);
231 OUT_RING(ring
, 0x00000000);
232 OUT_RING(ring
, 0x00000000);
235 debug_assert(v
->astc_srgb
.count
== 0);
238 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
239 OUT_RELOC(ring
, fd_resource(fd4_ctx
->border_color_buf
)->bo
, off
, 0, 0);
241 u_upload_unmap(fd4_ctx
->border_color_uploader
);
244 /* emit texture state for mem->gmem restore operation.. eventually it would
245 * be good to get rid of this and use normal CSO/etc state for more of these
249 fd4_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
250 struct pipe_surface
**bufs
)
252 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
];
255 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
256 mrt_comp
[i
] = (i
< nr_bufs
) ? 0xf : 0;
259 /* output sampler state: */
260 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * nr_bufs
));
261 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
262 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
263 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
264 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs
));
265 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
266 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
267 for (i
= 0; i
< nr_bufs
; i
++) {
268 OUT_RING(ring
, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST
) |
269 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST
) |
270 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE
) |
271 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE
) |
272 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT
));
273 OUT_RING(ring
, 0x00000000);
276 /* emit texture state: */
277 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (8 * nr_bufs
));
278 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
279 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
280 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
281 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs
));
282 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
283 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
284 for (i
= 0; i
< nr_bufs
; i
++) {
286 struct fd_resource
*rsc
= fd_resource(bufs
[i
]->texture
);
287 /* note: PIPE_BUFFER disallowed for surfaces */
288 unsigned lvl
= bufs
[i
]->u
.tex
.level
;
289 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
290 uint32_t offset
= fd_resource_offset(rsc
, lvl
, bufs
[i
]->u
.tex
.first_layer
);
291 enum pipe_format format
= fd4_gmem_restore_format(bufs
[i
]->format
);
293 /* The restore blit_zs shader expects stencil in sampler 0,
294 * and depth in sampler 1
296 if (rsc
->stencil
&& (i
== 0)) {
298 format
= fd4_gmem_restore_format(rsc
->base
.b
.format
);
301 /* z32 restore is accomplished using depth write. If there is
302 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
303 * then no render target:
305 * (The same applies for z32_s8x24, since for stencil sampler
306 * state the above 'if' will replace 'format' with s8)
308 if ((format
== PIPE_FORMAT_Z32_FLOAT
) ||
309 (format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
))
312 debug_assert(bufs
[i
]->u
.tex
.first_layer
== bufs
[i
]->u
.tex
.last_layer
);
314 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format
)) |
315 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
316 fd4_tex_swiz(format
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
,
317 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_W
));
318 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(bufs
[i
]->width
) |
319 A4XX_TEX_CONST_1_HEIGHT(bufs
[i
]->height
));
320 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
) |
321 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format
)));
322 OUT_RING(ring
, 0x00000000);
323 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
324 OUT_RING(ring
, 0x00000000);
325 OUT_RING(ring
, 0x00000000);
326 OUT_RING(ring
, 0x00000000);
328 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(0) |
329 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
330 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE
) |
331 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE
) |
332 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE
) |
333 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE
));
334 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(0) |
335 A4XX_TEX_CONST_1_HEIGHT(0));
336 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(0));
337 OUT_RING(ring
, 0x00000000);
338 OUT_RING(ring
, 0x00000000);
339 OUT_RING(ring
, 0x00000000);
340 OUT_RING(ring
, 0x00000000);
341 OUT_RING(ring
, 0x00000000);
345 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
346 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
347 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
348 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
349 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
350 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
351 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
352 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
353 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
357 fd4_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
)
359 int32_t i
, j
, last
= -1;
360 uint32_t total_in
= 0;
361 const struct fd_vertex_state
*vtx
= emit
->vtx
;
362 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
363 unsigned vertex_regid
= regid(63, 0);
364 unsigned instance_regid
= regid(63, 0);
365 unsigned vtxcnt_regid
= regid(63, 0);
367 /* Note that sysvals come *after* normal inputs: */
368 for (i
= 0; i
< vp
->inputs_count
; i
++) {
369 if (!vp
->inputs
[i
].compmask
)
371 if (vp
->inputs
[i
].sysval
) {
372 switch(vp
->inputs
[i
].slot
) {
373 case SYSTEM_VALUE_BASE_VERTEX
:
374 /* handled elsewhere */
376 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
377 vertex_regid
= vp
->inputs
[i
].regid
;
379 case SYSTEM_VALUE_INSTANCE_ID
:
380 instance_regid
= vp
->inputs
[i
].regid
;
382 case SYSTEM_VALUE_VERTEX_CNT
:
383 vtxcnt_regid
= vp
->inputs
[i
].regid
;
386 unreachable("invalid system value");
389 } else if (i
< vtx
->vtx
->num_elements
) {
394 for (i
= 0, j
= 0; i
<= last
; i
++) {
395 assert(!vp
->inputs
[i
].sysval
);
396 if (vp
->inputs
[i
].compmask
) {
397 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
398 const struct pipe_vertex_buffer
*vb
=
399 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
400 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
401 enum pipe_format pfmt
= elem
->src_format
;
402 enum a4xx_vtx_fmt fmt
= fd4_pipe2vtx(pfmt
);
403 bool switchnext
= (i
!= last
) ||
404 (vertex_regid
!= regid(63, 0)) ||
405 (instance_regid
!= regid(63, 0)) ||
406 (vtxcnt_regid
!= regid(63, 0));
407 bool isint
= util_format_is_pure_integer(pfmt
);
408 uint32_t fs
= util_format_get_blocksize(pfmt
);
409 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
410 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
411 debug_assert(fmt
!= ~0);
413 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(j
), 4);
414 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
415 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
416 COND(elem
->instance_divisor
, A4XX_VFD_FETCH_INSTR_0_INSTANCED
) |
417 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
418 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
419 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(size
));
420 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem
->instance_divisor
)));
422 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(j
), 1);
423 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
424 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
425 A4XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
426 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt
)) |
427 A4XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
428 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
429 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
430 COND(isint
, A4XX_VFD_DECODE_INSTR_INT
) |
431 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
433 total_in
+= vp
->inputs
[i
].ncomp
;
438 /* hw doesn't like to be configured for zero vbo's, it seems: */
440 /* just recycle the shader bo, we just need to point to *something*
443 struct fd_bo
*dummy_vbo
= vp
->bo
;
444 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
445 (instance_regid
!= regid(63, 0)) ||
446 (vtxcnt_regid
!= regid(63, 0));
448 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(0), 4);
449 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
450 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
451 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
452 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
453 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
454 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
456 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(0), 1);
457 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
458 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
459 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM
) |
460 A4XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
461 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
462 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
463 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
464 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
470 OUT_PKT0(ring
, REG_A4XX_VFD_CONTROL_0
, 5);
471 OUT_RING(ring
, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
473 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
474 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
475 OUT_RING(ring
, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
476 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
477 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
478 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_2 */
479 OUT_RING(ring
, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid
));
480 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_4 */
482 /* cache invalidate, otherwise vertex fetch could see
483 * stale vbo contents:
485 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
486 OUT_RING(ring
, 0x00000000);
487 OUT_RING(ring
, 0x00000012);
491 fd4_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
492 struct fd4_emit
*emit
)
494 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
495 const struct ir3_shader_variant
*fp
= fd4_emit_get_fp(emit
);
496 uint32_t dirty
= emit
->dirty
;
498 emit_marker(ring
, 5);
500 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->key
.binning_pass
) {
501 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
502 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
504 for (unsigned i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
505 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
508 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
509 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
510 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
511 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
512 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
513 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
514 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
515 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
516 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
519 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
520 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
521 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
522 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
524 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
525 rb_alpha_control
&= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
527 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
528 OUT_RING(ring
, rb_alpha_control
);
530 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
531 OUT_RING(ring
, zsa
->rb_stencil_control
);
532 OUT_RING(ring
, zsa
->rb_stencil_control2
);
535 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
536 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
537 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
539 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
540 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
541 A4XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
542 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
543 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
546 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) {
547 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
548 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
550 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
551 OUT_RING(ring
, zsa
->rb_depth_control
|
552 COND(fragz
, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
) |
553 COND(fragz
&& fp
->frag_coord
, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS
));
555 /* maybe this register/bitfield needs a better name.. this
556 * appears to be just disabling early-z
558 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
559 OUT_RING(ring
, zsa
->gras_alpha_control
|
560 COND(fragz
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
) |
561 COND(fragz
&& fp
->frag_coord
, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS
));
564 if (dirty
& FD_DIRTY_RASTERIZER
) {
565 struct fd4_rasterizer_stateobj
*rasterizer
=
566 fd4_rasterizer_stateobj(ctx
->rasterizer
);
568 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
569 OUT_RING(ring
, rasterizer
->gras_su_mode_control
|
570 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
572 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POINT_MINMAX
, 2);
573 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
574 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
576 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
577 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
578 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
580 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
581 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
584 /* NOTE: since primitive_restart is not actually part of any
585 * state object, we need to make sure that we always emit
586 * PRIM_VTX_CNTL.. either that or be more clever and detect
590 const struct pipe_draw_info
*info
= emit
->info
;
591 struct fd4_rasterizer_stateobj
*rast
=
592 fd4_rasterizer_stateobj(ctx
->rasterizer
);
593 uint32_t val
= rast
->pc_prim_vtx_cntl
;
595 if (info
->indexed
&& info
->primitive_restart
)
596 val
|= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
598 val
|= COND(vp
->writes_psize
, A4XX_PC_PRIM_VTX_CNTL_PSIZE
);
600 if (fp
->total_in
> 0) {
601 uint32_t varout
= align(fp
->total_in
, 16) / 16;
603 varout
= align(varout
, 2);
604 val
|= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout
);
607 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 2);
609 OUT_RING(ring
, rast
->pc_prim_vtx_cntl2
);
612 if (dirty
& FD_DIRTY_SCISSOR
) {
613 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
615 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
616 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
617 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
618 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
619 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
621 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
622 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
623 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
624 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
627 if (dirty
& FD_DIRTY_VIEWPORT
) {
629 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
630 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
631 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
632 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
633 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
634 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
635 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
638 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
)) {
639 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
640 unsigned n
= pfb
->nr_cbufs
;
641 /* if we have depth/stencil, we need at least on MRT: */
644 fd4_program_emit(ring
, emit
, n
, pfb
->cbufs
);
647 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
648 ir3_emit_consts(vp
, ring
, ctx
, emit
->info
, dirty
);
649 if (!emit
->key
.binning_pass
)
650 ir3_emit_consts(fp
, ring
, ctx
, emit
->info
, dirty
);
651 /* mark clean after emitting consts: */
655 if ((dirty
& FD_DIRTY_BLEND
)) {
656 struct fd4_blend_stateobj
*blend
= fd4_blend_stateobj(ctx
->blend
);
659 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
660 enum pipe_format format
= pipe_surface_format(
661 ctx
->framebuffer
.cbufs
[i
]);
662 bool is_int
= util_format_is_pure_integer(format
);
663 bool has_alpha
= util_format_has_alpha(format
);
664 uint32_t control
= blend
->rb_mrt
[i
].control
;
665 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
668 control
&= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
669 control
|= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
673 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
675 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
676 control
&= ~A4XX_RB_MRT_CONTROL_BLEND2
;
679 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
680 OUT_RING(ring
, control
);
682 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
683 OUT_RING(ring
, blend_control
);
686 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
687 OUT_RING(ring
, blend
->rb_fs_output
|
688 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
691 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
692 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
694 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 8);
695 OUT_RING(ring
, A4XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
696 A4XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
697 A4XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
698 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
699 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
700 A4XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
701 A4XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
702 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
703 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
704 A4XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
705 A4XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
706 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
707 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
708 A4XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
709 A4XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
710 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
713 if (dirty
& FD_DIRTY_VERTTEX
) {
715 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
, vp
);
717 dirty
&= ~FD_DIRTY_VERTTEX
;
720 if (dirty
& FD_DIRTY_FRAGTEX
) {
722 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
, fp
);
724 dirty
&= ~FD_DIRTY_FRAGTEX
;
727 ctx
->dirty
&= ~dirty
;
730 /* emit setup at begin of new cmdstream buffer (don't rely on previous
731 * state, there could have been a context switch between ioctls):
734 fd4_emit_restore(struct fd_context
*ctx
)
736 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
737 struct fd_ringbuffer
*ring
= ctx
->ring
;
739 OUT_PKT0(ring
, REG_A4XX_RBBM_PERFCTR_CTL
, 1);
740 OUT_RING(ring
, 0x00000001);
742 OUT_PKT0(ring
, REG_A4XX_GRAS_DEBUG_ECO_CONTROL
, 1);
743 OUT_RING(ring
, 0x00000000);
745 OUT_PKT0(ring
, REG_A4XX_SP_MODE_CONTROL
, 1);
746 OUT_RING(ring
, 0x00000006);
748 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_MODE_CONTROL
, 1);
749 OUT_RING(ring
, 0x0000003a);
751 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0D01
, 1);
752 OUT_RING(ring
, 0x00000001);
754 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0E42
, 1);
755 OUT_RING(ring
, 0x00000000);
757 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_WAYS_VFD
, 1);
758 OUT_RING(ring
, 0x00000007);
760 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_MODE_CONTROL
, 1);
761 OUT_RING(ring
, 0x00000000);
763 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
764 OUT_RING(ring
, 0x00000000);
765 OUT_RING(ring
, 0x00000012);
767 OUT_PKT0(ring
, REG_A4XX_HLSQ_MODE_CONTROL
, 1);
768 OUT_RING(ring
, 0x00000000);
770 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC5
, 1);
771 OUT_RING(ring
, 0x00000006);
773 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC6
, 1);
774 OUT_RING(ring
, 0x00000000);
776 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0EC2
, 1);
777 OUT_RING(ring
, 0x00040000);
779 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2001
, 1);
780 OUT_RING(ring
, 0x00000000);
782 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
783 OUT_RING(ring
, 0x00001000);
785 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20EF
, 1);
786 OUT_RING(ring
, 0x00000000);
788 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 4);
789 OUT_RING(ring
, A4XX_RB_BLEND_RED_UINT(0) |
790 A4XX_RB_BLEND_RED_FLOAT(0.0));
791 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_UINT(0) |
792 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
793 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_UINT(0) |
794 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
795 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
796 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
798 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2152
, 1);
799 OUT_RING(ring
, 0x00000000);
801 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2153
, 1);
802 OUT_RING(ring
, 0x00000000);
804 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2154
, 1);
805 OUT_RING(ring
, 0x00000000);
807 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2155
, 1);
808 OUT_RING(ring
, 0x00000000);
810 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2156
, 1);
811 OUT_RING(ring
, 0x00000000);
813 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2157
, 1);
814 OUT_RING(ring
, 0x00000000);
816 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21C3
, 1);
817 OUT_RING(ring
, 0x0000001d);
819 OUT_PKT0(ring
, REG_A4XX_PC_GS_PARAM
, 1);
820 OUT_RING(ring
, 0x00000000);
822 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21E6
, 1);
823 OUT_RING(ring
, 0x00000001);
825 OUT_PKT0(ring
, REG_A4XX_PC_HS_PARAM
, 1);
826 OUT_RING(ring
, 0x00000000);
828 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_22D7
, 1);
829 OUT_RING(ring
, 0x00000000);
831 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_OFFSET
, 1);
832 OUT_RING(ring
, 0x00000000);
834 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_COUNT
, 1);
835 OUT_RING(ring
, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
836 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
837 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
838 A4XX_TPL1_TP_TEX_COUNT_GS(0));
840 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_FS_TEX_COUNT
, 1);
843 /* we don't use this yet.. probably best to disable.. */
844 OUT_PKT3(ring
, CP_SET_DRAW_STATE
, 2);
845 OUT_RING(ring
, CP_SET_DRAW_STATE_0_COUNT(0) |
846 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS
|
847 CP_SET_DRAW_STATE_0_GROUP_ID(0));
848 OUT_RING(ring
, CP_SET_DRAW_STATE_1_ADDR(0));
850 OUT_PKT0(ring
, REG_A4XX_SP_VS_PVT_MEM_PARAM
, 2);
851 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
852 OUT_RELOC(ring
, fd4_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
854 OUT_PKT0(ring
, REG_A4XX_SP_FS_PVT_MEM_PARAM
, 2);
855 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
856 OUT_RELOC(ring
, fd4_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
858 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
859 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
860 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
861 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
862 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
864 OUT_PKT0(ring
, REG_A4XX_RB_MSAA_CONTROL
, 1);
865 OUT_RING(ring
, A4XX_RB_MSAA_CONTROL_DISABLE
|
866 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
));
868 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_GB_CLIP_ADJ
, 1);
869 OUT_RING(ring
, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
870 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
872 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
873 OUT_RING(ring
, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
));
875 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
876 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
878 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
879 OUT_RING(ring
, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR
);
881 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
884 fd_hw_query_enable(ctx
, ring
);
886 ctx
->needs_rb_fbd
= true;
890 fd4_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringmarker
*start
,
891 struct fd_ringmarker
*end
)
893 __OUT_IB(ring
, true, start
, end
);
897 fd4_emit_init(struct pipe_context
*pctx
)
899 struct fd_context
*ctx
= fd_context(pctx
);
900 ctx
->emit_const
= fd4_emit_const
;
901 ctx
->emit_const_bo
= fd4_emit_const_bo
;
902 ctx
->emit_ib
= fd4_emit_ib
;