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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 void
51 fd4_emit_constant(struct fd_ringbuffer *ring,
52 enum adreno_state_block sb,
53 uint32_t regid, uint32_t offset, uint32_t sizedwords,
54 const uint32_t *dwords, struct pipe_resource *prsc)
55 {
56 uint32_t i, sz;
57 enum adreno_state_src src;
58
59 if (prsc) {
60 sz = 0;
61 src = 0x2; // TODO ??
62 } else {
63 sz = sizedwords;
64 src = SS_DIRECT;
65 }
66
67 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
68 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
69 CP_LOAD_STATE_0_STATE_SRC(src) |
70 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
71 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
72 if (prsc) {
73 struct fd_bo *bo = fd_resource(prsc)->bo;
74 OUT_RELOC(ring, bo, offset,
75 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
76 } else {
77 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
78 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
79 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
80 }
81 for (i = 0; i < sz; i++) {
82 OUT_RING(ring, dwords[i]);
83 }
84 }
85
86 static void
87 emit_constants(struct fd_ringbuffer *ring,
88 enum adreno_state_block sb,
89 struct fd_constbuf_stateobj *constbuf,
90 struct ir3_shader_variant *shader)
91 {
92 uint32_t enabled_mask = constbuf->enabled_mask;
93 uint32_t first_immediate;
94 uint32_t base = 0;
95
96 // XXX TODO only emit dirty consts.. but we need to keep track if
97 // they are clobbered by a clear, gmem2mem, or mem2gmem..
98 constbuf->dirty_mask = enabled_mask;
99
100 /* in particular, with binning shader we may end up with unused
101 * consts, ie. we could end up w/ constlen that is smaller
102 * than first_immediate. In that case truncate the user consts
103 * early to avoid HLSQ lockup caused by writing too many consts
104 */
105 first_immediate = MIN2(shader->first_immediate, shader->constlen);
106
107 /* emit user constants: */
108 while (enabled_mask) {
109 unsigned index = ffs(enabled_mask) - 1;
110 struct pipe_constant_buffer *cb = &constbuf->cb[index];
111 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
112
113 // I expect that size should be a multiple of vec4's:
114 assert(size == align(size, 4));
115
116 /* gallium could leave const buffers bound above what the
117 * current shader uses.. don't let that confuse us.
118 */
119 if (base >= (4 * first_immediate))
120 break;
121
122 if (constbuf->dirty_mask & (1 << index)) {
123 /* and even if the start of the const buffer is before
124 * first_immediate, the end may not be:
125 */
126 size = MIN2(size, (4 * first_immediate) - base);
127 fd4_emit_constant(ring, sb, base,
128 cb->buffer_offset, size,
129 cb->user_buffer, cb->buffer);
130 constbuf->dirty_mask &= ~(1 << index);
131 }
132
133 base += size;
134 enabled_mask &= ~(1 << index);
135 }
136
137 /* emit shader immediates: */
138 if (shader) {
139 int size = shader->immediates_count;
140 base = shader->first_immediate;
141
142 /* truncate size to avoid writing constants that shader
143 * does not use:
144 */
145 size = MIN2(size + base, shader->constlen) - base;
146
147 /* convert out of vec4: */
148 base *= 4;
149 size *= 4;
150
151 if (size > 0) {
152 fd4_emit_constant(ring, sb, base,
153 0, size, shader->immediates[0].val, NULL);
154 }
155 }
156 }
157
158 static void
159 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
160 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
161 {
162 unsigned i;
163
164 if (tex->num_samplers > 0) {
165 int num_samplers;
166
167 /* not sure if this is an a420.0 workaround, but we seem
168 * to need to emit these in pairs.. emit a final dummy
169 * entry if odd # of samplers:
170 */
171 num_samplers = align(tex->num_samplers, 2);
172
173 /* output sampler state: */
174 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * num_samplers));
175 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
176 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
177 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
178 CP_LOAD_STATE_0_NUM_UNIT(num_samplers));
179 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
180 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
181 for (i = 0; i < tex->num_samplers; i++) {
182 static const struct fd4_sampler_stateobj dummy_sampler = {};
183 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
184 fd4_sampler_stateobj(tex->samplers[i]) :
185 &dummy_sampler;
186 OUT_RING(ring, sampler->texsamp0);
187 OUT_RING(ring, sampler->texsamp1);
188 }
189
190 for (; i < num_samplers; i++) {
191 OUT_RING(ring, 0x00000000);
192 OUT_RING(ring, 0x00000000);
193 }
194 }
195
196 if (tex->num_textures > 0) {
197 /* emit texture state: */
198 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * tex->num_textures));
199 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
200 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
201 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
202 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
203 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
204 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
205 for (i = 0; i < tex->num_textures; i++) {
206 static const struct fd4_pipe_sampler_view dummy_view = {};
207 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
208 fd4_pipe_sampler_view(tex->textures[i]) :
209 &dummy_view;
210 struct fd_resource *rsc = view->tex_resource;
211 unsigned start = view->base.u.tex.first_level;
212 uint32_t offset = fd_resource_offset(rsc, start, 0);
213
214 OUT_RING(ring, view->texconst0);
215 OUT_RING(ring, view->texconst1);
216 OUT_RING(ring, view->texconst2);
217 OUT_RING(ring, view->texconst3);
218 OUT_RELOC(ring, rsc->bo, offset, view->textconst4, 0);
219 OUT_RING(ring, 0x00000000);
220 OUT_RING(ring, 0x00000000);
221 OUT_RING(ring, 0x00000000);
222 }
223 }
224 }
225
226 /* emit texture state for mem->gmem restore operation.. eventually it would
227 * be good to get rid of this and use normal CSO/etc state for more of these
228 * special cases..
229 */
230 void
231 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf)
232 {
233 struct fd_resource *rsc = fd_resource(psurf->texture);
234 unsigned lvl = psurf->u.tex.level;
235 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
236 uint32_t offset = fd_resource_offset(rsc, lvl, psurf->u.tex.first_layer);
237 enum pipe_format format = fd4_gmem_restore_format(psurf->format);
238
239 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
240
241 /* output sampler state: */
242 OUT_PKT3(ring, CP_LOAD_STATE, 4);
243 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
244 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
245 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
246 CP_LOAD_STATE_0_NUM_UNIT(1));
247 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
248 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
249 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
250 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
251 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
252 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
253 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
254 OUT_RING(ring, 0x00000000);
255
256 /* emit texture state: */
257 OUT_PKT3(ring, CP_LOAD_STATE, 10);
258 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
259 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
260 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
261 CP_LOAD_STATE_0_NUM_UNIT(1));
262 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
263 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
264 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
265 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
266 fd4_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
267 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
268 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(psurf->width) |
269 A4XX_TEX_CONST_1_HEIGHT(psurf->height));
270 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp));
271 OUT_RING(ring, 0x00000000);
272 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
273 OUT_RING(ring, 0x00000000);
274 OUT_RING(ring, 0x00000000);
275 OUT_RING(ring, 0x00000000);
276 }
277
278 void
279 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
280 {
281 uint32_t i, j, last = 0;
282 uint32_t total_in = 0;
283 const struct fd_vertex_state *vtx = emit->vtx;
284 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
285 unsigned n = MIN2(vtx->vtx->num_elements, vp->inputs_count);
286
287 /* hw doesn't like to be configured for zero vbo's, it seems: */
288 if (vtx->vtx->num_elements == 0)
289 return;
290
291 for (i = 0; i < n; i++)
292 if (vp->inputs[i].compmask)
293 last = i;
294
295 for (i = 0, j = 0; i <= last; i++) {
296 if (vp->inputs[i].compmask) {
297 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
298 const struct pipe_vertex_buffer *vb =
299 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
300 struct fd_resource *rsc = fd_resource(vb->buffer);
301 enum pipe_format pfmt = elem->src_format;
302 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
303 bool switchnext = (i != last);
304 uint32_t fs = util_format_get_blocksize(pfmt);
305 uint32_t off = vb->buffer_offset + elem->src_offset;
306 uint32_t size = fd_bo_size(rsc->bo) - off;
307 debug_assert(fmt != ~0);
308
309 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
310 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
311 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
312 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
313 OUT_RELOC(ring, rsc->bo, off, 0, 0);
314 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
315 OUT_RING(ring, 0x00000001);
316
317 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
318 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
319 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
320 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
321 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
322 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
323 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
324 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
325 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
326
327 total_in += vp->inputs[i].ncomp;
328 j++;
329 }
330 }
331
332 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
333 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
334 0xa0000 | /* XXX */
335 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
336 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
337 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
338 A4XX_VFD_CONTROL_1_REGID4VTX(regid(63,0)) |
339 A4XX_VFD_CONTROL_1_REGID4INST(regid(63,0)));
340 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
341 OUT_RING(ring, 0x0000fc00); /* XXX VFD_CONTROL_3 */
342 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
343
344 /* cache invalidate, otherwise vertex fetch could see
345 * stale vbo contents:
346 */
347 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
348 OUT_RING(ring, 0x00000000);
349 OUT_RING(ring, 0x00000012);
350 }
351
352 void
353 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
354 struct fd4_emit *emit)
355 {
356 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
357 struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
358 uint32_t dirty = emit->dirty;
359
360 emit_marker(ring, 5);
361
362 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
363 uint32_t val = fd4_zsa_stateobj(ctx->zsa)->rb_render_control;
364
365 /* I suppose if we needed to (which I don't *think* we need
366 * to), we could emit this for binning pass too. But we
367 * would need to keep a different patch-list for binning
368 * vs render pass.
369 */
370
371 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
372 OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
373 }
374
375 if (dirty & FD_DIRTY_ZSA) {
376 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
377
378 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
379 OUT_RING(ring, zsa->rb_alpha_control);
380
381 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
382 OUT_RING(ring, zsa->rb_stencil_control);
383 OUT_RING(ring, zsa->rb_stencil_control2);
384 }
385
386 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
387 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
388 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
389
390 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
391 OUT_RING(ring, zsa->rb_stencilrefmask |
392 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
393 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
394 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
395 }
396
397 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
398 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
399 bool fragz = fp->has_kill | fp->writes_pos;
400
401 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
402 OUT_RING(ring, zsa->rb_depth_control |
403 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE));
404
405 /* maybe this register/bitfield needs a better name.. this
406 * appears to be just disabling early-z
407 */
408 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
409 OUT_RING(ring, zsa->gras_alpha_control |
410 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE));
411 }
412
413 if (dirty & FD_DIRTY_RASTERIZER) {
414 struct fd4_rasterizer_stateobj *rasterizer =
415 fd4_rasterizer_stateobj(ctx->rasterizer);
416
417 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
418 OUT_RING(ring, rasterizer->gras_su_mode_control |
419 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
420
421 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
422 OUT_RING(ring, rasterizer->gras_su_point_minmax);
423 OUT_RING(ring, rasterizer->gras_su_point_size);
424
425 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
426 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
427 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
428 }
429
430 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
431 uint32_t val = fd4_rasterizer_stateobj(ctx->rasterizer)
432 ->gras_cl_clip_cntl;
433 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
434 OUT_RING(ring, val);
435 }
436
437 /* NOTE: since primitive_restart is not actually part of any
438 * state object, we need to make sure that we always emit
439 * PRIM_VTX_CNTL.. either that or be more clever and detect
440 * when it changes.
441 */
442 if (emit->info) {
443 uint32_t val = fd4_rasterizer_stateobj(ctx->rasterizer)
444 ->pc_prim_vtx_cntl;
445
446 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
447 val |= COND(fp->total_in > 0, A4XX_PC_PRIM_VTX_CNTL_VAROUT);
448
449 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
450 OUT_RING(ring, val);
451 OUT_RING(ring, 0x12); /* XXX UNKNOWN_21C5 */
452 }
453
454 if (dirty & FD_DIRTY_SCISSOR) {
455 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
456
457 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
458 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
459 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
460 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
461 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
462
463 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
464 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
465 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
466 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
467 }
468
469 if (dirty & FD_DIRTY_VIEWPORT) {
470 fd_wfi(ctx, ring);
471 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
472 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
473 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
474 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
475 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
476 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
477 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
478 }
479
480 if (dirty & FD_DIRTY_PROG)
481 fd4_program_emit(ring, emit);
482
483 if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
484 /* evil hack to deal sanely with clear path: */
485 (emit->prog == &ctx->prog)) {
486 fd_wfi(ctx, ring);
487 emit_constants(ring, SB_VERT_SHADER,
488 &ctx->constbuf[PIPE_SHADER_VERTEX],
489 (emit->prog->dirty & FD_SHADER_DIRTY_VP) ? vp : NULL);
490 if (!emit->key.binning_pass) {
491 emit_constants(ring, SB_FRAG_SHADER,
492 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
493 (emit->prog->dirty & FD_SHADER_DIRTY_FP) ? fp : NULL);
494 }
495 }
496
497 if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
498 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
499 uint32_t i;
500
501 for (i = 0; i < 8; i++) {
502 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
503 OUT_RING(ring, blend->rb_mrt[i].control);
504
505 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
506 OUT_RING(ring, blend->rb_mrt[i].blend_control);
507 }
508
509 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
510 OUT_RING(ring, blend->rb_fs_output |
511 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
512 }
513
514 if (dirty & FD_DIRTY_VERTTEX) {
515 if (vp->has_samp)
516 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
517 else
518 dirty &= ~FD_DIRTY_VERTTEX;
519 }
520
521 if (dirty & FD_DIRTY_FRAGTEX) {
522 if (fp->has_samp)
523 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
524 else
525 dirty &= ~FD_DIRTY_FRAGTEX;
526 }
527
528 ctx->dirty &= ~dirty;
529 }
530
531 /* emit setup at begin of new cmdstream buffer (don't rely on previous
532 * state, there could have been a context switch between ioctls):
533 */
534 void
535 fd4_emit_restore(struct fd_context *ctx)
536 {
537 struct fd4_context *fd4_ctx = fd4_context(ctx);
538 struct fd_ringbuffer *ring = ctx->ring;
539
540 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
541 OUT_RING(ring, 0x00000001);
542
543 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
544 OUT_RING(ring, 0x00000000);
545
546 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC3, 1);
547 OUT_RING(ring, 0x00000006);
548
549 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0F03, 1);
550 OUT_RING(ring, 0x0000003a);
551
552 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
553 OUT_RING(ring, 0x00000001);
554
555 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
556 OUT_RING(ring, 0x00000000);
557
558 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
559 OUT_RING(ring, 0x00000007);
560
561 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
562 OUT_RING(ring, 0x00000000);
563
564 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
565 OUT_RING(ring, 0x00000000);
566 OUT_RING(ring, 0x00000012);
567
568 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E05, 1);
569 OUT_RING(ring, 0x00000000);
570
571 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
572 OUT_RING(ring, 0x00000006);
573
574 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
575 OUT_RING(ring, 0x00000000);
576
577 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
578 OUT_RING(ring, 0x00040000);
579
580 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
581 OUT_RING(ring, 0x00000000);
582
583 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
584 OUT_RING(ring, 0x00001000);
585
586 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
587 OUT_RING(ring, 0x00000000);
588
589 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F0, 1);
590 OUT_RING(ring, 0x00000000);
591
592 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F1, 1);
593 OUT_RING(ring, 0x00000000);
594
595 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F2, 1);
596 OUT_RING(ring, 0x00000000);
597
598 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
599 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
600 A4XX_RB_BLEND_RED_FLOAT(0.0));
601 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
602 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
603 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
604 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
605 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
606 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
607
608 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F7, 1);
609 OUT_RING(ring, 0x3f800000);
610
611 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
612 OUT_RING(ring, 0x00000000);
613
614 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
615 OUT_RING(ring, 0x00000000);
616
617 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
618 OUT_RING(ring, 0x00000000);
619
620 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
621 OUT_RING(ring, 0x00000000);
622
623 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
624 OUT_RING(ring, 0x00000000);
625
626 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
627 OUT_RING(ring, 0x00000000);
628
629 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
630 OUT_RING(ring, 0x0000001d);
631
632 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
633 OUT_RING(ring, 0x00000000);
634
635 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
636 OUT_RING(ring, 0x00000001);
637
638 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
639 OUT_RING(ring, 0x00000000);
640
641 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
642 OUT_RING(ring, 0x00000000);
643
644 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
645 OUT_RING(ring, 0x00000000);
646
647 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2381, 1);
648 OUT_RING(ring, 0x00000010);
649
650 OUT_PKT0(ring, REG_A4XX_UNKNOWN_23A0, 1);
651 OUT_RING(ring, 0x00000010);
652
653 /* we don't use this yet.. probably best to disable.. */
654 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
655 OUT_RING(ring, CP_SET_DRAW_STATE_0_COUNT(0) |
656 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS |
657 CP_SET_DRAW_STATE_0_GROUP_ID(0));
658 OUT_RING(ring, CP_SET_DRAW_STATE_1_ADDR(0));
659
660 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
661 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
662 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
663
664 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
665 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
666 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
667
668 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
669 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
670 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
671 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
672 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
673
674 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
675 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
676 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
677
678 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
679 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
680 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
681
682 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
683 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
684
685 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
686 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
687
688 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL3, 1);
689 OUT_RING(ring, A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(0xf));
690
691 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
692 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
693
694 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
695 OUT_RING(ring, 0x0);
696
697 ctx->needs_rb_fbd = true;
698 }