1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
51 fd4_emit_constant(struct fd_ringbuffer
*ring
,
52 enum adreno_state_block sb
,
53 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
54 const uint32_t *dwords
, struct pipe_resource
*prsc
)
57 enum adreno_state_src src
;
67 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
68 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
69 CP_LOAD_STATE_0_STATE_SRC(src
) |
70 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
71 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/4));
73 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
74 OUT_RELOC(ring
, bo
, offset
,
75 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
77 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
78 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
79 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
81 for (i
= 0; i
< sz
; i
++) {
82 OUT_RING(ring
, dwords
[i
]);
87 emit_constants(struct fd_ringbuffer
*ring
,
88 enum adreno_state_block sb
,
89 struct fd_constbuf_stateobj
*constbuf
,
90 struct ir3_shader_variant
*shader
,
93 uint32_t enabled_mask
= constbuf
->enabled_mask
;
97 // XXX TODO only emit dirty consts.. but we need to keep track if
98 // they are clobbered by a clear, gmem2mem, or mem2gmem..
99 constbuf
->dirty_mask
= enabled_mask
;
101 /* in particular, with binning shader we may end up with unused
102 * consts, ie. we could end up w/ constlen that is smaller
103 * than first_immediate. In that case truncate the user consts
104 * early to avoid HLSQ lockup caused by writing too many consts
106 max_const
= MIN2(shader
->first_driver_param
, shader
->constlen
);
108 /* emit user constants: */
109 if (enabled_mask
& 1) {
110 const unsigned index
= 0;
111 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[index
];
112 unsigned size
= align(cb
->buffer_size
, 4) / 4; /* size in dwords */
114 // I expect that size should be a multiple of vec4's:
115 assert(size
== align(size
, 4));
117 /* and even if the start of the const buffer is before
118 * first_immediate, the end may not be:
120 size
= MIN2(size
, 4 * max_const
);
122 if (size
&& (constbuf
->dirty_mask
& (1 << index
))) {
123 fd4_emit_constant(ring
, sb
, 0,
124 cb
->buffer_offset
, size
,
125 cb
->user_buffer
, cb
->buffer
);
126 constbuf
->dirty_mask
&= ~(1 << index
);
129 enabled_mask
&= ~(1 << index
);
133 if (shader
->constlen
> shader
->first_driver_param
) {
134 uint32_t params
= MIN2(4, shader
->constlen
- shader
->first_driver_param
);
135 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + params
* 4);
136 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(shader
->first_driver_param
) |
137 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
138 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
139 CP_LOAD_STATE_0_NUM_UNIT(params
));
140 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
141 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
143 for (i
= 1; i
<= params
* 4; i
++) {
144 struct pipe_constant_buffer
*cb
= &constbuf
->cb
[i
];
145 assert(!cb
->user_buffer
);
146 if ((enabled_mask
& (1 << i
)) && cb
->buffer
)
147 OUT_RELOC(ring
, fd_resource(cb
->buffer
)->bo
, cb
->buffer_offset
, 0, 0);
149 OUT_RING(ring
, 0xbad00000 | ((i
- 1) << 16));
153 /* emit shader immediates: */
154 if (shader
&& emit_immediates
) {
155 int size
= shader
->immediates_count
;
156 uint32_t base
= shader
->first_immediate
;
158 /* truncate size to avoid writing constants that shader
161 size
= MIN2(size
+ base
, shader
->constlen
) - base
;
163 /* convert out of vec4: */
168 fd4_emit_constant(ring
, sb
, base
,
169 0, size
, shader
->immediates
[0].val
, NULL
);
175 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
176 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
180 if (tex
->num_samplers
> 0) {
183 /* not sure if this is an a420.0 workaround, but we seem
184 * to need to emit these in pairs.. emit a final dummy
185 * entry if odd # of samplers:
187 num_samplers
= align(tex
->num_samplers
, 2);
189 /* output sampler state: */
190 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * num_samplers
));
191 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
192 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
193 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
194 CP_LOAD_STATE_0_NUM_UNIT(num_samplers
));
195 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
196 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
197 for (i
= 0; i
< tex
->num_samplers
; i
++) {
198 static const struct fd4_sampler_stateobj dummy_sampler
= {};
199 const struct fd4_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
200 fd4_sampler_stateobj(tex
->samplers
[i
]) :
202 OUT_RING(ring
, sampler
->texsamp0
);
203 OUT_RING(ring
, sampler
->texsamp1
);
206 for (; i
< num_samplers
; i
++) {
207 OUT_RING(ring
, 0x00000000);
208 OUT_RING(ring
, 0x00000000);
212 if (tex
->num_textures
> 0) {
213 /* emit texture state: */
214 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (8 * tex
->num_textures
));
215 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
216 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
217 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
218 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
219 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
220 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
221 for (i
= 0; i
< tex
->num_textures
; i
++) {
222 static const struct fd4_pipe_sampler_view dummy_view
= {};
223 const struct fd4_pipe_sampler_view
*view
= tex
->textures
[i
] ?
224 fd4_pipe_sampler_view(tex
->textures
[i
]) :
226 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
227 unsigned start
= view
->base
.u
.tex
.first_level
;
228 uint32_t offset
= fd_resource_offset(rsc
, start
, 0);
230 OUT_RING(ring
, view
->texconst0
);
231 OUT_RING(ring
, view
->texconst1
);
232 OUT_RING(ring
, view
->texconst2
);
233 OUT_RING(ring
, view
->texconst3
);
234 OUT_RELOC(ring
, rsc
->bo
, offset
, view
->textconst4
, 0);
235 OUT_RING(ring
, 0x00000000);
236 OUT_RING(ring
, 0x00000000);
237 OUT_RING(ring
, 0x00000000);
242 /* emit texture state for mem->gmem restore operation.. eventually it would
243 * be good to get rid of this and use normal CSO/etc state for more of these
247 fd4_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, struct pipe_surface
*psurf
)
249 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
250 unsigned lvl
= psurf
->u
.tex
.level
;
251 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
252 uint32_t offset
= fd_resource_offset(rsc
, lvl
, psurf
->u
.tex
.first_layer
);
253 enum pipe_format format
= fd4_gmem_restore_format(psurf
->format
);
255 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
257 /* output sampler state: */
258 OUT_PKT3(ring
, CP_LOAD_STATE
, 4);
259 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
260 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
261 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
262 CP_LOAD_STATE_0_NUM_UNIT(1));
263 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
264 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
265 OUT_RING(ring
, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST
) |
266 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST
) |
267 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE
) |
268 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE
) |
269 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT
));
270 OUT_RING(ring
, 0x00000000);
272 /* emit texture state: */
273 OUT_PKT3(ring
, CP_LOAD_STATE
, 10);
274 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
275 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
276 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
277 CP_LOAD_STATE_0_NUM_UNIT(1));
278 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
279 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
280 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format
)) |
281 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
282 fd4_tex_swiz(format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
283 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
));
284 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(psurf
->width
) |
285 A4XX_TEX_CONST_1_HEIGHT(psurf
->height
));
286 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
));
287 OUT_RING(ring
, 0x00000000);
288 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
289 OUT_RING(ring
, 0x00000000);
290 OUT_RING(ring
, 0x00000000);
291 OUT_RING(ring
, 0x00000000);
295 fd4_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
)
297 int32_t i
, j
, last
= -1;
298 uint32_t total_in
= 0;
299 const struct fd_vertex_state
*vtx
= emit
->vtx
;
300 struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
301 unsigned vertex_regid
= regid(63, 0), instance_regid
= regid(63, 0);
303 for (i
= 0; i
< vp
->inputs_count
; i
++) {
304 uint8_t semantic
= sem2name(vp
->inputs
[i
].semantic
);
305 if (semantic
== TGSI_SEMANTIC_VERTEXID_NOBASE
)
306 vertex_regid
= vp
->inputs
[i
].regid
;
307 else if (semantic
== TGSI_SEMANTIC_INSTANCEID
)
308 instance_regid
= vp
->inputs
[i
].regid
;
309 else if ((i
< vtx
->vtx
->num_elements
) && vp
->inputs
[i
].compmask
)
313 /* hw doesn't like to be configured for zero vbo's, it seems: */
314 if ((vtx
->vtx
->num_elements
== 0) &&
315 (vertex_regid
== regid(63, 0)) &&
316 (instance_regid
== regid(63, 0)))
319 for (i
= 0, j
= 0; i
<= last
; i
++) {
320 assert(sem2name(vp
->inputs
[i
].semantic
) == 0);
321 if (vp
->inputs
[i
].compmask
) {
322 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
323 const struct pipe_vertex_buffer
*vb
=
324 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
325 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
326 enum pipe_format pfmt
= elem
->src_format
;
327 enum a4xx_vtx_fmt fmt
= fd4_pipe2vtx(pfmt
);
328 bool switchnext
= (i
!= last
) ||
329 (vertex_regid
!= regid(63, 0)) ||
330 (instance_regid
!= regid(63, 0));
331 bool isint
= util_format_is_pure_integer(pfmt
);
332 uint32_t fs
= util_format_get_blocksize(pfmt
);
333 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
334 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
335 debug_assert(fmt
!= ~0);
337 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(j
), 4);
338 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
339 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
340 COND(elem
->instance_divisor
, A4XX_VFD_FETCH_INSTR_0_INSTANCED
) |
341 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
342 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
343 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(size
));
344 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem
->instance_divisor
)));
346 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(j
), 1);
347 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
348 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
349 A4XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
350 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt
)) |
351 A4XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
352 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
353 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
354 COND(isint
, A4XX_VFD_DECODE_INSTR_INT
) |
355 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
357 total_in
+= vp
->inputs
[i
].ncomp
;
362 OUT_PKT0(ring
, REG_A4XX_VFD_CONTROL_0
, 5);
363 OUT_RING(ring
, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
365 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
366 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
367 OUT_RING(ring
, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
368 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
369 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
370 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_2 */
371 OUT_RING(ring
, A4XX_VFD_CONTROL_3_REGID_VTXCNT(regid(63, 0)));
372 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_4 */
374 /* cache invalidate, otherwise vertex fetch could see
375 * stale vbo contents:
377 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
378 OUT_RING(ring
, 0x00000000);
379 OUT_RING(ring
, 0x00000012);
383 fd4_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
384 struct fd4_emit
*emit
)
386 struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
387 struct ir3_shader_variant
*fp
= fd4_emit_get_fp(emit
);
388 uint32_t dirty
= emit
->dirty
;
390 emit_marker(ring
, 5);
392 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) && !emit
->key
.binning_pass
) {
393 uint32_t val
= fd4_zsa_stateobj(ctx
->zsa
)->rb_render_control
;
395 /* I suppose if we needed to (which I don't *think* we need
396 * to), we could emit this for binning pass too. But we
397 * would need to keep a different patch-list for binning
401 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
402 OUT_RINGP(ring
, val
, &fd4_context(ctx
)->rbrc_patches
);
405 if (dirty
& FD_DIRTY_ZSA
) {
406 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
408 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
409 OUT_RING(ring
, zsa
->rb_alpha_control
);
411 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
412 OUT_RING(ring
, zsa
->rb_stencil_control
);
413 OUT_RING(ring
, zsa
->rb_stencil_control2
);
416 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
417 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
418 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
420 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
421 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
422 A4XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
423 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
424 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
427 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) {
428 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
429 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
431 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
432 OUT_RING(ring
, zsa
->rb_depth_control
|
433 COND(fragz
, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
));
435 /* maybe this register/bitfield needs a better name.. this
436 * appears to be just disabling early-z
438 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
439 OUT_RING(ring
, zsa
->gras_alpha_control
|
440 COND(fragz
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
));
443 if (dirty
& FD_DIRTY_RASTERIZER
) {
444 struct fd4_rasterizer_stateobj
*rasterizer
=
445 fd4_rasterizer_stateobj(ctx
->rasterizer
);
447 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
448 OUT_RING(ring
, rasterizer
->gras_su_mode_control
|
449 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
451 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POINT_MINMAX
, 2);
452 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
453 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
455 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
456 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
457 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
459 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
460 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
463 /* NOTE: since primitive_restart is not actually part of any
464 * state object, we need to make sure that we always emit
465 * PRIM_VTX_CNTL.. either that or be more clever and detect
469 uint32_t val
= fd4_rasterizer_stateobj(ctx
->rasterizer
)
472 val
|= COND(vp
->writes_psize
, A4XX_PC_PRIM_VTX_CNTL_PSIZE
);
473 if (fp
->total_in
> 0) {
474 uint32_t varout
= align(fp
->total_in
, 16) / 16;
476 varout
= align(varout
, 2);
477 val
|= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout
);
480 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 2);
482 OUT_RING(ring
, 0x12); /* XXX UNKNOWN_21C5 */
485 if (dirty
& FD_DIRTY_SCISSOR
) {
486 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
488 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
489 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
490 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
491 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
492 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
494 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
495 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
496 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
497 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
500 if (dirty
& FD_DIRTY_VIEWPORT
) {
502 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
503 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
504 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
505 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
506 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
507 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
508 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
511 if (dirty
& FD_DIRTY_PROG
)
512 fd4_program_emit(ring
, emit
);
514 if ((dirty
& (FD_DIRTY_PROG
| FD_DIRTY_CONSTBUF
)) &&
515 /* evil hack to deal sanely with clear path: */
516 (emit
->prog
== &ctx
->prog
)) {
518 emit_constants(ring
, SB_VERT_SHADER
,
519 &ctx
->constbuf
[PIPE_SHADER_VERTEX
],
520 vp
, emit
->prog
->dirty
& FD_SHADER_DIRTY_VP
);
521 if (!emit
->key
.binning_pass
) {
522 emit_constants(ring
, SB_FRAG_SHADER
,
523 &ctx
->constbuf
[PIPE_SHADER_FRAGMENT
],
524 fp
, emit
->prog
->dirty
& FD_SHADER_DIRTY_FP
);
528 /* emit driver params every time */
529 if (emit
->info
&& emit
->prog
== &ctx
->prog
) {
530 uint32_t vertex_params
[4] = {
531 emit
->info
->indexed
? emit
->info
->index_bias
: emit
->info
->start
,
536 if (vp
->constlen
>= vp
->first_driver_param
+ 4) {
537 fd4_emit_constant(ring
, SB_VERT_SHADER
,
538 (vp
->first_driver_param
+ 4) * 4,
539 0, 4, vertex_params
, NULL
);
543 if ((dirty
& FD_DIRTY_BLEND
) && ctx
->blend
) {
544 struct fd4_blend_stateobj
*blend
= fd4_blend_stateobj(ctx
->blend
);
547 for (i
= 0; i
< 8; i
++) {
548 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
549 OUT_RING(ring
, blend
->rb_mrt
[i
].control
);
551 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
552 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
);
555 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
556 OUT_RING(ring
, blend
->rb_fs_output
|
557 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
560 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
561 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
562 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 4);
563 OUT_RING(ring
, A4XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
564 A4XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
565 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
566 A4XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
567 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
568 A4XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
569 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
570 A4XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
573 if (dirty
& FD_DIRTY_VERTTEX
) {
575 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
);
577 dirty
&= ~FD_DIRTY_VERTTEX
;
580 if (dirty
& FD_DIRTY_FRAGTEX
) {
582 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
584 dirty
&= ~FD_DIRTY_FRAGTEX
;
587 ctx
->dirty
&= ~dirty
;
590 /* emit setup at begin of new cmdstream buffer (don't rely on previous
591 * state, there could have been a context switch between ioctls):
594 fd4_emit_restore(struct fd_context
*ctx
)
596 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
597 struct fd_ringbuffer
*ring
= ctx
->ring
;
599 OUT_PKT0(ring
, REG_A4XX_RBBM_PERFCTR_CTL
, 1);
600 OUT_RING(ring
, 0x00000001);
602 OUT_PKT0(ring
, REG_A4XX_GRAS_DEBUG_ECO_CONTROL
, 1);
603 OUT_RING(ring
, 0x00000000);
605 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0EC3
, 1);
606 OUT_RING(ring
, 0x00000006);
608 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0F03
, 1);
609 OUT_RING(ring
, 0x0000003a);
611 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0D01
, 1);
612 OUT_RING(ring
, 0x00000001);
614 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0E42
, 1);
615 OUT_RING(ring
, 0x00000000);
617 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_WAYS_VFD
, 1);
618 OUT_RING(ring
, 0x00000007);
620 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_MODE_CONTROL
, 1);
621 OUT_RING(ring
, 0x00000000);
623 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
624 OUT_RING(ring
, 0x00000000);
625 OUT_RING(ring
, 0x00000012);
627 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0E05
, 1);
628 OUT_RING(ring
, 0x00000000);
630 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC5
, 1);
631 OUT_RING(ring
, 0x00000006);
633 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC6
, 1);
634 OUT_RING(ring
, 0x00000000);
636 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0EC2
, 1);
637 OUT_RING(ring
, 0x00040000);
639 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2001
, 1);
640 OUT_RING(ring
, 0x00000000);
642 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
643 OUT_RING(ring
, 0x00001000);
645 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20EF
, 1);
646 OUT_RING(ring
, 0x00000000);
648 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20F0
, 1);
649 OUT_RING(ring
, 0x00000000);
651 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20F1
, 1);
652 OUT_RING(ring
, 0x00000000);
654 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20F2
, 1);
655 OUT_RING(ring
, 0x00000000);
657 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 4);
658 OUT_RING(ring
, A4XX_RB_BLEND_RED_UINT(0) |
659 A4XX_RB_BLEND_RED_FLOAT(0.0));
660 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_UINT(0) |
661 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
662 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_UINT(0) |
663 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
664 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
665 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
667 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20F7
, 1);
668 OUT_RING(ring
, 0x3f800000);
670 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2152
, 1);
671 OUT_RING(ring
, 0x00000000);
673 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2153
, 1);
674 OUT_RING(ring
, 0x00000000);
676 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2154
, 1);
677 OUT_RING(ring
, 0x00000000);
679 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2155
, 1);
680 OUT_RING(ring
, 0x00000000);
682 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2156
, 1);
683 OUT_RING(ring
, 0x00000000);
685 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2157
, 1);
686 OUT_RING(ring
, 0x00000000);
688 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21C3
, 1);
689 OUT_RING(ring
, 0x0000001d);
691 OUT_PKT0(ring
, REG_A4XX_PC_GS_PARAM
, 1);
692 OUT_RING(ring
, 0x00000000);
694 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21E6
, 1);
695 OUT_RING(ring
, 0x00000001);
697 OUT_PKT0(ring
, REG_A4XX_PC_HS_PARAM
, 1);
698 OUT_RING(ring
, 0x00000000);
700 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_22D7
, 1);
701 OUT_RING(ring
, 0x00000000);
703 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_OFFSET
, 1);
704 OUT_RING(ring
, 0x00000000);
706 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_COUNT
, 1);
707 OUT_RING(ring
, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
708 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
709 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
710 A4XX_TPL1_TP_TEX_COUNT_GS(0));
712 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_FS_TEX_COUNT
, 1);
715 /* we don't use this yet.. probably best to disable.. */
716 OUT_PKT3(ring
, CP_SET_DRAW_STATE
, 2);
717 OUT_RING(ring
, CP_SET_DRAW_STATE_0_COUNT(0) |
718 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS
|
719 CP_SET_DRAW_STATE_0_GROUP_ID(0));
720 OUT_RING(ring
, CP_SET_DRAW_STATE_1_ADDR(0));
722 OUT_PKT0(ring
, REG_A4XX_SP_VS_PVT_MEM_PARAM
, 2);
723 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
724 OUT_RELOC(ring
, fd4_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
726 OUT_PKT0(ring
, REG_A4XX_SP_FS_PVT_MEM_PARAM
, 2);
727 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
728 OUT_RELOC(ring
, fd4_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
730 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
731 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
732 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
733 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
734 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
736 OUT_PKT0(ring
, REG_A4XX_RB_MSAA_CONTROL
, 1);
737 OUT_RING(ring
, A4XX_RB_MSAA_CONTROL_DISABLE
|
738 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
));
740 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_GB_CLIP_ADJ
, 1);
741 OUT_RING(ring
, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
742 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
744 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
745 OUT_RING(ring
, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
));
747 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
748 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
750 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
751 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(0xf));
753 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
754 OUT_RING(ring
, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR
);
756 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
759 ctx
->needs_rb_fbd
= true;