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freedreno/a3xx+a4xx: add support for vtxcnt semantic
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 void
56 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = 0x2; // TODO ??
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
95 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
96 {
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100 debug_assert((num % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num/4));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 if (write) {
113 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121 }
122
123 static void
124 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
125 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
126 {
127 unsigned i;
128
129 if (tex->num_samplers > 0) {
130 int num_samplers;
131
132 /* not sure if this is an a420.0 workaround, but we seem
133 * to need to emit these in pairs.. emit a final dummy
134 * entry if odd # of samplers:
135 */
136 num_samplers = align(tex->num_samplers, 2);
137
138 /* output sampler state: */
139 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * num_samplers));
140 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
141 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
142 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
143 CP_LOAD_STATE_0_NUM_UNIT(num_samplers));
144 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
145 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
146 for (i = 0; i < tex->num_samplers; i++) {
147 static const struct fd4_sampler_stateobj dummy_sampler = {};
148 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
149 fd4_sampler_stateobj(tex->samplers[i]) :
150 &dummy_sampler;
151 OUT_RING(ring, sampler->texsamp0);
152 OUT_RING(ring, sampler->texsamp1);
153 }
154
155 for (; i < num_samplers; i++) {
156 OUT_RING(ring, 0x00000000);
157 OUT_RING(ring, 0x00000000);
158 }
159 }
160
161 if (tex->num_textures > 0) {
162 /* emit texture state: */
163 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * tex->num_textures));
164 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
165 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
166 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
167 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
168 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
169 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
170 for (i = 0; i < tex->num_textures; i++) {
171 static const struct fd4_pipe_sampler_view dummy_view = {};
172 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
173 fd4_pipe_sampler_view(tex->textures[i]) :
174 &dummy_view;
175 unsigned start = view->base.u.tex.first_level;
176
177 OUT_RING(ring, view->texconst0);
178 OUT_RING(ring, view->texconst1);
179 OUT_RING(ring, view->texconst2);
180 OUT_RING(ring, view->texconst3);
181 if (view->base.texture) {
182 struct fd_resource *rsc = fd_resource(view->base.texture);
183 uint32_t offset = fd_resource_offset(rsc, start, 0);
184 OUT_RELOC(ring, rsc->bo, offset, view->textconst4, 0);
185 } else {
186 OUT_RING(ring, 0x00000000);
187 }
188 OUT_RING(ring, 0x00000000);
189 OUT_RING(ring, 0x00000000);
190 OUT_RING(ring, 0x00000000);
191 }
192 }
193 }
194
195 /* emit texture state for mem->gmem restore operation.. eventually it would
196 * be good to get rid of this and use normal CSO/etc state for more of these
197 * special cases..
198 */
199 void
200 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf)
201 {
202 struct fd_resource *rsc = fd_resource(psurf->texture);
203 unsigned lvl = psurf->u.tex.level;
204 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
205 uint32_t offset = fd_resource_offset(rsc, lvl, psurf->u.tex.first_layer);
206 enum pipe_format format = fd4_gmem_restore_format(psurf->format);
207
208 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
209
210 /* output sampler state: */
211 OUT_PKT3(ring, CP_LOAD_STATE, 4);
212 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
213 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
214 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
215 CP_LOAD_STATE_0_NUM_UNIT(1));
216 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
217 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
218 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
219 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
220 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
221 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
222 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
223 OUT_RING(ring, 0x00000000);
224
225 /* emit texture state: */
226 OUT_PKT3(ring, CP_LOAD_STATE, 10);
227 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
228 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
229 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
230 CP_LOAD_STATE_0_NUM_UNIT(1));
231 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
232 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
233 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
234 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
235 fd4_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
236 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
237 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(psurf->width) |
238 A4XX_TEX_CONST_1_HEIGHT(psurf->height));
239 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp));
240 OUT_RING(ring, 0x00000000);
241 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
242 OUT_RING(ring, 0x00000000);
243 OUT_RING(ring, 0x00000000);
244 OUT_RING(ring, 0x00000000);
245 }
246
247 void
248 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
249 {
250 int32_t i, j, last = -1;
251 uint32_t total_in = 0;
252 const struct fd_vertex_state *vtx = emit->vtx;
253 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
254 unsigned vertex_regid = regid(63, 0);
255 unsigned instance_regid = regid(63, 0);
256 unsigned vtxcnt_regid = regid(63, 0);
257
258 for (i = 0; i < vp->inputs_count; i++) {
259 uint8_t semantic = sem2name(vp->inputs[i].semantic);
260 if (semantic == TGSI_SEMANTIC_VERTEXID_NOBASE)
261 vertex_regid = vp->inputs[i].regid;
262 else if (semantic == TGSI_SEMANTIC_INSTANCEID)
263 instance_regid = vp->inputs[i].regid;
264 else if (semantic == IR3_SEMANTIC_VTXCNT)
265 vtxcnt_regid = vp->inputs[i].regid;
266 else if ((i < vtx->vtx->num_elements) && vp->inputs[i].compmask)
267 last = i;
268 }
269
270 /* hw doesn't like to be configured for zero vbo's, it seems: */
271 if ((vtx->vtx->num_elements == 0) &&
272 (vertex_regid == regid(63, 0)) &&
273 (instance_regid == regid(63, 0)) &&
274 (vtxcnt_regid == regid(63, 0)))
275 return;
276
277 for (i = 0, j = 0; i <= last; i++) {
278 assert(sem2name(vp->inputs[i].semantic) == 0);
279 if (vp->inputs[i].compmask) {
280 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
281 const struct pipe_vertex_buffer *vb =
282 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
283 struct fd_resource *rsc = fd_resource(vb->buffer);
284 enum pipe_format pfmt = elem->src_format;
285 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
286 bool switchnext = (i != last) ||
287 (vertex_regid != regid(63, 0)) ||
288 (instance_regid != regid(63, 0)) ||
289 (vtxcnt_regid != regid(63, 0));
290 bool isint = util_format_is_pure_integer(pfmt);
291 uint32_t fs = util_format_get_blocksize(pfmt);
292 uint32_t off = vb->buffer_offset + elem->src_offset;
293 uint32_t size = fd_bo_size(rsc->bo) - off;
294 debug_assert(fmt != ~0);
295
296 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
297 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
298 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
299 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
300 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
301 OUT_RELOC(ring, rsc->bo, off, 0, 0);
302 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
303 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
304
305 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
306 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
307 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
308 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
309 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
310 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
311 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
312 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
313 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
314 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
315
316 total_in += vp->inputs[i].ncomp;
317 j++;
318 }
319 }
320
321 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
322 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
323 0xa0000 | /* XXX */
324 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
325 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
326 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
327 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
328 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
329 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
330 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
331 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
332
333 /* cache invalidate, otherwise vertex fetch could see
334 * stale vbo contents:
335 */
336 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
337 OUT_RING(ring, 0x00000000);
338 OUT_RING(ring, 0x00000012);
339 }
340
341 void
342 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
343 struct fd4_emit *emit)
344 {
345 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
346 struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
347 uint32_t dirty = emit->dirty;
348
349 emit_marker(ring, 5);
350
351 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
352 uint32_t val = fd4_zsa_stateobj(ctx->zsa)->rb_render_control;
353
354 /* I suppose if we needed to (which I don't *think* we need
355 * to), we could emit this for binning pass too. But we
356 * would need to keep a different patch-list for binning
357 * vs render pass.
358 */
359
360 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
361 OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
362 }
363
364 if (dirty & FD_DIRTY_ZSA) {
365 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
366
367 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
368 OUT_RING(ring, zsa->rb_alpha_control);
369
370 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
371 OUT_RING(ring, zsa->rb_stencil_control);
372 OUT_RING(ring, zsa->rb_stencil_control2);
373 }
374
375 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
376 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
377 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
378
379 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
380 OUT_RING(ring, zsa->rb_stencilrefmask |
381 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
382 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
383 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
384 }
385
386 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
387 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
388 bool fragz = fp->has_kill | fp->writes_pos;
389
390 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
391 OUT_RING(ring, zsa->rb_depth_control |
392 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE));
393
394 /* maybe this register/bitfield needs a better name.. this
395 * appears to be just disabling early-z
396 */
397 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
398 OUT_RING(ring, zsa->gras_alpha_control |
399 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE));
400 }
401
402 if (dirty & FD_DIRTY_RASTERIZER) {
403 struct fd4_rasterizer_stateobj *rasterizer =
404 fd4_rasterizer_stateobj(ctx->rasterizer);
405
406 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
407 OUT_RING(ring, rasterizer->gras_su_mode_control |
408 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
409
410 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
411 OUT_RING(ring, rasterizer->gras_su_point_minmax);
412 OUT_RING(ring, rasterizer->gras_su_point_size);
413
414 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
415 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
416 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
417
418 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
419 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
420 }
421
422 /* NOTE: since primitive_restart is not actually part of any
423 * state object, we need to make sure that we always emit
424 * PRIM_VTX_CNTL.. either that or be more clever and detect
425 * when it changes.
426 */
427 if (emit->info) {
428 const struct pipe_draw_info *info = emit->info;
429 uint32_t val = fd4_rasterizer_stateobj(ctx->rasterizer)
430 ->pc_prim_vtx_cntl;
431
432 if (info->indexed && info->primitive_restart)
433 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
434
435 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
436
437 if (fp->total_in > 0) {
438 uint32_t varout = align(fp->total_in, 16) / 16;
439 if (varout > 1)
440 varout = align(varout, 2);
441 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
442 }
443
444 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
445 OUT_RING(ring, val);
446 OUT_RING(ring, 0x12); /* XXX UNKNOWN_21C5 */
447 }
448
449 if (dirty & FD_DIRTY_SCISSOR) {
450 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
451
452 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
453 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
454 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
455 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
456 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
457
458 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
459 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
460 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
461 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
462 }
463
464 if (dirty & FD_DIRTY_VIEWPORT) {
465 fd_wfi(ctx, ring);
466 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
467 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
468 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
469 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
470 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
471 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
472 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
473 }
474
475 if (dirty & FD_DIRTY_PROG)
476 fd4_program_emit(ring, emit);
477
478 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
479 ir3_emit_consts(vp, ring, emit->info, dirty);
480 if (!emit->key.binning_pass)
481 ir3_emit_consts(fp, ring, emit->info, dirty);
482 /* mark clean after emitting consts: */
483 ctx->prog.dirty = 0;
484 }
485
486 if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
487 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
488 uint32_t i;
489
490 for (i = 0; i < 8; i++) {
491 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
492 OUT_RING(ring, blend->rb_mrt[i].control);
493
494 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
495 OUT_RING(ring, blend->rb_mrt[i].blend_control);
496 }
497
498 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
499 OUT_RING(ring, blend->rb_fs_output |
500 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
501 }
502
503 if (dirty & FD_DIRTY_BLEND_COLOR) {
504 struct pipe_blend_color *bcolor = &ctx->blend_color;
505 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
506 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
507 A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
508 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
509 A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
510 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
511 A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
512 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
513 A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
514 }
515
516 if (dirty & FD_DIRTY_VERTTEX) {
517 if (vp->has_samp)
518 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
519 else
520 dirty &= ~FD_DIRTY_VERTTEX;
521 }
522
523 if (dirty & FD_DIRTY_FRAGTEX) {
524 if (fp->has_samp)
525 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
526 else
527 dirty &= ~FD_DIRTY_FRAGTEX;
528 }
529
530 ctx->dirty &= ~dirty;
531 }
532
533 /* emit setup at begin of new cmdstream buffer (don't rely on previous
534 * state, there could have been a context switch between ioctls):
535 */
536 void
537 fd4_emit_restore(struct fd_context *ctx)
538 {
539 struct fd4_context *fd4_ctx = fd4_context(ctx);
540 struct fd_ringbuffer *ring = ctx->ring;
541
542 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
543 OUT_RING(ring, 0x00000001);
544
545 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
546 OUT_RING(ring, 0x00000000);
547
548 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
549 OUT_RING(ring, 0x00000006);
550
551 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
552 OUT_RING(ring, 0x0000003a);
553
554 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
555 OUT_RING(ring, 0x00000001);
556
557 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
558 OUT_RING(ring, 0x00000000);
559
560 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
561 OUT_RING(ring, 0x00000007);
562
563 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
564 OUT_RING(ring, 0x00000000);
565
566 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
567 OUT_RING(ring, 0x00000000);
568 OUT_RING(ring, 0x00000012);
569
570 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
571 OUT_RING(ring, 0x00000000);
572
573 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
574 OUT_RING(ring, 0x00000006);
575
576 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
577 OUT_RING(ring, 0x00000000);
578
579 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
580 OUT_RING(ring, 0x00040000);
581
582 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
583 OUT_RING(ring, 0x00000000);
584
585 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
586 OUT_RING(ring, 0x00001000);
587
588 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
589 OUT_RING(ring, 0x00000000);
590
591 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F0, 1);
592 OUT_RING(ring, 0x00000000);
593
594 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F1, 1);
595 OUT_RING(ring, 0x00000000);
596
597 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F2, 1);
598 OUT_RING(ring, 0x00000000);
599
600 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
601 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
602 A4XX_RB_BLEND_RED_FLOAT(0.0));
603 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
604 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
605 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
606 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
607 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
608 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
609
610 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F7, 1);
611 OUT_RING(ring, 0x3f800000);
612
613 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
614 OUT_RING(ring, 0x00000000);
615
616 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
617 OUT_RING(ring, 0x00000000);
618
619 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
620 OUT_RING(ring, 0x00000000);
621
622 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
623 OUT_RING(ring, 0x00000000);
624
625 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
626 OUT_RING(ring, 0x00000000);
627
628 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
629 OUT_RING(ring, 0x00000000);
630
631 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
632 OUT_RING(ring, 0x0000001d);
633
634 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
635 OUT_RING(ring, 0x00000000);
636
637 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
638 OUT_RING(ring, 0x00000001);
639
640 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
641 OUT_RING(ring, 0x00000000);
642
643 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
644 OUT_RING(ring, 0x00000000);
645
646 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
647 OUT_RING(ring, 0x00000000);
648
649 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
650 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
651 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
652 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
653 A4XX_TPL1_TP_TEX_COUNT_GS(0));
654
655 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
656 OUT_RING(ring, 16);
657
658 /* we don't use this yet.. probably best to disable.. */
659 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
660 OUT_RING(ring, CP_SET_DRAW_STATE_0_COUNT(0) |
661 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS |
662 CP_SET_DRAW_STATE_0_GROUP_ID(0));
663 OUT_RING(ring, CP_SET_DRAW_STATE_1_ADDR(0));
664
665 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
666 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
667 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
668
669 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
670 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
671 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
672
673 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
674 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
675 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
676 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
677 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
678
679 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
680 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
681 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
682
683 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
684 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
685 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
686
687 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
688 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
689
690 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
691 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
692
693 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
694 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(0xf));
695
696 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
697 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
698
699 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
700 OUT_RING(ring, 0x0);
701
702 ctx->needs_rb_fbd = true;
703 }
704
705 void
706 fd4_emit_init(struct pipe_context *pctx)
707 {
708 struct fd_context *ctx = fd_context(pctx);
709 ctx->emit_const = fd4_emit_const;
710 ctx->emit_const_bo = fd4_emit_const_bo;
711 }