projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno/a4xx: sysvals and UBOs
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 void
51 fd4_emit_constant(struct fd_ringbuffer *ring,
52 enum adreno_state_block sb,
53 uint32_t regid, uint32_t offset, uint32_t sizedwords,
54 const uint32_t *dwords, struct pipe_resource *prsc)
55 {
56 uint32_t i, sz;
57 enum adreno_state_src src;
58
59 if (prsc) {
60 sz = 0;
61 src = 0x2; // TODO ??
62 } else {
63 sz = sizedwords;
64 src = SS_DIRECT;
65 }
66
67 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
68 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
69 CP_LOAD_STATE_0_STATE_SRC(src) |
70 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
71 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
72 if (prsc) {
73 struct fd_bo *bo = fd_resource(prsc)->bo;
74 OUT_RELOC(ring, bo, offset,
75 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
76 } else {
77 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
78 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
79 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
80 }
81 for (i = 0; i < sz; i++) {
82 OUT_RING(ring, dwords[i]);
83 }
84 }
85
86 static void
87 emit_constants(struct fd_ringbuffer *ring,
88 enum adreno_state_block sb,
89 struct fd_constbuf_stateobj *constbuf,
90 struct ir3_shader_variant *shader,
91 bool emit_immediates)
92 {
93 uint32_t enabled_mask = constbuf->enabled_mask;
94 uint32_t max_const;
95 int i;
96
97 // XXX TODO only emit dirty consts.. but we need to keep track if
98 // they are clobbered by a clear, gmem2mem, or mem2gmem..
99 constbuf->dirty_mask = enabled_mask;
100
101 /* in particular, with binning shader we may end up with unused
102 * consts, ie. we could end up w/ constlen that is smaller
103 * than first_immediate. In that case truncate the user consts
104 * early to avoid HLSQ lockup caused by writing too many consts
105 */
106 max_const = MIN2(shader->first_driver_param, shader->constlen);
107
108 /* emit user constants: */
109 if (enabled_mask & 1) {
110 const unsigned index = 0;
111 struct pipe_constant_buffer *cb = &constbuf->cb[index];
112 unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
113
114 // I expect that size should be a multiple of vec4's:
115 assert(size == align(size, 4));
116
117 /* and even if the start of the const buffer is before
118 * first_immediate, the end may not be:
119 */
120 size = MIN2(size, 4 * max_const);
121
122 if (size && (constbuf->dirty_mask & (1 << index))) {
123 fd4_emit_constant(ring, sb, 0,
124 cb->buffer_offset, size,
125 cb->user_buffer, cb->buffer);
126 constbuf->dirty_mask &= ~(1 << index);
127 }
128
129 enabled_mask &= ~(1 << index);
130 }
131
132 /* emit ubos: */
133 if (shader->constlen > shader->first_driver_param) {
134 uint32_t params = MIN2(4, shader->constlen - shader->first_driver_param);
135 OUT_PKT3(ring, CP_LOAD_STATE, 2 + params * 4);
136 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(shader->first_driver_param) |
137 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
138 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
139 CP_LOAD_STATE_0_NUM_UNIT(params));
140 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
141 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
142
143 for (i = 1; i <= params * 4; i++) {
144 struct pipe_constant_buffer *cb = &constbuf->cb[i];
145 assert(!cb->user_buffer);
146 if ((enabled_mask & (1 << i)) && cb->buffer)
147 OUT_RELOC(ring, fd_resource(cb->buffer)->bo, cb->buffer_offset, 0, 0);
148 else
149 OUT_RING(ring, 0xbad00000 | ((i - 1) << 16));
150 }
151 }
152
153 /* emit shader immediates: */
154 if (shader && emit_immediates) {
155 int size = shader->immediates_count;
156 uint32_t base = shader->first_immediate;
157
158 /* truncate size to avoid writing constants that shader
159 * does not use:
160 */
161 size = MIN2(size + base, shader->constlen) - base;
162
163 /* convert out of vec4: */
164 base *= 4;
165 size *= 4;
166
167 if (size > 0) {
168 fd4_emit_constant(ring, sb, base,
169 0, size, shader->immediates[0].val, NULL);
170 }
171 }
172 }
173
174 static void
175 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
176 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
177 {
178 unsigned i;
179
180 if (tex->num_samplers > 0) {
181 int num_samplers;
182
183 /* not sure if this is an a420.0 workaround, but we seem
184 * to need to emit these in pairs.. emit a final dummy
185 * entry if odd # of samplers:
186 */
187 num_samplers = align(tex->num_samplers, 2);
188
189 /* output sampler state: */
190 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * num_samplers));
191 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
192 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
193 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
194 CP_LOAD_STATE_0_NUM_UNIT(num_samplers));
195 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
196 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
197 for (i = 0; i < tex->num_samplers; i++) {
198 static const struct fd4_sampler_stateobj dummy_sampler = {};
199 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
200 fd4_sampler_stateobj(tex->samplers[i]) :
201 &dummy_sampler;
202 OUT_RING(ring, sampler->texsamp0);
203 OUT_RING(ring, sampler->texsamp1);
204 }
205
206 for (; i < num_samplers; i++) {
207 OUT_RING(ring, 0x00000000);
208 OUT_RING(ring, 0x00000000);
209 }
210 }
211
212 if (tex->num_textures > 0) {
213 /* emit texture state: */
214 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * tex->num_textures));
215 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
216 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
217 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
218 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
219 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
220 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
221 for (i = 0; i < tex->num_textures; i++) {
222 static const struct fd4_pipe_sampler_view dummy_view = {};
223 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
224 fd4_pipe_sampler_view(tex->textures[i]) :
225 &dummy_view;
226 struct fd_resource *rsc = fd_resource(view->base.texture);
227 unsigned start = view->base.u.tex.first_level;
228 uint32_t offset = fd_resource_offset(rsc, start, 0);
229
230 OUT_RING(ring, view->texconst0);
231 OUT_RING(ring, view->texconst1);
232 OUT_RING(ring, view->texconst2);
233 OUT_RING(ring, view->texconst3);
234 OUT_RELOC(ring, rsc->bo, offset, view->textconst4, 0);
235 OUT_RING(ring, 0x00000000);
236 OUT_RING(ring, 0x00000000);
237 OUT_RING(ring, 0x00000000);
238 }
239 }
240 }
241
242 /* emit texture state for mem->gmem restore operation.. eventually it would
243 * be good to get rid of this and use normal CSO/etc state for more of these
244 * special cases..
245 */
246 void
247 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface *psurf)
248 {
249 struct fd_resource *rsc = fd_resource(psurf->texture);
250 unsigned lvl = psurf->u.tex.level;
251 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
252 uint32_t offset = fd_resource_offset(rsc, lvl, psurf->u.tex.first_layer);
253 enum pipe_format format = fd4_gmem_restore_format(psurf->format);
254
255 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
256
257 /* output sampler state: */
258 OUT_PKT3(ring, CP_LOAD_STATE, 4);
259 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
260 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
261 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
262 CP_LOAD_STATE_0_NUM_UNIT(1));
263 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
264 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
265 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
266 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
267 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
268 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
269 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
270 OUT_RING(ring, 0x00000000);
271
272 /* emit texture state: */
273 OUT_PKT3(ring, CP_LOAD_STATE, 10);
274 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
275 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
276 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
277 CP_LOAD_STATE_0_NUM_UNIT(1));
278 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
279 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
280 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
281 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
282 fd4_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
283 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
284 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(psurf->width) |
285 A4XX_TEX_CONST_1_HEIGHT(psurf->height));
286 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp));
287 OUT_RING(ring, 0x00000000);
288 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
289 OUT_RING(ring, 0x00000000);
290 OUT_RING(ring, 0x00000000);
291 OUT_RING(ring, 0x00000000);
292 }
293
294 void
295 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
296 {
297 int32_t i, j, last = -1;
298 uint32_t total_in = 0;
299 const struct fd_vertex_state *vtx = emit->vtx;
300 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
301 unsigned vertex_regid = regid(63, 0), instance_regid = regid(63, 0);
302
303 for (i = 0; i < vp->inputs_count; i++) {
304 uint8_t semantic = sem2name(vp->inputs[i].semantic);
305 if (semantic == TGSI_SEMANTIC_VERTEXID)
306 vertex_regid = vp->inputs[i].regid;
307 else if (semantic == TGSI_SEMANTIC_INSTANCEID)
308 instance_regid = vp->inputs[i].regid;
309 else if ((i < vtx->vtx->num_elements) && vp->inputs[i].compmask)
310 last = i;
311 }
312
313 /* hw doesn't like to be configured for zero vbo's, it seems: */
314 if ((vtx->vtx->num_elements == 0) &&
315 (vertex_regid == regid(63, 0)) &&
316 (instance_regid == regid(63, 0)))
317 return;
318
319 for (i = 0, j = 0; i <= last; i++) {
320 assert(sem2name(vp->inputs[i].semantic) == 0);
321 if (vp->inputs[i].compmask) {
322 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
323 const struct pipe_vertex_buffer *vb =
324 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
325 struct fd_resource *rsc = fd_resource(vb->buffer);
326 enum pipe_format pfmt = elem->src_format;
327 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
328 bool switchnext = (i != last) ||
329 (vertex_regid != regid(63, 0)) ||
330 (instance_regid != regid(63, 0));
331 uint32_t fs = util_format_get_blocksize(pfmt);
332 uint32_t off = vb->buffer_offset + elem->src_offset;
333 uint32_t size = fd_bo_size(rsc->bo) - off;
334 debug_assert(fmt != ~0);
335
336 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
337 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
338 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
339 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
340 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
341 OUT_RELOC(ring, rsc->bo, off, 0, 0);
342 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
343 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
344
345 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
346 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
347 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
348 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
349 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
350 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
351 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
352 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
353 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
354
355 total_in += vp->inputs[i].ncomp;
356 j++;
357 }
358 }
359
360 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
361 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
362 0xa0000 | /* XXX */
363 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
364 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
365 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
366 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
367 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
368 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
369 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(regid(63, 0)));
370 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
371
372 /* cache invalidate, otherwise vertex fetch could see
373 * stale vbo contents:
374 */
375 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
376 OUT_RING(ring, 0x00000000);
377 OUT_RING(ring, 0x00000012);
378 }
379
380 void
381 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
382 struct fd4_emit *emit)
383 {
384 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
385 struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
386 uint32_t dirty = emit->dirty;
387
388 emit_marker(ring, 5);
389
390 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
391 uint32_t val = fd4_zsa_stateobj(ctx->zsa)->rb_render_control;
392
393 /* I suppose if we needed to (which I don't *think* we need
394 * to), we could emit this for binning pass too. But we
395 * would need to keep a different patch-list for binning
396 * vs render pass.
397 */
398
399 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
400 OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
401 }
402
403 if (dirty & FD_DIRTY_ZSA) {
404 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
405
406 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
407 OUT_RING(ring, zsa->rb_alpha_control);
408
409 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
410 OUT_RING(ring, zsa->rb_stencil_control);
411 OUT_RING(ring, zsa->rb_stencil_control2);
412 }
413
414 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
415 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
416 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
417
418 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
419 OUT_RING(ring, zsa->rb_stencilrefmask |
420 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
421 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
422 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
423 }
424
425 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
426 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
427 bool fragz = fp->has_kill | fp->writes_pos;
428
429 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
430 OUT_RING(ring, zsa->rb_depth_control |
431 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE));
432
433 /* maybe this register/bitfield needs a better name.. this
434 * appears to be just disabling early-z
435 */
436 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
437 OUT_RING(ring, zsa->gras_alpha_control |
438 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE));
439 }
440
441 if (dirty & FD_DIRTY_RASTERIZER) {
442 struct fd4_rasterizer_stateobj *rasterizer =
443 fd4_rasterizer_stateobj(ctx->rasterizer);
444
445 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
446 OUT_RING(ring, rasterizer->gras_su_mode_control |
447 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
448
449 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
450 OUT_RING(ring, rasterizer->gras_su_point_minmax);
451 OUT_RING(ring, rasterizer->gras_su_point_size);
452
453 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
454 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
455 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
456
457 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
458 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
459 }
460
461 /* NOTE: since primitive_restart is not actually part of any
462 * state object, we need to make sure that we always emit
463 * PRIM_VTX_CNTL.. either that or be more clever and detect
464 * when it changes.
465 */
466 if (emit->info) {
467 uint32_t val = fd4_rasterizer_stateobj(ctx->rasterizer)
468 ->pc_prim_vtx_cntl;
469
470 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
471 if (fp->total_in > 0) {
472 uint32_t varout = align(fp->total_in, 16) / 16;
473 if (varout > 1)
474 varout = align(varout, 2);
475 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
476 }
477
478 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
479 OUT_RING(ring, val);
480 OUT_RING(ring, 0x12); /* XXX UNKNOWN_21C5 */
481 }
482
483 if (dirty & FD_DIRTY_SCISSOR) {
484 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
485
486 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
487 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
488 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
489 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
490 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
491
492 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
493 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
494 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
495 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
496 }
497
498 if (dirty & FD_DIRTY_VIEWPORT) {
499 fd_wfi(ctx, ring);
500 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
501 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
502 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
503 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
504 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
505 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
506 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
507 }
508
509 if (dirty & FD_DIRTY_PROG)
510 fd4_program_emit(ring, emit);
511
512 if ((dirty & (FD_DIRTY_PROG | FD_DIRTY_CONSTBUF)) &&
513 /* evil hack to deal sanely with clear path: */
514 (emit->prog == &ctx->prog)) {
515 fd_wfi(ctx, ring);
516 emit_constants(ring, SB_VERT_SHADER,
517 &ctx->constbuf[PIPE_SHADER_VERTEX],
518 vp, emit->prog->dirty & FD_SHADER_DIRTY_VP);
519 if (!emit->key.binning_pass) {
520 emit_constants(ring, SB_FRAG_SHADER,
521 &ctx->constbuf[PIPE_SHADER_FRAGMENT],
522 fp, emit->prog->dirty & FD_SHADER_DIRTY_FP);
523 }
524 }
525
526 /* emit driver params every time */
527 if (emit->info && emit->prog == &ctx->prog) {
528 uint32_t vertex_params[4] = {
529 emit->info->indexed ? emit->info->index_bias : emit->info->start,
530 0,
531 0,
532 0
533 };
534 if (vp->constlen >= vp->first_driver_param + 4) {
535 fd4_emit_constant(ring, SB_VERT_SHADER,
536 (vp->first_driver_param + 4) * 4,
537 0, 4, vertex_params, NULL);
538 }
539 }
540
541 if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
542 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
543 uint32_t i;
544
545 for (i = 0; i < 8; i++) {
546 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
547 OUT_RING(ring, blend->rb_mrt[i].control);
548
549 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
550 OUT_RING(ring, blend->rb_mrt[i].blend_control);
551 }
552
553 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
554 OUT_RING(ring, blend->rb_fs_output |
555 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
556 }
557
558 if (dirty & FD_DIRTY_BLEND_COLOR) {
559 struct pipe_blend_color *bcolor = &ctx->blend_color;
560 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
561 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
562 A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
563 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
564 A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
565 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
566 A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
567 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
568 A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
569 }
570
571 if (dirty & FD_DIRTY_VERTTEX) {
572 if (vp->has_samp)
573 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
574 else
575 dirty &= ~FD_DIRTY_VERTTEX;
576 }
577
578 if (dirty & FD_DIRTY_FRAGTEX) {
579 if (fp->has_samp)
580 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
581 else
582 dirty &= ~FD_DIRTY_FRAGTEX;
583 }
584
585 ctx->dirty &= ~dirty;
586 }
587
588 /* emit setup at begin of new cmdstream buffer (don't rely on previous
589 * state, there could have been a context switch between ioctls):
590 */
591 void
592 fd4_emit_restore(struct fd_context *ctx)
593 {
594 struct fd4_context *fd4_ctx = fd4_context(ctx);
595 struct fd_ringbuffer *ring = ctx->ring;
596
597 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
598 OUT_RING(ring, 0x00000001);
599
600 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
601 OUT_RING(ring, 0x00000000);
602
603 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC3, 1);
604 OUT_RING(ring, 0x00000006);
605
606 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0F03, 1);
607 OUT_RING(ring, 0x0000003a);
608
609 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
610 OUT_RING(ring, 0x00000001);
611
612 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
613 OUT_RING(ring, 0x00000000);
614
615 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
616 OUT_RING(ring, 0x00000007);
617
618 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
619 OUT_RING(ring, 0x00000000);
620
621 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
622 OUT_RING(ring, 0x00000000);
623 OUT_RING(ring, 0x00000012);
624
625 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E05, 1);
626 OUT_RING(ring, 0x00000000);
627
628 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
629 OUT_RING(ring, 0x00000006);
630
631 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
632 OUT_RING(ring, 0x00000000);
633
634 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
635 OUT_RING(ring, 0x00040000);
636
637 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
638 OUT_RING(ring, 0x00000000);
639
640 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
641 OUT_RING(ring, 0x00001000);
642
643 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
644 OUT_RING(ring, 0x00000000);
645
646 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F0, 1);
647 OUT_RING(ring, 0x00000000);
648
649 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F1, 1);
650 OUT_RING(ring, 0x00000000);
651
652 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F2, 1);
653 OUT_RING(ring, 0x00000000);
654
655 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
656 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
657 A4XX_RB_BLEND_RED_FLOAT(0.0));
658 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
659 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
660 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
661 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
662 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
663 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
664
665 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F7, 1);
666 OUT_RING(ring, 0x3f800000);
667
668 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
669 OUT_RING(ring, 0x00000000);
670
671 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
672 OUT_RING(ring, 0x00000000);
673
674 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
675 OUT_RING(ring, 0x00000000);
676
677 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
678 OUT_RING(ring, 0x00000000);
679
680 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
681 OUT_RING(ring, 0x00000000);
682
683 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
684 OUT_RING(ring, 0x00000000);
685
686 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
687 OUT_RING(ring, 0x0000001d);
688
689 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
690 OUT_RING(ring, 0x00000000);
691
692 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
693 OUT_RING(ring, 0x00000001);
694
695 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
696 OUT_RING(ring, 0x00000000);
697
698 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
699 OUT_RING(ring, 0x00000000);
700
701 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
702 OUT_RING(ring, 0x00000000);
703
704 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2381, 1);
705 OUT_RING(ring, 0x00000010);
706
707 OUT_PKT0(ring, REG_A4XX_UNKNOWN_23A0, 1);
708 OUT_RING(ring, 0x00000010);
709
710 /* we don't use this yet.. probably best to disable.. */
711 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
712 OUT_RING(ring, CP_SET_DRAW_STATE_0_COUNT(0) |
713 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS |
714 CP_SET_DRAW_STATE_0_GROUP_ID(0));
715 OUT_RING(ring, CP_SET_DRAW_STATE_1_ADDR(0));
716
717 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
718 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
719 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
720
721 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
722 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
723 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
724
725 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
726 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
727 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
728 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
729 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
730
731 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
732 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
733 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
734
735 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
736 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
737 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
738
739 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
740 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
741
742 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
743 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
744
745 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL3, 1);
746 OUT_RING(ring, A4XX_RB_RENDER_CONTROL3_COMPONENT_ENABLE(0xf));
747
748 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
749 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
750
751 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
752 OUT_RING(ring, 0x0);
753
754 ctx->needs_rb_fbd = true;
755 }