1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
40 #include "fd4_context.h"
43 #include "fd4_program.h"
44 #include "fd4_format.h"
48 emit_mrt(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
49 struct pipe_surface
**bufs
, uint32_t *bases
,
50 uint32_t bin_w
, bool decode_srgb
)
52 enum a4xx_tile_mode tile_mode
;
58 tile_mode
= TILE4_LINEAR
;
61 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
62 enum a4xx_color_fmt format
= 0;
63 enum a3xx_color_swap swap
= WZYX
;
65 struct fd_resource
*rsc
= NULL
;
66 struct fd_resource_slice
*slice
= NULL
;
71 if ((i
< nr_bufs
) && bufs
[i
]) {
72 struct pipe_surface
*psurf
= bufs
[i
];
73 enum pipe_format pformat
= psurf
->format
;
75 rsc
= fd_resource(psurf
->texture
);
77 /* In case we're drawing to Z32F_S8, the "color" actually goes to
82 pformat
= rsc
->base
.format
;
87 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
88 format
= fd4_pipe2color(pformat
);
89 swap
= fd4_pipe2swap(pformat
);
92 srgb
= util_format_is_srgb(pformat
);
94 pformat
= util_format_linear(pformat
);
96 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
98 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
99 psurf
->u
.tex
.first_layer
);
102 stride
= bin_w
* rsc
->cpp
;
108 stride
= slice
->pitch
* rsc
->cpp
;
110 } else if ((i
< nr_bufs
) && bases
) {
114 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BUF_INFO(i
), 3);
115 OUT_RING(ring
, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
116 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
117 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride
) |
118 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
) |
119 COND(srgb
, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB
));
120 if (bin_w
|| (i
>= nr_bufs
) || !bufs
[i
]) {
121 OUT_RING(ring
, base
);
122 OUT_RING(ring
, A4XX_RB_MRT_CONTROL3_STRIDE(stride
));
124 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0);
125 /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
126 * not sure if we need to skip it for bypass or
129 OUT_RING(ring
, A4XX_RB_MRT_CONTROL3_STRIDE(0));
135 use_hw_binning(struct fd_batch
*batch
)
137 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
139 if ((gmem
->maxpw
* gmem
->maxph
) > 32)
142 if ((gmem
->maxpw
> 15) || (gmem
->maxph
> 15))
145 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) > 2);
148 /* transfer from gmem to system memory (ie. normal RAM) */
151 emit_gmem2mem_surf(struct fd_batch
*batch
, bool stencil
,
152 uint32_t base
, struct pipe_surface
*psurf
)
154 struct fd_ringbuffer
*ring
= batch
->gmem
;
155 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
156 enum pipe_format pformat
= psurf
->format
;
157 struct fd_resource_slice
*slice
;
161 debug_assert(rsc
->stencil
);
163 pformat
= rsc
->base
.format
;
166 slice
= &rsc
->slices
[psurf
->u
.tex
.level
];
167 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
168 psurf
->u
.tex
.first_layer
);
170 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
172 OUT_PKT0(ring
, REG_A4XX_RB_COPY_CONTROL
, 4);
173 OUT_RING(ring
, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
174 A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE
) |
175 A4XX_RB_COPY_CONTROL_GMEM_BASE(base
));
176 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* RB_COPY_DEST_BASE */
177 OUT_RING(ring
, A4XX_RB_COPY_DEST_PITCH_PITCH(slice
->pitch
* rsc
->cpp
));
178 OUT_RING(ring
, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR
) |
179 A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat
)) |
180 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
181 A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
) |
182 A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat
)));
184 fd4_draw(batch
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
185 DI_SRC_SEL_AUTO_INDEX
, 2, 1, INDEX_SIZE_IGN
, 0, 0, NULL
);
189 fd4_emit_tile_gmem2mem(struct fd_batch
*batch
, struct fd_tile
*tile
)
191 struct fd_context
*ctx
= batch
->ctx
;
192 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
193 struct fd_ringbuffer
*ring
= batch
->gmem
;
194 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
195 struct fd4_emit emit
= {
196 .debug
= &ctx
->debug
,
197 .vtx
= &ctx
->solid_vbuf_state
,
198 .prog
= &ctx
->solid_prog
,
200 .half_precision
= true,
204 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
205 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
207 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
208 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
209 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
210 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
211 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
212 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
213 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
214 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
215 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
216 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_CONTROL2 */
218 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
219 OUT_RING(ring
, 0xff000000 |
220 A4XX_RB_STENCILREFMASK_STENCILREF(0) |
221 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
222 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
223 OUT_RING(ring
, 0xff000000 |
224 A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
225 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
226 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
228 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
229 OUT_RING(ring
, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
233 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
234 OUT_RING(ring
, 0x80000); /* GRAS_CL_CLIP_CNTL */
236 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
237 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb
->width
/2.0));
238 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb
->width
/2.0));
239 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb
->height
/2.0));
240 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb
->height
/2.0));
241 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
242 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
244 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
245 OUT_RING(ring
, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
248 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
249 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
250 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
251 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
252 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
254 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 1);
255 OUT_RING(ring
, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
257 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
258 OUT_RING(ring
, 0x00000002);
260 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
261 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb
->width
- 1) |
262 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb
->height
- 1));
263 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
264 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
266 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
267 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
268 OUT_RING(ring
, 0); /* ??? UNKNOWN_2209 */
270 fd4_program_emit(ring
, &emit
, 0, NULL
);
271 fd4_emit_vertex_bufs(ring
, &emit
);
273 if (batch
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
274 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
275 if (!rsc
->stencil
|| (batch
->resolve
& FD_BUFFER_DEPTH
))
276 emit_gmem2mem_surf(batch
, false, ctx
->gmem
.zsbuf_base
[0], pfb
->zsbuf
);
277 if (rsc
->stencil
&& (batch
->resolve
& FD_BUFFER_STENCIL
))
278 emit_gmem2mem_surf(batch
, true, ctx
->gmem
.zsbuf_base
[1], pfb
->zsbuf
);
281 if (batch
->resolve
& FD_BUFFER_COLOR
) {
283 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
286 if (!(batch
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
288 emit_gmem2mem_surf(batch
, false, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
]);
292 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
293 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
294 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
295 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
296 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
299 /* transfer from system memory to gmem */
302 emit_mem2gmem_surf(struct fd_batch
*batch
, uint32_t *bases
,
303 struct pipe_surface
**bufs
, uint32_t nr_bufs
, uint32_t bin_w
)
305 struct fd_ringbuffer
*ring
= batch
->gmem
;
306 struct pipe_surface
*zsbufs
[2];
308 emit_mrt(ring
, nr_bufs
, bufs
, bases
, bin_w
, false);
310 if (bufs
[0] && (bufs
[0]->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
311 /* The gmem_restore_tex logic will put the first buffer's stencil
312 * as color. Supply it with the proper information to make that
315 zsbufs
[0] = zsbufs
[1] = bufs
[0];
320 fd4_emit_gmem_restore_tex(ring
, nr_bufs
, bufs
);
322 fd4_draw(batch
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
323 DI_SRC_SEL_AUTO_INDEX
, 2, 1, INDEX_SIZE_IGN
, 0, 0, NULL
);
327 fd4_emit_tile_mem2gmem(struct fd_batch
*batch
, struct fd_tile
*tile
)
329 struct fd_context
*ctx
= batch
->ctx
;
330 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
331 struct fd_ringbuffer
*ring
= batch
->gmem
;
332 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
333 struct fd4_emit emit
= {
334 .debug
= &ctx
->debug
,
335 .vtx
= &ctx
->blit_vbuf_state
,
336 .sprite_coord_enable
= 1,
337 /* NOTE: They all use the same VP, this is for vtx bufs. */
338 .prog
= &ctx
->blit_prog
[0],
340 .half_precision
= fd_half_precision(pfb
),
342 .no_decode_srgb
= true,
344 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
345 float x0
, y0
, x1
, y1
;
346 unsigned bin_w
= tile
->bin_w
;
347 unsigned bin_h
= tile
->bin_h
;
350 /* write texture coordinates to vertexbuf: */
351 x0
= ((float)tile
->xoff
) / ((float)pfb
->width
);
352 x1
= ((float)tile
->xoff
+ bin_w
) / ((float)pfb
->width
);
353 y0
= ((float)tile
->yoff
) / ((float)pfb
->height
);
354 y1
= ((float)tile
->yoff
+ bin_h
) / ((float)pfb
->height
);
356 OUT_PKT3(ring
, CP_MEM_WRITE
, 5);
357 OUT_RELOCW(ring
, fd_resource(ctx
->blit_texcoord_vbuf
)->bo
, 0, 0, 0);
358 OUT_RING(ring
, fui(x0
));
359 OUT_RING(ring
, fui(y0
));
360 OUT_RING(ring
, fui(x1
));
361 OUT_RING(ring
, fui(y1
));
363 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
364 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
366 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
367 OUT_RING(ring
, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
368 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
370 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
371 OUT_RING(ring
, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
372 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
373 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
374 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
375 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
376 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
));
379 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
380 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
381 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
382 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
383 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
384 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
385 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
386 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
387 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
389 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
390 OUT_RING(ring
, 0x8); /* XXX RB_RENDER_CONTROL */
392 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
393 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS
));
395 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
396 OUT_RING(ring
, 0x280000); /* XXX GRAS_CL_CLIP_CNTL */
398 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
399 OUT_RING(ring
, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
400 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
402 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
403 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w
/2.0));
404 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w
/2.0));
405 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h
/2.0));
406 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h
/2.0));
407 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
408 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
410 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
411 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w
- 1) |
412 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h
- 1));
413 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
414 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
416 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
417 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
418 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
419 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w
- 1) |
420 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h
- 1));
422 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
423 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
424 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
));
426 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
427 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
428 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
429 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
430 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
431 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS
) |
432 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
433 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
434 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
435 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_CONTROL2 */
437 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
438 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
439 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
440 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
441 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
443 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 1);
444 OUT_RING(ring
, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
|
445 A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
447 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
448 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
449 OUT_RING(ring
, 0); /* ??? UNKNOWN_2209 */
451 fd4_emit_vertex_bufs(ring
, &emit
);
453 /* for gmem pitch/base calculations, we need to use the non-
454 * truncated tile sizes:
459 if (fd_gmem_needs_restore(batch
, tile
, FD_BUFFER_COLOR
)) {
460 emit
.prog
= &ctx
->blit_prog
[pfb
->nr_cbufs
- 1];
461 emit
.fp
= NULL
; /* frag shader changed so clear cache */
462 fd4_program_emit(ring
, &emit
, pfb
->nr_cbufs
, pfb
->cbufs
);
463 emit_mem2gmem_surf(batch
, gmem
->cbuf_base
, pfb
->cbufs
, pfb
->nr_cbufs
, bin_w
);
466 if (fd_gmem_needs_restore(batch
, tile
, FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
467 switch (pfb
->zsbuf
->format
) {
468 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
469 case PIPE_FORMAT_Z32_FLOAT
:
470 emit
.prog
= (pfb
->zsbuf
->format
== PIPE_FORMAT_Z32_FLOAT
) ?
471 &ctx
->blit_z
: &ctx
->blit_zs
;
472 emit
.key
.half_precision
= false;
474 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
475 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_Z_ENABLE
|
476 A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
477 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
) |
478 A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
);
480 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
481 OUT_RING(ring
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
);
483 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
484 OUT_RING(ring
, 0x80000); /* GRAS_CL_CLIP_CNTL */
488 /* Non-float can use a regular color write. It's split over 8-bit
489 * components, so half precision is always sufficient.
491 emit
.prog
= &ctx
->blit_prog
[0];
492 emit
.key
.half_precision
= true;
495 emit
.fp
= NULL
; /* frag shader changed so clear cache */
496 fd4_program_emit(ring
, &emit
, 1, &pfb
->zsbuf
);
497 emit_mem2gmem_surf(batch
, gmem
->zsbuf_base
, &pfb
->zsbuf
, 1, bin_w
);
500 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
501 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
502 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
503 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
505 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
506 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
507 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
) |
508 0x00010000); /* XXX */
512 patch_draws(struct fd_batch
*batch
, enum pc_di_vis_cull_mode vismode
)
515 for (i
= 0; i
< fd_patch_num_elements(&batch
->draw_patches
); i
++) {
516 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->draw_patches
, i
);
517 *patch
->cs
= patch
->val
| DRAW4(0, 0, 0, vismode
);
519 util_dynarray_resize(&batch
->draw_patches
, 0);
522 /* for rendering directly to system memory: */
524 fd4_emit_sysmem_prep(struct fd_batch
*batch
)
526 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
527 struct fd_ringbuffer
*ring
= batch
->gmem
;
529 fd4_emit_restore(batch
, ring
);
531 OUT_PKT0(ring
, REG_A4XX_RB_FRAME_BUFFER_DIMENSION
, 1);
532 OUT_RING(ring
, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
533 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
535 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
, 0, true);
537 /* setup scissor/offset for current tile: */
538 OUT_PKT0(ring
, REG_A4XX_RB_BIN_OFFSET
, 1);
539 OUT_RING(ring
, A4XX_RB_BIN_OFFSET_X(0) |
540 A4XX_RB_BIN_OFFSET_Y(0));
542 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
543 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
544 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
545 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb
->width
- 1) |
546 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb
->height
- 1));
548 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
549 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(0) |
550 A4XX_RB_MODE_CONTROL_HEIGHT(0) |
551 0x00c00000); /* XXX */
553 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
556 patch_draws(batch
, IGNORE_VISIBILITY
);
560 update_vsc_pipe(struct fd_batch
*batch
)
562 struct fd_context
*ctx
= batch
->ctx
;
563 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
564 struct fd_ringbuffer
*ring
= batch
->gmem
;
567 OUT_PKT0(ring
, REG_A4XX_VSC_SIZE_ADDRESS
, 1);
568 OUT_RELOCW(ring
, fd4_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS */
570 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
571 for (i
= 0; i
< 8; i
++) {
572 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[i
];
573 OUT_RING(ring
, A4XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
574 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
575 A4XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
576 A4XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
579 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
580 for (i
= 0; i
< 8; i
++) {
581 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[i
];
583 pipe
->bo
= fd_bo_new(ctx
->dev
, 0x40000,
584 DRM_FREEDRENO_GEM_TYPE_KMEM
);
586 OUT_RELOCW(ring
, pipe
->bo
, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
589 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
590 for (i
= 0; i
< 8; i
++) {
591 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[i
];
592 OUT_RING(ring
, fd_bo_size(pipe
->bo
) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
597 emit_binning_pass(struct fd_batch
*batch
)
599 struct fd_context
*ctx
= batch
->ctx
;
600 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
601 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
602 struct fd_ringbuffer
*ring
= batch
->gmem
;
605 uint32_t x1
= gmem
->minx
;
606 uint32_t y1
= gmem
->miny
;
607 uint32_t x2
= gmem
->minx
+ gmem
->width
- 1;
608 uint32_t y2
= gmem
->miny
+ gmem
->height
- 1;
610 OUT_PKT0(ring
, REG_A4XX_PC_BINNING_COMMAND
, 1);
611 OUT_RING(ring
, A4XX_PC_BINNING_COMMAND_BINNING_ENABLE
);
613 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
614 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS
) |
615 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
616 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
617 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
619 OUT_PKT0(ring
, REG_A4XX_RB_FRAME_BUFFER_DIMENSION
, 1);
620 OUT_RING(ring
, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
621 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
623 /* setup scissor/offset for whole screen: */
624 OUT_PKT0(ring
, REG_A4XX_RB_BIN_OFFSET
, 1);
625 OUT_RING(ring
, A4XX_RB_BIN_OFFSET_X(x1
) |
626 A4XX_RB_BIN_OFFSET_Y(y1
));
628 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
629 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
630 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
631 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
632 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
634 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
635 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
636 OUT_RING(ring
, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR
) |
637 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
640 /* emit IB to binning drawcmds: */
641 ctx
->emit_ib(ring
, batch
->binning
);
646 /* and then put stuff back the way it was: */
648 OUT_PKT0(ring
, REG_A4XX_PC_BINNING_COMMAND
, 1);
649 OUT_RING(ring
, 0x00000000);
651 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
652 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
653 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
654 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
655 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
657 fd_event_write(batch
, ring
, CACHE_FLUSH
);
661 /* before first tile */
663 fd4_emit_tile_init(struct fd_batch
*batch
)
665 struct fd_ringbuffer
*ring
= batch
->gmem
;
666 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
667 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
669 fd4_emit_restore(batch
, ring
);
671 OUT_PKT0(ring
, REG_A4XX_VSC_BIN_SIZE
, 1);
672 OUT_RING(ring
, A4XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
673 A4XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
675 update_vsc_pipe(batch
);
678 OUT_PKT0(ring
, REG_A4XX_RB_FRAME_BUFFER_DIMENSION
, 1);
679 OUT_RING(ring
, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
680 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
682 if (use_hw_binning(batch
)) {
683 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
684 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
685 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
));
687 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
688 OUT_RING(ring
, A4XX_RB_RENDER_CONTROL_BINNING_PASS
|
689 A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
692 /* emit hw binning pass: */
693 emit_binning_pass(batch
);
695 patch_draws(batch
, USE_VISIBILITY
);
697 patch_draws(batch
, IGNORE_VISIBILITY
);
700 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
701 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
702 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
) |
703 A4XX_RB_MODE_CONTROL_ENABLE_GMEM
);
706 /* before mem2gmem */
708 fd4_emit_tile_prep(struct fd_batch
*batch
, struct fd_tile
*tile
)
710 struct fd_context
*ctx
= batch
->ctx
;
711 struct fd_ringbuffer
*ring
= batch
->gmem
;
712 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
713 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
716 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
717 uint32_t cpp
= rsc
->cpp
;
719 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_INFO
, 3);
720 OUT_RING(ring
, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem
->zsbuf_base
[0]) |
721 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb
->zsbuf
->format
)));
722 OUT_RING(ring
, A4XX_RB_DEPTH_PITCH(cpp
* gmem
->bin_w
));
723 OUT_RING(ring
, A4XX_RB_DEPTH_PITCH2(cpp
* gmem
->bin_w
));
725 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_INFO
, 2);
727 OUT_RING(ring
, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL
|
728 A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem
->zsbuf_base
[1]));
729 OUT_RING(ring
, A4XX_RB_STENCIL_PITCH(rsc
->stencil
->cpp
* gmem
->bin_w
));
731 OUT_RING(ring
, 0x00000000);
732 OUT_RING(ring
, 0x00000000);
735 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_INFO
, 3);
736 OUT_RING(ring
, 0x00000000);
737 OUT_RING(ring
, 0x00000000);
738 OUT_RING(ring
, 0x00000000);
740 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_INFO
, 2);
741 OUT_RING(ring
, 0); /* RB_STENCIL_INFO */
742 OUT_RING(ring
, 0); /* RB_STENCIL_PITCH */
745 OUT_PKT0(ring
, REG_A4XX_GRAS_DEPTH_CONTROL
, 1);
747 OUT_RING(ring
, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
748 fd4_pipe2depth(pfb
->zsbuf
->format
)));
750 OUT_RING(ring
, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE
));
754 /* before IB to rendering cmds: */
756 fd4_emit_tile_renderprep(struct fd_batch
*batch
, struct fd_tile
*tile
)
758 struct fd_context
*ctx
= batch
->ctx
;
759 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
760 struct fd_ringbuffer
*ring
= batch
->gmem
;
761 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
762 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
764 uint32_t x1
= tile
->xoff
;
765 uint32_t y1
= tile
->yoff
;
766 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
767 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
769 if (use_hw_binning(batch
)) {
770 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[tile
->p
];
772 assert(pipe
->w
* pipe
->h
);
774 fd_event_write(batch
, ring
, HLSQ_FLUSH
);
777 OUT_PKT0(ring
, REG_A4XX_PC_VSTREAM_CONTROL
, 1);
778 OUT_RING(ring
, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe
->w
* pipe
->h
) |
779 A4XX_PC_VSTREAM_CONTROL_N(tile
->n
));
781 OUT_PKT3(ring
, CP_SET_BIN_DATA
, 2);
782 OUT_RELOCW(ring
, pipe
->bo
, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
783 OUT_RELOCW(ring
, fd4_ctx
->vsc_size_mem
, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
784 (tile
->p
* 4), 0, 0);
786 OUT_PKT0(ring
, REG_A4XX_PC_VSTREAM_CONTROL
, 1);
787 OUT_RING(ring
, 0x00000000);
790 OUT_PKT3(ring
, CP_SET_BIN
, 3);
791 OUT_RING(ring
, 0x00000000);
792 OUT_RING(ring
, CP_SET_BIN_1_X1(x1
) | CP_SET_BIN_1_Y1(y1
));
793 OUT_RING(ring
, CP_SET_BIN_2_X2(x2
) | CP_SET_BIN_2_Y2(y2
));
795 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, gmem
->cbuf_base
, gmem
->bin_w
, true);
797 /* setup scissor/offset for current tile: */
798 OUT_PKT0(ring
, REG_A4XX_RB_BIN_OFFSET
, 1);
799 OUT_RING(ring
, A4XX_RB_BIN_OFFSET_X(tile
->xoff
) |
800 A4XX_RB_BIN_OFFSET_Y(tile
->yoff
));
802 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
803 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
804 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
805 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
806 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
808 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
813 fd4_gmem_init(struct pipe_context
*pctx
)
815 struct fd_context
*ctx
= fd_context(pctx
);
817 ctx
->emit_sysmem_prep
= fd4_emit_sysmem_prep
;
818 ctx
->emit_tile_init
= fd4_emit_tile_init
;
819 ctx
->emit_tile_prep
= fd4_emit_tile_prep
;
820 ctx
->emit_tile_mem2gmem
= fd4_emit_tile_mem2gmem
;
821 ctx
->emit_tile_renderprep
= fd4_emit_tile_renderprep
;
822 ctx
->emit_tile_gmem2mem
= fd4_emit_tile_gmem2mem
;