1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
40 #include "fd4_context.h"
43 #include "fd4_program.h"
44 #include "fd4_format.h"
48 emit_mrt(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
49 struct pipe_surface
**bufs
, uint32_t *bases
,
50 uint32_t bin_w
, bool decode_srgb
)
52 enum a4xx_tile_mode tile_mode
;
58 tile_mode
= TILE4_LINEAR
;
61 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
62 enum a4xx_color_fmt format
= 0;
63 enum a3xx_color_swap swap
= WZYX
;
65 struct fd_resource
*rsc
= NULL
;
66 struct fd_resource_slice
*slice
= NULL
;
71 if ((i
< nr_bufs
) && bufs
[i
]) {
72 struct pipe_surface
*psurf
= bufs
[i
];
73 enum pipe_format pformat
= psurf
->format
;
75 rsc
= fd_resource(psurf
->texture
);
77 /* In case we're drawing to Z32F_S8, the "color" actually goes to
82 pformat
= rsc
->base
.b
.format
;
86 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
87 format
= fd4_pipe2color(pformat
);
88 swap
= fd4_pipe2swap(pformat
);
91 srgb
= util_format_is_srgb(pformat
);
93 pformat
= util_format_linear(pformat
);
95 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
97 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
98 psurf
->u
.tex
.first_layer
);
101 stride
= bin_w
* rsc
->cpp
;
107 stride
= slice
->pitch
* rsc
->cpp
;
109 } else if ((i
< nr_bufs
) && bases
) {
113 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BUF_INFO(i
), 3);
114 OUT_RING(ring
, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
115 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
116 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride
) |
117 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
) |
118 COND(srgb
, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB
));
119 if (bin_w
|| (i
>= nr_bufs
) || !bufs
[i
]) {
120 OUT_RING(ring
, base
);
121 OUT_RING(ring
, A4XX_RB_MRT_CONTROL3_STRIDE(stride
));
123 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0);
124 /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
125 * not sure if we need to skip it for bypass or
128 OUT_RING(ring
, A4XX_RB_MRT_CONTROL3_STRIDE(0));
133 /* transfer from gmem to system memory (ie. normal RAM) */
136 emit_gmem2mem_surf(struct fd_context
*ctx
, bool stencil
,
137 uint32_t base
, struct pipe_surface
*psurf
)
139 struct fd_ringbuffer
*ring
= ctx
->ring
;
140 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
141 enum pipe_format pformat
= psurf
->format
;
142 struct fd_resource_slice
*slice
;
146 debug_assert(rsc
->stencil
);
148 pformat
= rsc
->base
.b
.format
;
151 slice
= &rsc
->slices
[psurf
->u
.tex
.level
];
152 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
153 psurf
->u
.tex
.first_layer
);
155 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
157 OUT_PKT0(ring
, REG_A4XX_RB_COPY_CONTROL
, 4);
158 OUT_RING(ring
, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
159 A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE
) |
160 A4XX_RB_COPY_CONTROL_GMEM_BASE(base
));
161 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* RB_COPY_DEST_BASE */
162 OUT_RING(ring
, A4XX_RB_COPY_DEST_PITCH_PITCH(slice
->pitch
* rsc
->cpp
));
163 OUT_RING(ring
, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR
) |
164 A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat
)) |
165 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
166 A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
) |
167 A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat
)));
169 fd4_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
170 DI_SRC_SEL_AUTO_INDEX
, 2, 1, INDEX_SIZE_IGN
, 0, 0, NULL
);
174 fd4_emit_tile_gmem2mem(struct fd_context
*ctx
, struct fd_tile
*tile
)
176 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
177 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
178 struct fd_ringbuffer
*ring
= ctx
->ring
;
179 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
180 struct fd4_emit emit
= {
181 .vtx
= &fd4_ctx
->solid_vbuf_state
,
182 .prog
= &ctx
->solid_prog
,
184 .half_precision
= true,
188 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
189 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
191 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
192 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
193 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
194 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
195 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
196 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
197 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
198 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
199 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
200 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_CONTROL2 */
202 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
203 OUT_RING(ring
, 0xff000000 |
204 A4XX_RB_STENCILREFMASK_STENCILREF(0) |
205 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
206 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
207 OUT_RING(ring
, 0xff000000 |
208 A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
209 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
210 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
212 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
213 OUT_RING(ring
, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
217 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
218 OUT_RING(ring
, 0x80000); /* GRAS_CL_CLIP_CNTL */
220 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
221 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb
->width
/2.0));
222 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb
->width
/2.0));
223 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb
->height
/2.0));
224 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb
->height
/2.0));
225 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
226 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
228 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
229 OUT_RING(ring
, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
232 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
233 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
234 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
235 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
236 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
238 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 1);
239 OUT_RING(ring
, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
241 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
242 OUT_RING(ring
, 0x00000002);
244 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
245 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb
->width
- 1) |
246 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb
->height
- 1));
247 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
248 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
250 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
251 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
252 OUT_RING(ring
, 0); /* ??? UNKNOWN_2209 */
254 fd4_program_emit(ring
, &emit
, 0, NULL
);
255 fd4_emit_vertex_bufs(ring
, &emit
);
257 if (ctx
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
258 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
259 if (!rsc
->stencil
|| (ctx
->resolve
& FD_BUFFER_DEPTH
))
260 emit_gmem2mem_surf(ctx
, false, ctx
->gmem
.zsbuf_base
[0], pfb
->zsbuf
);
261 if (rsc
->stencil
&& (ctx
->resolve
& FD_BUFFER_STENCIL
))
262 emit_gmem2mem_surf(ctx
, true, ctx
->gmem
.zsbuf_base
[1], pfb
->zsbuf
);
265 if (ctx
->resolve
& FD_BUFFER_COLOR
) {
267 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
270 if (!(ctx
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
272 emit_gmem2mem_surf(ctx
, false, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
]);
276 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
277 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
278 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
279 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
280 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
283 /* transfer from system memory to gmem */
286 emit_mem2gmem_surf(struct fd_context
*ctx
, uint32_t *bases
,
287 struct pipe_surface
**bufs
, uint32_t nr_bufs
, uint32_t bin_w
)
289 struct fd_ringbuffer
*ring
= ctx
->ring
;
290 struct pipe_surface
*zsbufs
[2];
292 emit_mrt(ring
, nr_bufs
, bufs
, bases
, bin_w
, false);
294 if (bufs
[0] && (bufs
[0]->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
295 /* The gmem_restore_tex logic will put the first buffer's stencil
296 * as color. Supply it with the proper information to make that
299 zsbufs
[0] = zsbufs
[1] = bufs
[0];
304 fd4_emit_gmem_restore_tex(ring
, nr_bufs
, bufs
);
306 fd4_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
307 DI_SRC_SEL_AUTO_INDEX
, 2, 1, INDEX_SIZE_IGN
, 0, 0, NULL
);
311 fd4_emit_tile_mem2gmem(struct fd_context
*ctx
, struct fd_tile
*tile
)
313 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
314 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
315 struct fd_ringbuffer
*ring
= ctx
->ring
;
316 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
317 struct fd4_emit emit
= {
318 .vtx
= &fd4_ctx
->blit_vbuf_state
,
319 .sprite_coord_enable
= 1,
320 /* NOTE: They all use the same VP, this is for vtx bufs. */
321 .prog
= &ctx
->blit_prog
[0],
323 .half_precision
= fd_half_precision(pfb
),
325 .no_decode_srgb
= true,
327 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
328 float x0
, y0
, x1
, y1
;
329 unsigned bin_w
= tile
->bin_w
;
330 unsigned bin_h
= tile
->bin_h
;
333 /* write texture coordinates to vertexbuf: */
334 x0
= ((float)tile
->xoff
) / ((float)pfb
->width
);
335 x1
= ((float)tile
->xoff
+ bin_w
) / ((float)pfb
->width
);
336 y0
= ((float)tile
->yoff
) / ((float)pfb
->height
);
337 y1
= ((float)tile
->yoff
+ bin_h
) / ((float)pfb
->height
);
339 OUT_PKT3(ring
, CP_MEM_WRITE
, 5);
340 OUT_RELOCW(ring
, fd_resource(fd4_ctx
->blit_texcoord_vbuf
)->bo
, 0, 0, 0);
341 OUT_RING(ring
, fui(x0
));
342 OUT_RING(ring
, fui(y0
));
343 OUT_RING(ring
, fui(x1
));
344 OUT_RING(ring
, fui(y1
));
346 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
347 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
349 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
350 OUT_RING(ring
, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
351 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
353 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
354 OUT_RING(ring
, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
355 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
356 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
357 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
358 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
359 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
));
362 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
363 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
364 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
365 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
366 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
367 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
368 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
369 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
370 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
372 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
373 OUT_RING(ring
, 0x8); /* XXX RB_RENDER_CONTROL */
375 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
376 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS
));
378 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
379 OUT_RING(ring
, 0x280000); /* XXX GRAS_CL_CLIP_CNTL */
381 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
382 OUT_RING(ring
, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
383 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
385 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
386 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w
/2.0));
387 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w
/2.0));
388 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h
/2.0));
389 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h
/2.0));
390 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
391 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
393 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
394 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w
- 1) |
395 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h
- 1));
396 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
397 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
399 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
400 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
401 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
402 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w
- 1) |
403 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h
- 1));
405 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
406 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
407 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
));
409 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
410 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
411 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
412 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
413 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
414 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS
) |
415 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
416 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
417 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
418 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_CONTROL2 */
420 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
421 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
422 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
423 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
424 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
426 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 1);
427 OUT_RING(ring
, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
|
428 A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
430 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
431 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
432 OUT_RING(ring
, 0); /* ??? UNKNOWN_2209 */
434 fd4_emit_vertex_bufs(ring
, &emit
);
436 /* for gmem pitch/base calculations, we need to use the non-
437 * truncated tile sizes:
442 if (fd_gmem_needs_restore(ctx
, tile
, FD_BUFFER_COLOR
)) {
443 emit
.prog
= &ctx
->blit_prog
[pfb
->nr_cbufs
- 1];
444 emit
.fp
= NULL
; /* frag shader changed so clear cache */
445 fd4_program_emit(ring
, &emit
, pfb
->nr_cbufs
, pfb
->cbufs
);
446 emit_mem2gmem_surf(ctx
, gmem
->cbuf_base
, pfb
->cbufs
, pfb
->nr_cbufs
, bin_w
);
449 if (fd_gmem_needs_restore(ctx
, tile
, FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
450 switch (pfb
->zsbuf
->format
) {
451 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
452 case PIPE_FORMAT_Z32_FLOAT
:
453 emit
.prog
= (pfb
->zsbuf
->format
== PIPE_FORMAT_Z32_FLOAT
) ?
454 &ctx
->blit_z
: &ctx
->blit_zs
;
455 emit
.key
.half_precision
= false;
457 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
458 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_Z_ENABLE
|
459 A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
460 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
) |
461 A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
);
463 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
464 OUT_RING(ring
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
);
466 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
467 OUT_RING(ring
, 0x80000); /* GRAS_CL_CLIP_CNTL */
471 /* Non-float can use a regular color write. It's split over 8-bit
472 * components, so half precision is always sufficient.
474 emit
.prog
= &ctx
->blit_prog
[0];
475 emit
.key
.half_precision
= true;
478 emit
.fp
= NULL
; /* frag shader changed so clear cache */
479 fd4_program_emit(ring
, &emit
, 1, &pfb
->zsbuf
);
480 emit_mem2gmem_surf(ctx
, gmem
->zsbuf_base
, &pfb
->zsbuf
, 1, bin_w
);
483 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
484 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
485 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
486 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
488 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
489 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
490 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
) |
491 0x00010000); /* XXX */
495 patch_draws(struct fd_context
*ctx
, enum pc_di_vis_cull_mode vismode
)
498 for (i
= 0; i
< fd_patch_num_elements(&ctx
->draw_patches
); i
++) {
499 struct fd_cs_patch
*patch
= fd_patch_element(&ctx
->draw_patches
, i
);
500 *patch
->cs
= patch
->val
| DRAW4(0, 0, 0, vismode
);
502 util_dynarray_resize(&ctx
->draw_patches
, 0);
506 patch_rbrc(struct fd_context
*ctx
, uint32_t val
)
508 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
510 for (i
= 0; i
< fd_patch_num_elements(&fd4_ctx
->rbrc_patches
); i
++) {
511 struct fd_cs_patch
*patch
= fd_patch_element(&fd4_ctx
->rbrc_patches
, i
);
512 *patch
->cs
= patch
->val
| val
;
514 util_dynarray_resize(&fd4_ctx
->rbrc_patches
, 0);
517 /* for rendering directly to system memory: */
519 fd4_emit_sysmem_prep(struct fd_context
*ctx
)
521 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
522 struct fd_ringbuffer
*ring
= ctx
->ring
;
524 fd4_emit_restore(ctx
);
526 OUT_PKT0(ring
, REG_A4XX_RB_FRAME_BUFFER_DIMENSION
, 1);
527 OUT_RING(ring
, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
528 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
530 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
, 0, true);
532 /* setup scissor/offset for current tile: */
533 OUT_PKT0(ring
, REG_A4XX_RB_BIN_OFFSET
, 1);
534 OUT_RING(ring
, A4XX_RB_BIN_OFFSET_X(0) |
535 A4XX_RB_BIN_OFFSET_Y(0));
537 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
538 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
539 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
540 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb
->width
- 1) |
541 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb
->height
- 1));
543 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
544 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(0) |
545 A4XX_RB_MODE_CONTROL_HEIGHT(0) |
546 0x00c00000); /* XXX */
548 patch_draws(ctx
, IGNORE_VISIBILITY
);
549 patch_rbrc(ctx
, 0); // XXX
553 update_vsc_pipe(struct fd_context
*ctx
)
555 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
556 struct fd_ringbuffer
*ring
= ctx
->ring
;
559 OUT_PKT0(ring
, REG_A4XX_VSC_SIZE_ADDRESS
, 1);
560 OUT_RELOCW(ring
, fd4_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS */
562 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
563 for (i
= 0; i
< 8; i
++) {
564 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
565 OUT_RING(ring
, A4XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
566 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
567 A4XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
568 A4XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
571 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
572 for (i
= 0; i
< 8; i
++) {
573 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
575 pipe
->bo
= fd_bo_new(ctx
->dev
, 0x40000,
576 DRM_FREEDRENO_GEM_TYPE_KMEM
);
578 OUT_RELOCW(ring
, pipe
->bo
, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
581 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
582 for (i
= 0; i
< 8; i
++) {
583 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
584 OUT_RING(ring
, fd_bo_size(pipe
->bo
) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
588 /* before first tile */
590 fd4_emit_tile_init(struct fd_context
*ctx
)
592 struct fd_ringbuffer
*ring
= ctx
->ring
;
593 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
594 uint32_t rb_render_control
;
596 fd4_emit_restore(ctx
);
598 OUT_PKT0(ring
, REG_A4XX_VSC_BIN_SIZE
, 1);
599 OUT_RING(ring
, A4XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
600 A4XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
602 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
603 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
604 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
) |
605 0x00010000); /* XXX */
607 update_vsc_pipe(ctx
);
608 patch_draws(ctx
, IGNORE_VISIBILITY
);
610 rb_render_control
= 0; // XXX or BINNING_PASS.. but maybe we can emit only from gmem
611 patch_rbrc(ctx
, rb_render_control
);
614 /* before mem2gmem */
616 fd4_emit_tile_prep(struct fd_context
*ctx
, struct fd_tile
*tile
)
618 struct fd_ringbuffer
*ring
= ctx
->ring
;
619 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
620 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
623 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
624 uint32_t cpp
= rsc
->cpp
;
626 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_INFO
, 3);
627 OUT_RING(ring
, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem
->zsbuf_base
[0]) |
628 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb
->zsbuf
->format
)));
629 OUT_RING(ring
, A4XX_RB_DEPTH_PITCH(cpp
* gmem
->bin_w
));
630 OUT_RING(ring
, A4XX_RB_DEPTH_PITCH2(cpp
* gmem
->bin_w
));
632 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_INFO
, 2);
634 OUT_RING(ring
, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL
|
635 A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem
->zsbuf_base
[1]));
636 OUT_RING(ring
, A4XX_RB_STENCIL_PITCH(rsc
->stencil
->cpp
* gmem
->bin_w
));
638 OUT_RING(ring
, 0x00000000);
639 OUT_RING(ring
, 0x00000000);
642 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_INFO
, 3);
643 OUT_RING(ring
, 0x00000000);
644 OUT_RING(ring
, 0x00000000);
645 OUT_RING(ring
, 0x00000000);
647 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_INFO
, 2);
648 OUT_RING(ring
, 0); /* RB_STENCIL_INFO */
649 OUT_RING(ring
, 0); /* RB_STENCIL_PITCH */
652 OUT_PKT0(ring
, REG_A4XX_GRAS_DEPTH_CONTROL
, 1);
654 OUT_RING(ring
, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
655 fd4_pipe2depth(pfb
->zsbuf
->format
)));
657 OUT_RING(ring
, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE
));
660 if (ctx
->needs_rb_fbd
) {
662 OUT_PKT0(ring
, REG_A4XX_RB_FRAME_BUFFER_DIMENSION
, 1);
663 OUT_RING(ring
, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
664 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
665 ctx
->needs_rb_fbd
= false;
669 /* before IB to rendering cmds: */
671 fd4_emit_tile_renderprep(struct fd_context
*ctx
, struct fd_tile
*tile
)
673 struct fd_ringbuffer
*ring
= ctx
->ring
;
674 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
675 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
677 uint32_t x1
= tile
->xoff
;
678 uint32_t y1
= tile
->yoff
;
679 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
680 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
682 OUT_PKT3(ring
, CP_SET_BIN
, 3);
683 OUT_RING(ring
, 0x00000000);
684 OUT_RING(ring
, CP_SET_BIN_1_X1(x1
) | CP_SET_BIN_1_Y1(y1
));
685 OUT_RING(ring
, CP_SET_BIN_2_X2(x2
) | CP_SET_BIN_2_Y2(y2
));
687 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, gmem
->cbuf_base
, gmem
->bin_w
, true);
689 /* setup scissor/offset for current tile: */
690 OUT_PKT0(ring
, REG_A4XX_RB_BIN_OFFSET
, 1);
691 OUT_RING(ring
, A4XX_RB_BIN_OFFSET_X(tile
->xoff
) |
692 A4XX_RB_BIN_OFFSET_Y(tile
->yoff
));
694 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
695 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
696 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
697 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
698 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
702 fd4_gmem_init(struct pipe_context
*pctx
)
704 struct fd_context
*ctx
= fd_context(pctx
);
706 ctx
->emit_sysmem_prep
= fd4_emit_sysmem_prep
;
707 ctx
->emit_tile_init
= fd4_emit_tile_init
;
708 ctx
->emit_tile_prep
= fd4_emit_tile_prep
;
709 ctx
->emit_tile_mem2gmem
= fd4_emit_tile_mem2gmem
;
710 ctx
->emit_tile_renderprep
= fd4_emit_tile_renderprep
;
711 ctx
->emit_tile_gmem2mem
= fd4_emit_tile_gmem2mem
;