1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_draw.h"
36 #include "freedreno_state.h"
37 #include "freedreno_resource.h"
40 #include "fd4_context.h"
43 #include "fd4_program.h"
47 static const struct ir3_shader_key key
= {
48 // XXX should set this based on render target format! We don't
49 // want half_precision if float32 render target!!!
50 .half_precision
= true,
54 emit_mrt(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
55 struct pipe_surface
**bufs
, uint32_t *bases
, uint32_t bin_w
)
59 for (i
= 0; i
< 8; i
++) {
60 enum a4xx_color_fmt format
= 0;
61 enum a3xx_color_swap swap
= WZYX
;
62 struct fd_resource
*rsc
= NULL
;
63 struct fd_resource_slice
*slice
= NULL
;
66 uint32_t layer_offset
= 0;
68 if ((i
< nr_bufs
) && bufs
[i
]) {
69 struct pipe_surface
*psurf
= bufs
[i
];
71 rsc
= fd_resource(psurf
->texture
);
72 slice
= &rsc
->slices
[psurf
->u
.tex
.level
];
73 format
= fd4_pipe2color(psurf
->format
);
74 swap
= fd4_pipe2swap(psurf
->format
);
76 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
78 layer_offset
= slice
->size0
* psurf
->u
.tex
.first_layer
;
81 stride
= bin_w
* rsc
->cpp
;
87 stride
= slice
->pitch
* rsc
->cpp
;
91 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BUF_INFO(i
), 3);
92 OUT_RING(ring
, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
93 0x80 | /* XXX not on gmem2mem?? tile-mode? */
94 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride
) |
95 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
));
96 if (bin_w
|| (i
>= nr_bufs
)) {
99 OUT_RELOCW(ring
, rsc
->bo
,
100 slice
->offset
+ layer_offset
, 0, -1);
102 OUT_RING(ring
, A4XX_RB_MRT_CONTROL3_STRIDE(stride
));
107 depth_base(struct fd_context
*ctx
)
109 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
110 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
113 struct fd_resource
*rsc
=
114 fd_resource(pfb
->cbufs
[0]->texture
);
117 return align(gmem
->bin_w
* gmem
->bin_h
* cpp
, 0x4000);
120 /* transfer from gmem to system memory (ie. normal RAM) */
123 emit_gmem2mem_surf(struct fd_context
*ctx
,
124 uint32_t base
, struct pipe_surface
*psurf
)
126 struct fd_ringbuffer
*ring
= ctx
->ring
;
127 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
128 struct fd_resource_slice
*slice
= &rsc
->slices
[psurf
->u
.tex
.level
];
130 OUT_PKT0(ring
, REG_A4XX_RB_COPY_CONTROL
, 4);
131 OUT_RING(ring
, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
132 A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE
) |
133 A4XX_RB_COPY_CONTROL_GMEM_BASE(base
));
134 OUT_RELOCW(ring
, rsc
->bo
, slice
->offset
, 0, 0); /* RB_COPY_DEST_BASE */
135 OUT_RING(ring
, A4XX_RB_COPY_DEST_PITCH_PITCH(slice
->pitch
* rsc
->cpp
));
136 OUT_RING(ring
, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR
) |
137 A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(psurf
->format
)) |
138 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
139 A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
) |
140 A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(psurf
->format
)));
142 fd4_draw(ctx
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
143 DI_SRC_SEL_AUTO_INDEX
, 2, INDEX_SIZE_IGN
, 0, 0, NULL
);
147 fd4_emit_tile_gmem2mem(struct fd_context
*ctx
, struct fd_tile
*tile
)
149 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
150 struct fd_ringbuffer
*ring
= ctx
->ring
;
151 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
152 struct fd4_emit emit
= {
153 .vtx
= &fd4_ctx
->solid_vbuf_state
,
154 .prog
= &ctx
->solid_prog
,
158 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
159 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
161 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 1);
162 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
163 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
164 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
165 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
166 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
167 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
168 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
169 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
171 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
172 OUT_RING(ring
, 0xff000000 |
173 A4XX_RB_STENCILREFMASK_STENCILREF(0) |
174 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
175 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
176 OUT_RING(ring
, 0xff000000 |
177 A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
178 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
179 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
181 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
182 OUT_RING(ring
, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
186 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
187 OUT_RING(ring
, 0x80000); /* GRAS_CL_CLIP_CNTL */
189 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
190 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb
->width
/2.0));
191 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb
->width
/2.0));
192 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb
->height
/2.0));
193 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb
->height
/2.0));
194 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
195 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
197 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
198 OUT_RING(ring
, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
201 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
202 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
203 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
204 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
205 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
207 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 1);
208 OUT_RING(ring
, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
210 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
211 OUT_RING(ring
, 0x00000002);
213 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
214 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb
->width
- 1) |
215 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb
->height
- 1));
216 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
217 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
219 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
220 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
221 OUT_RING(ring
, 0); /* ??? UNKNOWN_2209 */
223 fd4_program_emit(ring
, &emit
);
224 fd4_emit_vertex_bufs(ring
, &emit
);
226 if (ctx
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
227 uint32_t base
= depth_base(ctx
);
228 emit_gmem2mem_surf(ctx
, base
, pfb
->zsbuf
);
231 if (ctx
->resolve
& FD_BUFFER_COLOR
) {
232 emit_gmem2mem_surf(ctx
, 0, pfb
->cbufs
[0]);
235 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
236 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
237 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
238 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
239 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
242 /* transfer from system memory to gmem */
245 fd4_emit_tile_mem2gmem(struct fd_context
*ctx
, struct fd_tile
*tile
)
251 patch_draws(struct fd_context
*ctx
, enum pc_di_vis_cull_mode vismode
)
254 for (i
= 0; i
< fd_patch_num_elements(&ctx
->draw_patches
); i
++) {
255 struct fd_cs_patch
*patch
= fd_patch_element(&ctx
->draw_patches
, i
);
256 *patch
->cs
= patch
->val
| DRAW4(0, 0, 0, vismode
);
258 util_dynarray_resize(&ctx
->draw_patches
, 0);
262 patch_rbrc(struct fd_context
*ctx
, uint32_t val
)
264 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
266 for (i
= 0; i
< fd_patch_num_elements(&fd4_ctx
->rbrc_patches
); i
++) {
267 struct fd_cs_patch
*patch
= fd_patch_element(&fd4_ctx
->rbrc_patches
, i
);
268 *patch
->cs
= patch
->val
| val
;
270 util_dynarray_resize(&fd4_ctx
->rbrc_patches
, 0);
274 update_vsc_pipe(struct fd_context
*ctx
)
276 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
277 struct fd_ringbuffer
*ring
= ctx
->ring
;
280 OUT_PKT0(ring
, REG_A4XX_VSC_SIZE_ADDRESS
, 1);
281 OUT_RELOCW(ring
, fd4_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS */
283 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
284 for (i
= 0; i
< 8; i
++) {
285 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
286 OUT_RING(ring
, A4XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
287 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
288 A4XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
289 A4XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
292 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
293 for (i
= 0; i
< 8; i
++) {
294 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
296 pipe
->bo
= fd_bo_new(ctx
->dev
, 0x40000,
297 DRM_FREEDRENO_GEM_TYPE_KMEM
);
299 OUT_RELOCW(ring
, pipe
->bo
, 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
302 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
303 for (i
= 0; i
< 8; i
++) {
304 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
305 OUT_RING(ring
, fd_bo_size(pipe
->bo
) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
309 /* before first tile */
311 fd4_emit_tile_init(struct fd_context
*ctx
)
313 struct fd_ringbuffer
*ring
= ctx
->ring
;
314 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
315 uint32_t rb_render_control
;
317 fd4_emit_restore(ctx
);
319 OUT_PKT0(ring
, REG_A4XX_VSC_BIN_SIZE
, 1);
320 OUT_RING(ring
, A4XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
321 A4XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
323 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
324 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
325 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
) |
326 0x00010000); /* XXX */
328 update_vsc_pipe(ctx
);
329 patch_draws(ctx
, IGNORE_VISIBILITY
);
331 rb_render_control
= 0; // XXX or BINNING_PASS.. but maybe we can emit only from gmem
332 patch_rbrc(ctx
, rb_render_control
);
335 /* before mem2gmem */
337 fd4_emit_tile_prep(struct fd_context
*ctx
, struct fd_tile
*tile
)
339 struct fd_ringbuffer
*ring
= ctx
->ring
;
340 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
341 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
344 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_INFO
, 3);
345 reg
= A4XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base(ctx
));
347 reg
|= A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb
->zsbuf
->format
));
351 OUT_RING(ring
, A4XX_RB_DEPTH_PITCH(gmem
->bin_w
));
352 OUT_RING(ring
, A4XX_RB_DEPTH_PITCH2(gmem
->bin_w
));
354 OUT_RING(ring
, 0x00000000);
355 OUT_RING(ring
, 0x00000000);
359 OUT_PKT0(ring
, REG_A4XX_GRAS_DEPTH_CONTROL
, 1);
360 OUT_RING(ring
, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
361 fd_pipe2depth(pfb
->zsbuf
->format
)));
364 if (ctx
->needs_rb_fbd
) {
366 OUT_PKT0(ring
, REG_A4XX_RB_FRAME_BUFFER_DIMENSION
, 1);
367 OUT_RING(ring
, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
368 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
369 ctx
->needs_rb_fbd
= false;
373 /* before IB to rendering cmds: */
375 fd4_emit_tile_renderprep(struct fd_context
*ctx
, struct fd_tile
*tile
)
377 struct fd_ringbuffer
*ring
= ctx
->ring
;
378 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
379 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
381 uint32_t x1
= tile
->xoff
;
382 uint32_t y1
= tile
->yoff
;
383 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
384 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
386 OUT_PKT3(ring
, CP_SET_BIN
, 3);
387 OUT_RING(ring
, 0x00000000);
388 OUT_RING(ring
, CP_SET_BIN_1_X1(x1
) | CP_SET_BIN_1_Y1(y1
));
389 OUT_RING(ring
, CP_SET_BIN_2_X2(x2
) | CP_SET_BIN_2_Y2(y2
));
391 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
, gmem
->bin_w
);
393 /* setup scissor/offset for current tile: */
394 OUT_PKT0(ring
, REG_A4XX_RB_BIN_OFFSET
, 1);
395 OUT_RING(ring
, A4XX_RB_BIN_OFFSET_X(tile
->xoff
) |
396 A4XX_RB_BIN_OFFSET_Y(tile
->yoff
));
398 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
399 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
400 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
401 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
402 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
406 fd4_gmem_init(struct pipe_context
*pctx
)
408 struct fd_context
*ctx
= fd_context(pctx
);
410 ctx
->emit_tile_init
= fd4_emit_tile_init
;
411 ctx
->emit_tile_prep
= fd4_emit_tile_prep
;
412 ctx
->emit_tile_mem2gmem
= fd4_emit_tile_mem2gmem
;
413 ctx
->emit_tile_renderprep
= fd4_emit_tile_renderprep
;
414 ctx
->emit_tile_gmem2mem
= fd4_emit_tile_gmem2mem
;