src/gallium/drivers/freedreno/a4xx/fd4_gmem.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_inlines.h"
  31 #include "util/format/u_format.h"
  32
  33 #include "freedreno_draw.h"
  34 #include "freedreno_state.h"
  35 #include "freedreno_resource.h"
  36
  37 #include "fd4_gmem.h"
  38 #include "fd4_context.h"
  39 #include "fd4_draw.h"
  40 #include "fd4_emit.h"
  41 #include "fd4_program.h"
  42 #include "fd4_format.h"
  43 #include "fd4_zsa.h"
  44
  45 static void
  46 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  47                 struct pipe_surface **bufs, const uint32_t *bases,
  48                 uint32_t bin_w, bool decode_srgb)
  49 {
  50         enum a4xx_tile_mode tile_mode;
  51         unsigned i;
  52
  53         if (bin_w) {
  54                 tile_mode = 2;
  55         } else {
  56                 tile_mode = TILE4_LINEAR;
  57         }
  58
  59         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
  60                 enum a4xx_color_fmt format = 0;
  61                 enum a3xx_color_swap swap = WZYX;
  62                 bool srgb = false;
  63                 struct fd_resource *rsc = NULL;
  64                 uint32_t stride = 0;
  65                 uint32_t base = 0;
  66                 uint32_t offset = 0;
  67
  68                 if ((i < nr_bufs) && bufs[i]) {
  69                         struct pipe_surface *psurf = bufs[i];
  70                         enum pipe_format pformat = psurf->format;
  71
  72                         rsc = fd_resource(psurf->texture);
  73
  74                         /* In case we're drawing to Z32F_S8, the "color" actually goes to
  75                          * the stencil
  76                          */
  77                         if (rsc->stencil) {
  78                                 rsc = rsc->stencil;
  79                                 pformat = rsc->base.format;
  80                                 if (bases)
  81                                         bases++;
  82                         }
  83
  84                         format = fd4_pipe2color(pformat);
  85                         swap = fd4_pipe2swap(pformat);
  86
  87                         if (decode_srgb)
  88                                 srgb = util_format_is_srgb(pformat);
  89                         else
  90                                 pformat = util_format_linear(pformat);
  91
  92                         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  93
  94                         offset = fd_resource_offset(rsc, psurf->u.tex.level,
  95                                         psurf->u.tex.first_layer);
  96
  97                         if (bin_w) {
  98                                 stride = bin_w << fdl_cpp_shift(&rsc->layout);
  99
 100                                 if (bases) {
 101                                         base = bases[i];
 102                                 }
 103                         } else {
 104                                 stride = fd_resource_pitch(rsc, psurf->u.tex.level);
 105                         }
 106                 } else if ((i < nr_bufs) && bases) {
 107                         base = bases[i];
 108                 }
 109
 110                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
 111                 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
 112                                 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
 113                                 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
 114                                 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
 115                                 COND(srgb, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB));
 116                 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
 117                         OUT_RING(ring, base);
 118                         OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
 119                 } else {
 120                         OUT_RELOC(ring, rsc->bo, offset, 0, 0);
 121                         /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
 122                          * not sure if we need to skip it for bypass or
 123                          * not.
 124                          */
 125                         OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
 126                 }
 127         }
 128 }
 129
 130 static bool
 131 use_hw_binning(struct fd_batch *batch)
 132 {
 133         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 134
 135         if ((gmem->maxpw * gmem->maxph) > 32)
 136                 return false;
 137
 138         if ((gmem->maxpw > 15) || (gmem->maxph > 15))
 139                 return false;
 140
 141         return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
 142 }
 143
 144 /* transfer from gmem to system memory (ie. normal RAM) */
 145
 146 static void
 147 emit_gmem2mem_surf(struct fd_batch *batch, bool stencil,
 148                 uint32_t base, struct pipe_surface *psurf)
 149 {
 150         struct fd_ringbuffer *ring = batch->gmem;
 151         struct fd_resource *rsc = fd_resource(psurf->texture);
 152         enum pipe_format pformat = psurf->format;
 153         uint32_t offset, pitch;
 154
 155         if (!rsc->valid)
 156                 return;
 157
 158         if (stencil) {
 159                 debug_assert(rsc->stencil);
 160                 rsc = rsc->stencil;
 161                 pformat = rsc->base.format;
 162         }
 163
 164         offset = fd_resource_offset(rsc, psurf->u.tex.level,
 165                         psurf->u.tex.first_layer);
 166         pitch = fd_resource_pitch(rsc, psurf->u.tex.level);
 167
 168         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
 169
 170         OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
 171         OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
 172                         A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
 173                         A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
 174         OUT_RELOC(ring, rsc->bo, offset, 0, 0);   /* RB_COPY_DEST_BASE */
 175         OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(pitch));
 176         OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
 177                         A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat)) |
 178                         A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
 179                         A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
 180                         A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
 181
 182         fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 183                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX4_SIZE_8_BIT, 0, 0, NULL);
 184 }
 185
 186 static void
 187 fd4_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
 188 {
 189         struct fd_context *ctx = batch->ctx;
 190         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 191         struct fd_ringbuffer *ring = batch->gmem;
 192         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 193         struct fd4_emit emit = {
 194                         .debug = &ctx->debug,
 195                         .vtx = &ctx->solid_vbuf_state,
 196                         .prog = &ctx->solid_prog,
 197         };
 198
 199         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 200         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
 201
 202         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 203         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
 204                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 205                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 206                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 207                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
 208                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 209                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 210                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 211         OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 212
 213         OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
 214         OUT_RING(ring, 0xff000000 |
 215                         A4XX_RB_STENCILREFMASK_STENCILREF(0) |
 216                         A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
 217                         A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
 218         OUT_RING(ring, 0xff000000 |
 219                         A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
 220                         A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
 221                         A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
 222
 223         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 224         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
 225
 226         fd_wfi(batch, ring);
 227
 228         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 229         OUT_RING(ring, 0x80000);      /* GRAS_CL_CLIP_CNTL */
 230
 231         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 232         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width/2.0));
 233         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width/2.0));
 234         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height/2.0));
 235         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height/2.0));
 236         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 237         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 238
 239         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 240         OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 241                         0xa);       /* XXX */
 242
 243         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 244         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
 245                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 246                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 247                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 248
 249         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 250         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
 251
 252         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 253         OUT_RING(ring, 0x00000002);
 254
 255         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 256         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
 257                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
 258         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 259                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 260
 261         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 262         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 263         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 264
 265         fd4_program_emit(ring, &emit, 0, NULL);
 266         fd4_emit_vertex_bufs(ring, &emit);
 267
 268         if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 269                 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
 270                 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
 271                         emit_gmem2mem_surf(batch, false, gmem->zsbuf_base[0], pfb->zsbuf);
 272                 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
 273                         emit_gmem2mem_surf(batch, true, gmem->zsbuf_base[1], pfb->zsbuf);
 274         }
 275
 276         if (batch->resolve & FD_BUFFER_COLOR) {
 277                 unsigned i;
 278                 for (i = 0; i < pfb->nr_cbufs; i++) {
 279                         if (!pfb->cbufs[i])
 280                                 continue;
 281                         if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
 282                                 continue;
 283                         emit_gmem2mem_surf(batch, false, gmem->cbuf_base[i], pfb->cbufs[i]);
 284                 }
 285         }
 286
 287         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 288         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 289                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 290                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 291                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 292 }
 293
 294 /* transfer from system memory to gmem */
 295
 296 static void
 297 emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t *bases,
 298                 struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
 299 {
 300         struct fd_ringbuffer *ring = batch->gmem;
 301         struct pipe_surface *zsbufs[2];
 302
 303         emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
 304
 305         if (bufs[0] && (bufs[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
 306                 /* The gmem_restore_tex logic will put the first buffer's stencil
 307                  * as color. Supply it with the proper information to make that
 308                  * happen.
 309                  */
 310                 zsbufs[0] = zsbufs[1] = bufs[0];
 311                 bufs = zsbufs;
 312                 nr_bufs = 2;
 313         }
 314
 315         fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
 316
 317         fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
 318                         DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX4_SIZE_8_BIT, 0, 0, NULL);
 319 }
 320
 321 static void
 322 fd4_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
 323 {
 324         struct fd_context *ctx = batch->ctx;
 325         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 326         struct fd_ringbuffer *ring = batch->gmem;
 327         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 328         struct fd4_emit emit = {
 329                         .debug = &ctx->debug,
 330                         .vtx = &ctx->blit_vbuf_state,
 331                         .sprite_coord_enable = 1,
 332                         /* NOTE: They all use the same VP, this is for vtx bufs. */
 333                         .prog = &ctx->blit_prog[0],
 334                         .no_decode_srgb = true,
 335         };
 336         unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
 337         float x0, y0, x1, y1;
 338         unsigned bin_w = tile->bin_w;
 339         unsigned bin_h = tile->bin_h;
 340         unsigned i;
 341
 342         /* write texture coordinates to vertexbuf: */
 343         x0 = ((float)tile->xoff) / ((float)pfb->width);
 344         x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
 345         y0 = ((float)tile->yoff) / ((float)pfb->height);
 346         y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
 347
 348         OUT_PKT3(ring, CP_MEM_WRITE, 5);
 349         OUT_RELOC(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
 350         OUT_RING(ring, fui(x0));
 351         OUT_RING(ring, fui(y0));
 352         OUT_RING(ring, fui(x1));
 353         OUT_RING(ring, fui(y1));
 354
 355         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 356                 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
 357
 358                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 359                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
 360                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 361
 362                 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
 363                 OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
 364                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 365                                 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
 366                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
 367                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
 368                                 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
 369         }
 370
 371         OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
 372         OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
 373                         A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
 374                         A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
 375                         A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
 376                         A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
 377                         A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
 378                         A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
 379                         A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
 380
 381         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 382         OUT_RING(ring, 0x8);          /* XXX RB_RENDER_CONTROL */
 383
 384         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 385         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
 386
 387         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 388         OUT_RING(ring, 0x280000);     /* XXX GRAS_CL_CLIP_CNTL */
 389
 390         OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
 391         OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
 392                         A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
 393
 394         OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
 395         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w/2.0));
 396         OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w/2.0));
 397         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h/2.0));
 398         OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h/2.0));
 399         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
 400         OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
 401
 402         OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
 403         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
 404                         A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
 405         OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
 406                         A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
 407
 408         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 409         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 410                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 411         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
 412                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
 413
 414         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 415         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 416                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
 417
 418         OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
 419         OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
 420                         A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
 421                         A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
 422                         A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
 423                         A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
 424                         A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
 425                         A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
 426                         A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
 427         OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
 428
 429         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 430         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 431                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 432                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 433                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
 434
 435         OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
 436         OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
 437                         A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
 438
 439         OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
 440         OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
 441         OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
 442
 443         fd4_emit_vertex_bufs(ring, &emit);
 444
 445         /* for gmem pitch/base calculations, we need to use the non-
 446          * truncated tile sizes:
 447          */
 448         bin_w = gmem->bin_w;
 449         bin_h = gmem->bin_h;
 450
 451         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
 452                 emit.prog = &ctx->blit_prog[pfb->nr_cbufs - 1];
 453                 emit.fs = NULL;      /* frag shader changed so clear cache */
 454                 fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
 455                 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs, bin_w);
 456         }
 457
 458         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 459                 switch (pfb->zsbuf->format) {
 460                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 461                 case PIPE_FORMAT_Z32_FLOAT:
 462                         emit.prog = (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT) ?
 463                                         &ctx->blit_z : &ctx->blit_zs;
 464
 465                         OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
 466                         OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
 467                                         A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
 468                                         A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS) |
 469                                         A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE);
 470
 471                         OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
 472                         OUT_RING(ring, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE);
 473
 474                         OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
 475                         OUT_RING(ring, 0x80000);   /* GRAS_CL_CLIP_CNTL */
 476
 477                         break;
 478                 default:
 479                         /* Non-float can use a regular color write. It's split over 8-bit
 480                          * components, so half precision is always sufficient.
 481                          */
 482                         emit.prog = &ctx->blit_prog[0];
 483                         break;
 484                 }
 485                 emit.fs = NULL;      /* frag shader changed so clear cache */
 486                 fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
 487                 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
 488         }
 489
 490         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 491         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 492                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 493                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 494
 495         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 496         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 497                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 498                         0x00010000);  /* XXX */
 499 }
 500
 501 static void
 502 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
 503 {
 504         unsigned i;
 505         for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
 506                 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
 507                 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
 508         }
 509         util_dynarray_clear(&batch->draw_patches);
 510 }
 511
 512 /* for rendering directly to system memory: */
 513 static void
 514 fd4_emit_sysmem_prep(struct fd_batch *batch)
 515 {
 516         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 517         struct fd_ringbuffer *ring = batch->gmem;
 518
 519         fd4_emit_restore(batch, ring);
 520
 521         OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 522         OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 523                         A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 524
 525         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
 526
 527         /* setup scissor/offset for current tile: */
 528         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 529         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(0) |
 530                         A4XX_RB_BIN_OFFSET_Y(0));
 531
 532         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 533         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
 534                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
 535         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
 536                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
 537
 538         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 539         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(0) |
 540                         A4XX_RB_MODE_CONTROL_HEIGHT(0) |
 541                         0x00c00000);  /* XXX */
 542
 543         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 544         OUT_RING(ring, 0x8);
 545
 546         patch_draws(batch, IGNORE_VISIBILITY);
 547 }
 548
 549 static void
 550 update_vsc_pipe(struct fd_batch *batch)
 551 {
 552         struct fd_context *ctx = batch->ctx;
 553         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 554         struct fd4_context *fd4_ctx = fd4_context(ctx);
 555         struct fd_ringbuffer *ring = batch->gmem;
 556         int i;
 557
 558         OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
 559         OUT_RELOC(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
 560
 561         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
 562         for (i = 0; i < 8; i++) {
 563                 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
 564                 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
 565                                 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
 566                                 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
 567                                 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
 568         }
 569
 570         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
 571         for (i = 0; i < 8; i++) {
 572                 if (!ctx->vsc_pipe_bo[i]) {
 573                         ctx->vsc_pipe_bo[i] = fd_bo_new(ctx->dev, 0x40000,
 574                                         DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
 575                 }
 576                 OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0, 0);       /* VSC_PIPE_DATA_ADDRESS[i] */
 577         }
 578
 579         OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
 580         for (i = 0; i < 8; i++) {
 581                 OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
 582         }
 583 }
 584
 585 static void
 586 emit_binning_pass(struct fd_batch *batch)
 587 {
 588         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 589         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 590         struct fd_ringbuffer *ring = batch->gmem;
 591         int i;
 592
 593         uint32_t x1 = gmem->minx;
 594         uint32_t y1 = gmem->miny;
 595         uint32_t x2 = gmem->minx + gmem->width - 1;
 596         uint32_t y2 = gmem->miny + gmem->height - 1;
 597
 598         OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
 599         OUT_RING(ring, A4XX_PC_BINNING_COMMAND_BINNING_ENABLE);
 600
 601         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 602         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
 603                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 604                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 605                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 606
 607         OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 608         OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 609                         A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 610
 611         /* setup scissor/offset for whole screen: */
 612         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 613         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(x1) |
 614                         A4XX_RB_BIN_OFFSET_Y(y1));
 615
 616         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 617         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 618                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 619         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 620                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 621
 622         for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
 623                 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
 624                 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
 625                                 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
 626         }
 627
 628         /* emit IB to binning drawcmds: */
 629         fd4_emit_ib(ring, batch->binning);
 630
 631         fd_reset_wfi(batch);
 632         fd_wfi(batch, ring);
 633
 634         /* and then put stuff back the way it was: */
 635
 636         OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
 637         OUT_RING(ring, 0x00000000);
 638
 639         OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
 640         OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
 641                         A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
 642                         A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
 643                         A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
 644
 645         fd_event_write(batch, ring, CACHE_FLUSH);
 646         fd_wfi(batch, ring);
 647 }
 648
 649 /* before first tile */
 650 static void
 651 fd4_emit_tile_init(struct fd_batch *batch)
 652 {
 653         struct fd_ringbuffer *ring = batch->gmem;
 654         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 655         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 656
 657         fd4_emit_restore(batch, ring);
 658
 659         OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
 660         OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 661                         A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 662
 663         update_vsc_pipe(batch);
 664
 665         fd_wfi(batch, ring);
 666         OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
 667         OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
 668                         A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
 669
 670         if (use_hw_binning(batch)) {
 671                 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 672                 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 673                                 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
 674
 675                 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 676                 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_BINNING_PASS |
 677                                 A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
 678                                 0x8);
 679
 680                 /* emit hw binning pass: */
 681                 emit_binning_pass(batch);
 682
 683                 patch_draws(batch, USE_VISIBILITY);
 684         } else {
 685                 patch_draws(batch, IGNORE_VISIBILITY);
 686         }
 687
 688         OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
 689         OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
 690                         A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
 691                         A4XX_RB_MODE_CONTROL_ENABLE_GMEM);
 692 }
 693
 694 /* before mem2gmem */
 695 static void
 696 fd4_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
 697 {
 698         struct fd_ringbuffer *ring = batch->gmem;
 699         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 700         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 701
 702         if (pfb->zsbuf) {
 703                 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
 704                 uint32_t cpp = rsc->layout.cpp;
 705
 706                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
 707                 OUT_RING(ring, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]) |
 708                                 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb->zsbuf->format)));
 709                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
 710                 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
 711
 712                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
 713                 if (rsc->stencil) {
 714                         OUT_RING(ring, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL |
 715                                         A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
 716                         OUT_RING(ring, A4XX_RB_STENCIL_PITCH(rsc->stencil->layout.cpp * gmem->bin_w));
 717                 } else {
 718                         OUT_RING(ring, 0x00000000);
 719                         OUT_RING(ring, 0x00000000);
 720                 }
 721         } else {
 722                 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
 723                 OUT_RING(ring, 0x00000000);
 724                 OUT_RING(ring, 0x00000000);
 725                 OUT_RING(ring, 0x00000000);
 726
 727                 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
 728                 OUT_RING(ring, 0);            /* RB_STENCIL_INFO */
 729                 OUT_RING(ring, 0);            /* RB_STENCIL_PITCH */
 730         }
 731
 732         OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
 733         if (pfb->zsbuf) {
 734                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
 735                                 fd4_pipe2depth(pfb->zsbuf->format)));
 736         } else {
 737                 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
 738         }
 739 }
 740
 741 /* before IB to rendering cmds: */
 742 static void
 743 fd4_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
 744 {
 745         struct fd_context *ctx = batch->ctx;
 746         struct fd4_context *fd4_ctx = fd4_context(ctx);
 747         struct fd_ringbuffer *ring = batch->gmem;
 748         const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 749         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 750
 751         uint32_t x1 = tile->xoff;
 752         uint32_t y1 = tile->yoff;
 753         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 754         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 755
 756         if (use_hw_binning(batch)) {
 757                 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
 758                 struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
 759
 760                 assert(pipe->w && pipe->h);
 761
 762                 fd_event_write(batch, ring, HLSQ_FLUSH);
 763                 fd_wfi(batch, ring);
 764
 765                 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
 766                 OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
 767                                 A4XX_PC_VSTREAM_CONTROL_N(tile->n));
 768
 769                 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
 770                 OUT_RELOC(ring, pipe_bo, 0, 0, 0);     /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
 771                 OUT_RELOC(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
 772                                 (tile->p * 4), 0, 0);
 773         } else {
 774                 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
 775                 OUT_RING(ring, 0x00000000);
 776         }
 777
 778         OUT_PKT3(ring, CP_SET_BIN, 3);
 779         OUT_RING(ring, 0x00000000);
 780         OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
 781         OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
 782
 783         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w, true);
 784
 785         /* setup scissor/offset for current tile: */
 786         OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
 787         OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
 788                         A4XX_RB_BIN_OFFSET_Y(tile->yoff));
 789
 790         OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
 791         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
 792                         A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
 793         OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
 794                         A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
 795
 796         OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
 797         OUT_RING(ring, 0x8);
 798 }
 799
 800 void
 801 fd4_gmem_init(struct pipe_context *pctx)
 802 {
 803         struct fd_context *ctx = fd_context(pctx);
 804
 805         ctx->emit_sysmem_prep = fd4_emit_sysmem_prep;
 806         ctx->emit_tile_init = fd4_emit_tile_init;
 807         ctx->emit_tile_prep = fd4_emit_tile_prep;
 808         ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
 809         ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
 810         ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
 811 }