2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
33 #include "freedreno_draw.h"
34 #include "freedreno_state.h"
35 #include "freedreno_resource.h"
38 #include "fd4_context.h"
41 #include "fd4_program.h"
42 #include "fd4_format.h"
46 emit_mrt(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
47 struct pipe_surface
**bufs
, uint32_t *bases
,
48 uint32_t bin_w
, bool decode_srgb
)
50 enum a4xx_tile_mode tile_mode
;
56 tile_mode
= TILE4_LINEAR
;
59 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
60 enum a4xx_color_fmt format
= 0;
61 enum a3xx_color_swap swap
= WZYX
;
63 struct fd_resource
*rsc
= NULL
;
64 struct fdl_slice
*slice
= NULL
;
69 if ((i
< nr_bufs
) && bufs
[i
]) {
70 struct pipe_surface
*psurf
= bufs
[i
];
71 enum pipe_format pformat
= psurf
->format
;
73 rsc
= fd_resource(psurf
->texture
);
75 /* In case we're drawing to Z32F_S8, the "color" actually goes to
80 pformat
= rsc
->base
.format
;
85 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
86 format
= fd4_pipe2color(pformat
);
87 swap
= fd4_pipe2swap(pformat
);
90 srgb
= util_format_is_srgb(pformat
);
92 pformat
= util_format_linear(pformat
);
94 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
96 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
97 psurf
->u
.tex
.first_layer
);
100 stride
= bin_w
* rsc
->layout
.cpp
;
106 stride
= slice
->pitch
* rsc
->layout
.cpp
;
108 } else if ((i
< nr_bufs
) && bases
) {
112 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BUF_INFO(i
), 3);
113 OUT_RING(ring
, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
114 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
115 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride
) |
116 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
) |
117 COND(srgb
, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB
));
118 if (bin_w
|| (i
>= nr_bufs
) || !bufs
[i
]) {
119 OUT_RING(ring
, base
);
120 OUT_RING(ring
, A4XX_RB_MRT_CONTROL3_STRIDE(stride
));
122 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0);
123 /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
124 * not sure if we need to skip it for bypass or
127 OUT_RING(ring
, A4XX_RB_MRT_CONTROL3_STRIDE(0));
133 use_hw_binning(struct fd_batch
*batch
)
135 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
137 if ((gmem
->maxpw
* gmem
->maxph
) > 32)
140 if ((gmem
->maxpw
> 15) || (gmem
->maxph
> 15))
143 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) > 2);
146 /* transfer from gmem to system memory (ie. normal RAM) */
149 emit_gmem2mem_surf(struct fd_batch
*batch
, bool stencil
,
150 uint32_t base
, struct pipe_surface
*psurf
)
152 struct fd_ringbuffer
*ring
= batch
->gmem
;
153 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
154 enum pipe_format pformat
= psurf
->format
;
155 struct fdl_slice
*slice
;
162 debug_assert(rsc
->stencil
);
164 pformat
= rsc
->base
.format
;
167 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
168 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
169 psurf
->u
.tex
.first_layer
);
171 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
173 OUT_PKT0(ring
, REG_A4XX_RB_COPY_CONTROL
, 4);
174 OUT_RING(ring
, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE
) |
175 A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE
) |
176 A4XX_RB_COPY_CONTROL_GMEM_BASE(base
));
177 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* RB_COPY_DEST_BASE */
178 OUT_RING(ring
, A4XX_RB_COPY_DEST_PITCH_PITCH(slice
->pitch
* rsc
->layout
.cpp
));
179 OUT_RING(ring
, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR
) |
180 A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat
)) |
181 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
182 A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE
) |
183 A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat
)));
185 fd4_draw(batch
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
186 DI_SRC_SEL_AUTO_INDEX
, 2, 1, INDEX4_SIZE_8_BIT
, 0, 0, NULL
);
190 fd4_emit_tile_gmem2mem(struct fd_batch
*batch
, const struct fd_tile
*tile
)
192 struct fd_context
*ctx
= batch
->ctx
;
193 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
194 struct fd_ringbuffer
*ring
= batch
->gmem
;
195 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
196 struct fd4_emit emit
= {
197 .debug
= &ctx
->debug
,
198 .vtx
= &ctx
->solid_vbuf_state
,
199 .prog
= &ctx
->solid_prog
,
201 .half_precision
= true,
205 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
206 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER
));
208 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
209 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER
) |
210 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
211 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
212 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
213 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER
) |
214 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
215 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
216 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
217 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_CONTROL2 */
219 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
220 OUT_RING(ring
, 0xff000000 |
221 A4XX_RB_STENCILREFMASK_STENCILREF(0) |
222 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
223 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
224 OUT_RING(ring
, 0xff000000 |
225 A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
226 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
227 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
229 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
230 OUT_RING(ring
, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
234 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
235 OUT_RING(ring
, 0x80000); /* GRAS_CL_CLIP_CNTL */
237 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
238 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb
->width
/2.0));
239 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb
->width
/2.0));
240 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb
->height
/2.0));
241 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb
->height
/2.0));
242 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
243 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
245 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
246 OUT_RING(ring
, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
249 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
250 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS
) |
251 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
252 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
253 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
255 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 1);
256 OUT_RING(ring
, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
);
258 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
259 OUT_RING(ring
, 0x00000002);
261 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
262 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb
->width
- 1) |
263 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb
->height
- 1));
264 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
265 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
267 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
268 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
269 OUT_RING(ring
, 0); /* ??? UNKNOWN_2209 */
271 fd4_program_emit(ring
, &emit
, 0, NULL
);
272 fd4_emit_vertex_bufs(ring
, &emit
);
274 if (batch
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
275 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
276 if (!rsc
->stencil
|| (batch
->resolve
& FD_BUFFER_DEPTH
))
277 emit_gmem2mem_surf(batch
, false, ctx
->gmem
.zsbuf_base
[0], pfb
->zsbuf
);
278 if (rsc
->stencil
&& (batch
->resolve
& FD_BUFFER_STENCIL
))
279 emit_gmem2mem_surf(batch
, true, ctx
->gmem
.zsbuf_base
[1], pfb
->zsbuf
);
282 if (batch
->resolve
& FD_BUFFER_COLOR
) {
284 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
287 if (!(batch
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
289 emit_gmem2mem_surf(batch
, false, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
]);
293 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
294 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
295 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
296 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
297 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
300 /* transfer from system memory to gmem */
303 emit_mem2gmem_surf(struct fd_batch
*batch
, uint32_t *bases
,
304 struct pipe_surface
**bufs
, uint32_t nr_bufs
, uint32_t bin_w
)
306 struct fd_ringbuffer
*ring
= batch
->gmem
;
307 struct pipe_surface
*zsbufs
[2];
309 emit_mrt(ring
, nr_bufs
, bufs
, bases
, bin_w
, false);
311 if (bufs
[0] && (bufs
[0]->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
312 /* The gmem_restore_tex logic will put the first buffer's stencil
313 * as color. Supply it with the proper information to make that
316 zsbufs
[0] = zsbufs
[1] = bufs
[0];
321 fd4_emit_gmem_restore_tex(ring
, nr_bufs
, bufs
);
323 fd4_draw(batch
, ring
, DI_PT_RECTLIST
, IGNORE_VISIBILITY
,
324 DI_SRC_SEL_AUTO_INDEX
, 2, 1, INDEX4_SIZE_8_BIT
, 0, 0, NULL
);
328 fd4_emit_tile_mem2gmem(struct fd_batch
*batch
, const struct fd_tile
*tile
)
330 struct fd_context
*ctx
= batch
->ctx
;
331 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
332 struct fd_ringbuffer
*ring
= batch
->gmem
;
333 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
334 struct fd4_emit emit
= {
335 .debug
= &ctx
->debug
,
336 .vtx
= &ctx
->blit_vbuf_state
,
337 .sprite_coord_enable
= 1,
338 /* NOTE: They all use the same VP, this is for vtx bufs. */
339 .prog
= &ctx
->blit_prog
[0],
341 .half_precision
= fd_half_precision(pfb
),
343 .no_decode_srgb
= true,
345 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
346 float x0
, y0
, x1
, y1
;
347 unsigned bin_w
= tile
->bin_w
;
348 unsigned bin_h
= tile
->bin_h
;
351 /* write texture coordinates to vertexbuf: */
352 x0
= ((float)tile
->xoff
) / ((float)pfb
->width
);
353 x1
= ((float)tile
->xoff
+ bin_w
) / ((float)pfb
->width
);
354 y0
= ((float)tile
->yoff
) / ((float)pfb
->height
);
355 y1
= ((float)tile
->yoff
+ bin_h
) / ((float)pfb
->height
);
357 OUT_PKT3(ring
, CP_MEM_WRITE
, 5);
358 OUT_RELOCW(ring
, fd_resource(ctx
->blit_texcoord_vbuf
)->bo
, 0, 0, 0);
359 OUT_RING(ring
, fui(x0
));
360 OUT_RING(ring
, fui(y0
));
361 OUT_RING(ring
, fui(x1
));
362 OUT_RING(ring
, fui(y1
));
364 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
365 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
367 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
368 OUT_RING(ring
, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
) |
369 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
371 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
372 OUT_RING(ring
, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE
) |
373 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
374 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO
) |
375 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE
) |
376 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC
) |
377 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO
));
380 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
381 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
382 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
383 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
384 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
385 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
386 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
387 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
388 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
390 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
391 OUT_RING(ring
, 0x8); /* XXX RB_RENDER_CONTROL */
393 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
394 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS
));
396 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
397 OUT_RING(ring
, 0x280000); /* XXX GRAS_CL_CLIP_CNTL */
399 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
400 OUT_RING(ring
, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
401 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
403 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
404 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w
/2.0));
405 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w
/2.0));
406 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h
/2.0));
407 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h
/2.0));
408 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
409 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
411 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
412 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w
- 1) |
413 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h
- 1));
414 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
415 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
417 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
418 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
419 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
420 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w
- 1) |
421 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h
- 1));
423 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
424 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
425 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
));
427 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
428 OUT_RING(ring
, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS
) |
429 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP
) |
430 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP
) |
431 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP
) |
432 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS
) |
433 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP
) |
434 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP
) |
435 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP
));
436 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_CONTROL2 */
438 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
439 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
440 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
441 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
442 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
444 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 1);
445 OUT_RING(ring
, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST
|
446 A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
448 OUT_PKT0(ring
, REG_A4XX_VFD_INDEX_OFFSET
, 2);
449 OUT_RING(ring
, 0); /* VFD_INDEX_OFFSET */
450 OUT_RING(ring
, 0); /* ??? UNKNOWN_2209 */
452 fd4_emit_vertex_bufs(ring
, &emit
);
454 /* for gmem pitch/base calculations, we need to use the non-
455 * truncated tile sizes:
460 if (fd_gmem_needs_restore(batch
, tile
, FD_BUFFER_COLOR
)) {
461 emit
.prog
= &ctx
->blit_prog
[pfb
->nr_cbufs
- 1];
462 emit
.fs
= NULL
; /* frag shader changed so clear cache */
463 fd4_program_emit(ring
, &emit
, pfb
->nr_cbufs
, pfb
->cbufs
);
464 emit_mem2gmem_surf(batch
, gmem
->cbuf_base
, pfb
->cbufs
, pfb
->nr_cbufs
, bin_w
);
467 if (fd_gmem_needs_restore(batch
, tile
, FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
468 switch (pfb
->zsbuf
->format
) {
469 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
470 case PIPE_FORMAT_Z32_FLOAT
:
471 emit
.prog
= (pfb
->zsbuf
->format
== PIPE_FORMAT_Z32_FLOAT
) ?
472 &ctx
->blit_z
: &ctx
->blit_zs
;
473 emit
.key
.half_precision
= false;
475 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
476 OUT_RING(ring
, A4XX_RB_DEPTH_CONTROL_Z_ENABLE
|
477 A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE
|
478 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS
) |
479 A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
);
481 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
482 OUT_RING(ring
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
);
484 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
485 OUT_RING(ring
, 0x80000); /* GRAS_CL_CLIP_CNTL */
489 /* Non-float can use a regular color write. It's split over 8-bit
490 * components, so half precision is always sufficient.
492 emit
.prog
= &ctx
->blit_prog
[0];
493 emit
.key
.half_precision
= true;
496 emit
.fs
= NULL
; /* frag shader changed so clear cache */
497 fd4_program_emit(ring
, &emit
, 1, &pfb
->zsbuf
);
498 emit_mem2gmem_surf(batch
, gmem
->zsbuf_base
, &pfb
->zsbuf
, 1, bin_w
);
501 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
502 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
503 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
504 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
506 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
507 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
508 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
) |
509 0x00010000); /* XXX */
513 patch_draws(struct fd_batch
*batch
, enum pc_di_vis_cull_mode vismode
)
516 for (i
= 0; i
< fd_patch_num_elements(&batch
->draw_patches
); i
++) {
517 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->draw_patches
, i
);
518 *patch
->cs
= patch
->val
| DRAW4(0, 0, 0, vismode
);
520 util_dynarray_clear(&batch
->draw_patches
);
523 /* for rendering directly to system memory: */
525 fd4_emit_sysmem_prep(struct fd_batch
*batch
)
527 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
528 struct fd_ringbuffer
*ring
= batch
->gmem
;
530 fd4_emit_restore(batch
, ring
);
532 OUT_PKT0(ring
, REG_A4XX_RB_FRAME_BUFFER_DIMENSION
, 1);
533 OUT_RING(ring
, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
534 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
536 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, NULL
, 0, true);
538 /* setup scissor/offset for current tile: */
539 OUT_PKT0(ring
, REG_A4XX_RB_BIN_OFFSET
, 1);
540 OUT_RING(ring
, A4XX_RB_BIN_OFFSET_X(0) |
541 A4XX_RB_BIN_OFFSET_Y(0));
543 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
544 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
545 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
546 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb
->width
- 1) |
547 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb
->height
- 1));
549 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
550 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(0) |
551 A4XX_RB_MODE_CONTROL_HEIGHT(0) |
552 0x00c00000); /* XXX */
554 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
557 patch_draws(batch
, IGNORE_VISIBILITY
);
561 update_vsc_pipe(struct fd_batch
*batch
)
563 struct fd_context
*ctx
= batch
->ctx
;
564 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
565 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
566 struct fd_ringbuffer
*ring
= batch
->gmem
;
569 OUT_PKT0(ring
, REG_A4XX_VSC_SIZE_ADDRESS
, 1);
570 OUT_RELOCW(ring
, fd4_ctx
->vsc_size_mem
, 0, 0, 0); /* VSC_SIZE_ADDRESS */
572 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
573 for (i
= 0; i
< 8; i
++) {
574 const struct fd_vsc_pipe
*pipe
= &gmem
->vsc_pipe
[i
];
575 OUT_RING(ring
, A4XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
576 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
577 A4XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
578 A4XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
581 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
582 for (i
= 0; i
< 8; i
++) {
583 if (!ctx
->vsc_pipe_bo
[i
]) {
584 ctx
->vsc_pipe_bo
[i
] = fd_bo_new(ctx
->dev
, 0x40000,
585 DRM_FREEDRENO_GEM_TYPE_KMEM
, "vsc_pipe[%u]", i
);
587 OUT_RELOCW(ring
, ctx
->vsc_pipe_bo
[i
], 0, 0, 0); /* VSC_PIPE_DATA_ADDRESS[i] */
590 OUT_PKT0(ring
, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
591 for (i
= 0; i
< 8; i
++) {
592 OUT_RING(ring
, fd_bo_size(ctx
->vsc_pipe_bo
[i
]) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
597 emit_binning_pass(struct fd_batch
*batch
)
599 struct fd_context
*ctx
= batch
->ctx
;
600 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
601 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
602 struct fd_ringbuffer
*ring
= batch
->gmem
;
605 uint32_t x1
= gmem
->minx
;
606 uint32_t y1
= gmem
->miny
;
607 uint32_t x2
= gmem
->minx
+ gmem
->width
- 1;
608 uint32_t y2
= gmem
->miny
+ gmem
->height
- 1;
610 OUT_PKT0(ring
, REG_A4XX_PC_BINNING_COMMAND
, 1);
611 OUT_RING(ring
, A4XX_PC_BINNING_COMMAND_BINNING_ENABLE
);
613 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
614 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS
) |
615 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
616 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
617 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
619 OUT_PKT0(ring
, REG_A4XX_RB_FRAME_BUFFER_DIMENSION
, 1);
620 OUT_RING(ring
, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
621 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
623 /* setup scissor/offset for whole screen: */
624 OUT_PKT0(ring
, REG_A4XX_RB_BIN_OFFSET
, 1);
625 OUT_RING(ring
, A4XX_RB_BIN_OFFSET_X(x1
) |
626 A4XX_RB_BIN_OFFSET_Y(y1
));
628 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
629 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
630 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
631 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
632 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
634 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
635 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
636 OUT_RING(ring
, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR
) |
637 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
640 /* emit IB to binning drawcmds: */
641 fd4_emit_ib(ring
, batch
->binning
);
646 /* and then put stuff back the way it was: */
648 OUT_PKT0(ring
, REG_A4XX_PC_BINNING_COMMAND
, 1);
649 OUT_RING(ring
, 0x00000000);
651 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
652 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
653 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
654 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
655 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
657 fd_event_write(batch
, ring
, CACHE_FLUSH
);
661 /* before first tile */
663 fd4_emit_tile_init(struct fd_batch
*batch
)
665 struct fd_ringbuffer
*ring
= batch
->gmem
;
666 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
667 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
669 fd4_emit_restore(batch
, ring
);
671 OUT_PKT0(ring
, REG_A4XX_VSC_BIN_SIZE
, 1);
672 OUT_RING(ring
, A4XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
673 A4XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
675 update_vsc_pipe(batch
);
678 OUT_PKT0(ring
, REG_A4XX_RB_FRAME_BUFFER_DIMENSION
, 1);
679 OUT_RING(ring
, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb
->width
) |
680 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb
->height
));
682 if (use_hw_binning(batch
)) {
683 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
684 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
685 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
));
687 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
688 OUT_RING(ring
, A4XX_RB_RENDER_CONTROL_BINNING_PASS
|
689 A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE
|
692 /* emit hw binning pass: */
693 emit_binning_pass(batch
);
695 patch_draws(batch
, USE_VISIBILITY
);
697 patch_draws(batch
, IGNORE_VISIBILITY
);
700 OUT_PKT0(ring
, REG_A4XX_RB_MODE_CONTROL
, 1);
701 OUT_RING(ring
, A4XX_RB_MODE_CONTROL_WIDTH(gmem
->bin_w
) |
702 A4XX_RB_MODE_CONTROL_HEIGHT(gmem
->bin_h
) |
703 A4XX_RB_MODE_CONTROL_ENABLE_GMEM
);
706 /* before mem2gmem */
708 fd4_emit_tile_prep(struct fd_batch
*batch
, const struct fd_tile
*tile
)
710 struct fd_context
*ctx
= batch
->ctx
;
711 struct fd_ringbuffer
*ring
= batch
->gmem
;
712 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
713 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
716 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
717 uint32_t cpp
= rsc
->layout
.cpp
;
719 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_INFO
, 3);
720 OUT_RING(ring
, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem
->zsbuf_base
[0]) |
721 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd4_pipe2depth(pfb
->zsbuf
->format
)));
722 OUT_RING(ring
, A4XX_RB_DEPTH_PITCH(cpp
* gmem
->bin_w
));
723 OUT_RING(ring
, A4XX_RB_DEPTH_PITCH2(cpp
* gmem
->bin_w
));
725 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_INFO
, 2);
727 OUT_RING(ring
, A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL
|
728 A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem
->zsbuf_base
[1]));
729 OUT_RING(ring
, A4XX_RB_STENCIL_PITCH(rsc
->stencil
->layout
.cpp
* gmem
->bin_w
));
731 OUT_RING(ring
, 0x00000000);
732 OUT_RING(ring
, 0x00000000);
735 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_INFO
, 3);
736 OUT_RING(ring
, 0x00000000);
737 OUT_RING(ring
, 0x00000000);
738 OUT_RING(ring
, 0x00000000);
740 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_INFO
, 2);
741 OUT_RING(ring
, 0); /* RB_STENCIL_INFO */
742 OUT_RING(ring
, 0); /* RB_STENCIL_PITCH */
745 OUT_PKT0(ring
, REG_A4XX_GRAS_DEPTH_CONTROL
, 1);
747 OUT_RING(ring
, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
748 fd4_pipe2depth(pfb
->zsbuf
->format
)));
750 OUT_RING(ring
, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE
));
754 /* before IB to rendering cmds: */
756 fd4_emit_tile_renderprep(struct fd_batch
*batch
, const struct fd_tile
*tile
)
758 struct fd_context
*ctx
= batch
->ctx
;
759 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
760 struct fd_ringbuffer
*ring
= batch
->gmem
;
761 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
762 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
764 uint32_t x1
= tile
->xoff
;
765 uint32_t y1
= tile
->yoff
;
766 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
767 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
769 if (use_hw_binning(batch
)) {
770 const struct fd_vsc_pipe
*pipe
= &gmem
->vsc_pipe
[tile
->p
];
771 struct fd_bo
*pipe_bo
= ctx
->vsc_pipe_bo
[tile
->p
];
773 assert(pipe
->w
&& pipe
->h
);
775 fd_event_write(batch
, ring
, HLSQ_FLUSH
);
778 OUT_PKT0(ring
, REG_A4XX_PC_VSTREAM_CONTROL
, 1);
779 OUT_RING(ring
, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe
->w
* pipe
->h
) |
780 A4XX_PC_VSTREAM_CONTROL_N(tile
->n
));
782 OUT_PKT3(ring
, CP_SET_BIN_DATA
, 2);
783 OUT_RELOCW(ring
, pipe_bo
, 0, 0, 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
784 OUT_RELOCW(ring
, fd4_ctx
->vsc_size_mem
, /* BIN_SIZE_ADDR <- VSC_SIZE_ADDRESS + (p * 4) */
785 (tile
->p
* 4), 0, 0);
787 OUT_PKT0(ring
, REG_A4XX_PC_VSTREAM_CONTROL
, 1);
788 OUT_RING(ring
, 0x00000000);
791 OUT_PKT3(ring
, CP_SET_BIN
, 3);
792 OUT_RING(ring
, 0x00000000);
793 OUT_RING(ring
, CP_SET_BIN_1_X1(x1
) | CP_SET_BIN_1_Y1(y1
));
794 OUT_RING(ring
, CP_SET_BIN_2_X2(x2
) | CP_SET_BIN_2_Y2(y2
));
796 emit_mrt(ring
, pfb
->nr_cbufs
, pfb
->cbufs
, gmem
->cbuf_base
, gmem
->bin_w
, true);
798 /* setup scissor/offset for current tile: */
799 OUT_PKT0(ring
, REG_A4XX_RB_BIN_OFFSET
, 1);
800 OUT_RING(ring
, A4XX_RB_BIN_OFFSET_X(tile
->xoff
) |
801 A4XX_RB_BIN_OFFSET_Y(tile
->yoff
));
803 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
, 2);
804 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1
) |
805 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1
));
806 OUT_RING(ring
, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2
) |
807 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2
));
809 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
814 fd4_gmem_init(struct pipe_context
*pctx
)
816 struct fd_context
*ctx
= fd_context(pctx
);
818 ctx
->emit_sysmem_prep
= fd4_emit_sysmem_prep
;
819 ctx
->emit_tile_init
= fd4_emit_tile_init
;
820 ctx
->emit_tile_prep
= fd4_emit_tile_prep
;
821 ctx
->emit_tile_mem2gmem
= fd4_emit_tile_mem2gmem
;
822 ctx
->emit_tile_renderprep
= fd4_emit_tile_renderprep
;
823 ctx
->emit_tile_gmem2mem
= fd4_emit_tile_gmem2mem
;