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[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_program.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd4_program.h"
38 #include "fd4_emit.h"
39 #include "fd4_texture.h"
40 #include "fd4_format.h"
41
42 static struct ir3_shader *
43 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
44 enum shader_t type)
45 {
46 struct fd_context *ctx = fd_context(pctx);
47 struct ir3_compiler *compiler = ctx->screen->compiler;
48 return ir3_shader_create(compiler, cso, type, &ctx->debug);
49 }
50
51 static void *
52 fd4_fp_state_create(struct pipe_context *pctx,
53 const struct pipe_shader_state *cso)
54 {
55 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
56 }
57
58 static void
59 fd4_fp_state_delete(struct pipe_context *pctx, void *hwcso)
60 {
61 struct ir3_shader *so = hwcso;
62 ir3_shader_destroy(so);
63 }
64
65 static void *
66 fd4_vp_state_create(struct pipe_context *pctx,
67 const struct pipe_shader_state *cso)
68 {
69 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
70 }
71
72 static void
73 fd4_vp_state_delete(struct pipe_context *pctx, void *hwcso)
74 {
75 struct ir3_shader *so = hwcso;
76 ir3_shader_destroy(so);
77 }
78
79 static void
80 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
81 {
82 const struct ir3_info *si = &so->info;
83 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
84 enum adreno_state_src src;
85 uint32_t i, sz, *bin;
86
87 if (fd_mesa_debug & FD_DBG_DIRECT) {
88 sz = si->sizedwords;
89 src = SS4_DIRECT;
90 bin = fd_bo_map(so->bo);
91 } else {
92 sz = 0;
93 src = SS4_INDIRECT;
94 bin = NULL;
95 }
96
97 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
98 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
99 CP_LOAD_STATE4_0_STATE_SRC(src) |
100 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
101 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
102 if (bin) {
103 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
104 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
105 } else {
106 OUT_RELOC(ring, so->bo, 0,
107 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
108 }
109
110 /* for how clever coverity is, it is sometimes rather dull, and
111 * doesn't realize that the only case where bin==NULL, sz==0:
112 */
113 assume(bin || (sz == 0));
114
115 for (i = 0; i < sz; i++) {
116 OUT_RING(ring, bin[i]);
117 }
118 }
119
120 struct stage {
121 const struct ir3_shader_variant *v;
122 const struct ir3_info *i;
123 /* const sizes are in units of 4 * vec4 */
124 uint8_t constoff;
125 uint8_t constlen;
126 /* instr sizes are in units of 16 instructions */
127 uint8_t instroff;
128 uint8_t instrlen;
129 };
130
131 enum {
132 VS = 0,
133 FS = 1,
134 HS = 2,
135 DS = 3,
136 GS = 4,
137 MAX_STAGES
138 };
139
140 static void
141 setup_stages(struct fd4_emit *emit, struct stage *s)
142 {
143 unsigned i;
144
145 s[VS].v = fd4_emit_get_vp(emit);
146 s[FS].v = fd4_emit_get_fp(emit);
147
148 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
149
150 for (i = 0; i < MAX_STAGES; i++) {
151 if (s[i].v) {
152 s[i].i = &s[i].v->info;
153 /* constlen is in units of 4 * vec4: */
154 s[i].constlen = align(s[i].v->constlen, 4) / 4;
155 /* instrlen is already in units of 16 instr.. although
156 * probably we should ditch that and not make the compiler
157 * care about instruction group size of a3xx vs a4xx
158 */
159 s[i].instrlen = s[i].v->instrlen;
160 } else {
161 s[i].i = NULL;
162 s[i].constlen = 0;
163 s[i].instrlen = 0;
164 }
165 }
166
167 /* NOTE: at least for gles2, blob partitions VS at bottom of const
168 * space and FS taking entire remaining space. We probably don't
169 * need to do that the same way, but for now mimic what the blob
170 * does to make it easier to diff against register values from blob
171 *
172 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
173 * is run from external memory.
174 */
175 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
176 /* prioritize FS for internal memory: */
177 if (s[FS].instrlen < 64) {
178 /* if FS can fit, kick VS out to external memory: */
179 s[VS].instrlen = 0;
180 } else if (s[VS].instrlen < 64) {
181 /* otherwise if VS can fit, kick out FS: */
182 s[FS].instrlen = 0;
183 } else {
184 /* neither can fit, run both from external memory: */
185 s[VS].instrlen = 0;
186 s[FS].instrlen = 0;
187 }
188 }
189 s[VS].constlen = 66;
190 s[FS].constlen = 128 - s[VS].constlen;
191 s[VS].instroff = 0;
192 s[VS].constoff = 0;
193 s[FS].instroff = 64 - s[FS].instrlen;
194 s[FS].constoff = s[VS].constlen;
195 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
196 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
197 }
198
199 void
200 fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
201 int nr, struct pipe_surface **bufs)
202 {
203 struct stage s[MAX_STAGES];
204 uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
205 uint32_t face_regid, coord_regid, zwcoord_regid;
206 enum a3xx_threadsize fssz;
207 int constmode;
208 int i, j;
209
210 debug_assert(nr <= ARRAY_SIZE(color_regid));
211
212 if (emit->key.binning_pass)
213 nr = 0;
214
215 setup_stages(emit, s);
216
217 fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
218
219 /* blob seems to always use constmode currently: */
220 constmode = 1;
221
222 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
223 if (pos_regid == regid(63, 0)) {
224 /* hw dislikes when there is no position output, which can
225 * happen for transform-feedback vertex shaders. Just tell
226 * the hw to use r0.x, with whatever random value is there:
227 */
228 pos_regid = regid(0, 0);
229 }
230 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
231 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
232 if (s[FS].v->color0_mrt) {
233 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
234 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
235 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
236 } else {
237 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
238 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
239 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
240 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
241 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
242 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
243 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
244 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
245 }
246
247 /* TODO get these dynamically: */
248 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
249 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
250 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
251
252 /* we could probably divide this up into things that need to be
253 * emitted if frag-prog is dirty vs if vert-prog is dirty..
254 */
255
256 OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
257 OUT_RING(ring, 0x00000003);
258
259 OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 5);
260 OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
261 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
262 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
263 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
264 * flush some caches? I think we only need to set those
265 * bits if we have updated const or shader..
266 */
267 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
268 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
269 OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
270 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
271 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid) |
272 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid));
273 OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
274 0x3f3f000 | /* XXX */
275 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
276 OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(s[FS].v->pos_regid) |
277 0xfcfcfc00);
278 OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
279
280 OUT_PKT0(ring, REG_A4XX_HLSQ_VS_CONTROL_REG, 5);
281 OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) |
282 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
283 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s[VS].instrlen) |
284 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff));
285 OUT_RING(ring, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) |
286 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
287 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s[FS].instrlen) |
288 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff));
289 OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
290 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
291 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
292 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
293 OUT_RING(ring, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
294 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
295 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
296 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
297 OUT_RING(ring, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
298 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
299 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
300 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
301
302 OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
303 OUT_RING(ring, 0x140010 | /* XXX */
304 COND(emit->key.binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
305
306 OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
307 OUT_RING(ring, 0x7f | /* XXX */
308 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
309 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
310 COND(s[VS].instrlen && s[FS].instrlen,
311 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER));
312
313 OUT_PKT0(ring, REG_A4XX_SP_VS_LENGTH_REG, 1);
314 OUT_RING(ring, s[VS].v->instrlen); /* SP_VS_LENGTH_REG */
315
316 OUT_PKT0(ring, REG_A4XX_SP_VS_CTRL_REG0, 3);
317 OUT_RING(ring, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
318 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
319 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
320 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
321 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
322 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
323 COND(s[VS].v->has_samp, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
324 OUT_RING(ring, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
325 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
326 OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
327 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
328 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(s[FS].v->varying_in));
329
330 struct ir3_shader_linkage l = {0};
331 ir3_link_shaders(&l, s[VS].v, s[FS].v);
332
333 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
334 uint32_t reg = 0;
335
336 OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
337
338 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
339 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
340 j++;
341
342 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
343 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
344 j++;
345
346 OUT_RING(ring, reg);
347 }
348
349 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
350 uint32_t reg = 0;
351
352 OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
353
354 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
355 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
356 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
357 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
358
359 OUT_RING(ring, reg);
360 }
361
362 OUT_PKT0(ring, REG_A4XX_SP_VS_OBJ_OFFSET_REG, 2);
363 OUT_RING(ring, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
364 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
365 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
366
367 if (emit->key.binning_pass) {
368 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
369 OUT_RING(ring, 0x00000000); /* SP_FS_LENGTH_REG */
370
371 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
372 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
373 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
374 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(0) |
375 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(0) |
376 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
377 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
378 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE);
379 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
380 0x80000000);
381
382 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
383 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
384 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
385 OUT_RING(ring, 0x00000000);
386 } else {
387 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
388 OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
389
390 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
391 OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
392 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
393 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
394 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
395 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
396 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
397 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
398 COND(s[FS].v->has_samp, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
399 OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
400 0x80000000 | /* XXX */
401 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
402 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
403 COND(s[FS].v->frag_coord, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
404
405 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
406 OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
407 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
408 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
409 }
410
411 OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
412 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
413 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS].instroff));
414
415 OUT_PKT0(ring, REG_A4XX_SP_DS_OBJ_OFFSET_REG, 1);
416 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
417 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff));
418
419 OUT_PKT0(ring, REG_A4XX_SP_GS_OBJ_OFFSET_REG, 1);
420 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
421 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
422
423 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
424 OUT_RING(ring, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
425 COND(s[FS].v->total_in > 0, A4XX_RB_RENDER_CONTROL2_VARYING) |
426 COND(s[FS].v->frag_face, A4XX_RB_RENDER_CONTROL2_FACENESS) |
427 COND(s[FS].v->frag_coord, A4XX_RB_RENDER_CONTROL2_XCOORD |
428 A4XX_RB_RENDER_CONTROL2_YCOORD |
429 A4XX_RB_RENDER_CONTROL2_ZCOORD |
430 A4XX_RB_RENDER_CONTROL2_WCOORD));
431
432 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
433 OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(nr) |
434 COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
435
436 OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
437 OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(nr) |
438 COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
439 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
440
441 OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
442 for (i = 0; i < 8; i++) {
443 enum a4xx_color_fmt format = 0;
444 bool srgb = false;
445 if (i < nr) {
446 format = fd4_emit_format(bufs[i]);
447 if (bufs[i] && !emit->no_decode_srgb)
448 srgb = util_format_is_srgb(bufs[i]->format);
449 }
450 OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
451 A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
452 COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
453 COND(emit->key.half_precision,
454 A4XX_SP_FS_MRT_REG_HALF_PRECISION));
455 }
456
457 if (emit->key.binning_pass) {
458 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
459 OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |
460 0x40000000 | /* XXX */
461 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
462 OUT_RING(ring, 0x00000000);
463 } else {
464 uint32_t vinterp[8], vpsrepl[8];
465
466 memset(vinterp, 0, sizeof(vinterp));
467 memset(vpsrepl, 0, sizeof(vpsrepl));
468
469 /* looks like we need to do int varyings in the frag
470 * shader on a4xx (no flatshad reg? or a420.0 bug?):
471 *
472 * (sy)(ss)nop
473 * (sy)ldlv.u32 r0.x,l[r0.x], 1
474 * ldlv.u32 r0.y,l[r0.x+1], 1
475 * (ss)bary.f (ei)r63.x, 0, r0.x
476 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
477 * (rpt5)nop
478 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
479 *
480 * Possibly on later a4xx variants we'll be able to use
481 * something like the code below instead of workaround
482 * in the shader:
483 */
484 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
485 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
486 /* NOTE: varyings are packed, so if compmask is 0xb
487 * then first, third, and fourth component occupy
488 * three consecutive varying slots:
489 */
490 unsigned compmask = s[FS].v->inputs[j].compmask;
491
492 uint32_t inloc = s[FS].v->inputs[j].inloc;
493
494 if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
495 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
496 uint32_t loc = inloc;
497
498 for (i = 0; i < 4; i++) {
499 if (compmask & (1 << i)) {
500 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
501 //flatshade[loc / 32] |= 1 << (loc % 32);
502 loc++;
503 }
504 }
505 }
506
507 gl_varying_slot slot = s[FS].v->inputs[j].slot;
508
509 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
510 if (slot >= VARYING_SLOT_VAR0) {
511 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
512 /* Replace the .xy coordinates with S/T from the point sprite. Set
513 * interpolation bits for .zw such that they become .01
514 */
515 if (emit->sprite_coord_enable & texmask) {
516 /* mask is two 2-bit fields, where:
517 * '01' -> S
518 * '10' -> T
519 * '11' -> 1 - T (flip mode)
520 */
521 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
522 uint32_t loc = inloc;
523 if (compmask & 0x1) {
524 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
525 loc++;
526 }
527 if (compmask & 0x2) {
528 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
529 loc++;
530 }
531 if (compmask & 0x4) {
532 /* .z <- 0.0f */
533 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
534 loc++;
535 }
536 if (compmask & 0x8) {
537 /* .w <- 1.0f */
538 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
539 loc++;
540 }
541 }
542 }
543 }
544
545 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
546 OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |
547 A4XX_VPC_ATTR_THRDASSIGN(1) |
548 COND(s[FS].v->total_in > 0, A4XX_VPC_ATTR_ENABLE) |
549 0x40000000 | /* XXX */
550 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
551 OUT_RING(ring, A4XX_VPC_PACK_NUMFPNONPOSVAR(s[FS].v->total_in) |
552 A4XX_VPC_PACK_NUMNONPOSVSVAR(s[FS].v->total_in));
553
554 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
555 for (i = 0; i < 8; i++)
556 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
557
558 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
559 for (i = 0; i < 8; i++)
560 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
561 }
562
563 if (s[VS].instrlen)
564 emit_shader(ring, s[VS].v);
565
566 if (!emit->key.binning_pass)
567 if (s[FS].instrlen)
568 emit_shader(ring, s[FS].v);
569 }
570
571 void
572 fd4_prog_init(struct pipe_context *pctx)
573 {
574 pctx->create_fs_state = fd4_fp_state_create;
575 pctx->delete_fs_state = fd4_fp_state_delete;
576
577 pctx->create_vs_state = fd4_vp_state_create;
578 pctx->delete_vs_state = fd4_vp_state_delete;
579
580 fd_prog_init(pctx);
581 }