2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
33 #include "freedreno_program.h"
35 #include "fd4_program.h"
37 #include "fd4_texture.h"
38 #include "fd4_format.h"
40 static struct ir3_shader
*
41 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
44 struct fd_context
*ctx
= fd_context(pctx
);
45 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
46 return ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
);
50 fd4_fp_state_create(struct pipe_context
*pctx
,
51 const struct pipe_shader_state
*cso
)
53 return create_shader_stateobj(pctx
, cso
, SHADER_FRAGMENT
);
57 fd4_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
59 struct ir3_shader
*so
= hwcso
;
60 ir3_shader_destroy(so
);
64 fd4_vp_state_create(struct pipe_context
*pctx
,
65 const struct pipe_shader_state
*cso
)
67 return create_shader_stateobj(pctx
, cso
, SHADER_VERTEX
);
71 fd4_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
73 struct ir3_shader
*so
= hwcso
;
74 ir3_shader_destroy(so
);
78 emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
80 const struct ir3_info
*si
= &so
->info
;
81 enum a4xx_state_block sb
= fd4_stage2shadersb(so
->type
);
82 enum adreno_state_src src
;
85 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
88 bin
= fd_bo_map(so
->bo
);
95 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + sz
);
96 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
97 CP_LOAD_STATE4_0_STATE_SRC(src
) |
98 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
99 CP_LOAD_STATE4_0_NUM_UNIT(so
->instrlen
));
101 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
102 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
));
104 OUT_RELOC(ring
, so
->bo
, 0,
105 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
), 0);
108 /* for how clever coverity is, it is sometimes rather dull, and
109 * doesn't realize that the only case where bin==NULL, sz==0:
111 assume(bin
|| (sz
== 0));
113 for (i
= 0; i
< sz
; i
++) {
114 OUT_RING(ring
, bin
[i
]);
119 const struct ir3_shader_variant
*v
;
120 const struct ir3_info
*i
;
121 /* const sizes are in units of 4 * vec4 */
124 /* instr sizes are in units of 16 instructions */
139 setup_stages(struct fd4_emit
*emit
, struct stage
*s
)
143 s
[VS
].v
= fd4_emit_get_vp(emit
);
144 s
[FS
].v
= fd4_emit_get_fp(emit
);
146 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
148 for (i
= 0; i
< MAX_STAGES
; i
++) {
150 s
[i
].i
= &s
[i
].v
->info
;
151 /* constlen is in units of 4 * vec4: */
152 s
[i
].constlen
= align(s
[i
].v
->constlen
, 4) / 4;
153 /* instrlen is already in units of 16 instr.. although
154 * probably we should ditch that and not make the compiler
155 * care about instruction group size of a3xx vs a4xx
157 s
[i
].instrlen
= s
[i
].v
->instrlen
;
165 /* NOTE: at least for gles2, blob partitions VS at bottom of const
166 * space and FS taking entire remaining space. We probably don't
167 * need to do that the same way, but for now mimic what the blob
168 * does to make it easier to diff against register values from blob
170 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
171 * is run from external memory.
173 if ((s
[VS
].instrlen
+ s
[FS
].instrlen
) > 64) {
174 /* prioritize FS for internal memory: */
175 if (s
[FS
].instrlen
< 64) {
176 /* if FS can fit, kick VS out to external memory: */
178 } else if (s
[VS
].instrlen
< 64) {
179 /* otherwise if VS can fit, kick out FS: */
182 /* neither can fit, run both from external memory: */
188 s
[FS
].constlen
= 128 - s
[VS
].constlen
;
191 s
[FS
].instroff
= 64 - s
[FS
].instrlen
;
192 s
[FS
].constoff
= s
[VS
].constlen
;
193 s
[HS
].instroff
= s
[DS
].instroff
= s
[GS
].instroff
= s
[FS
].instroff
;
194 s
[HS
].constoff
= s
[DS
].constoff
= s
[GS
].constoff
= s
[FS
].constoff
;
198 fd4_program_emit(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
,
199 int nr
, struct pipe_surface
**bufs
)
201 struct stage s
[MAX_STAGES
];
202 uint32_t pos_regid
, posz_regid
, psize_regid
, color_regid
[8];
203 uint32_t face_regid
, coord_regid
, zwcoord_regid
, vcoord_regid
;
204 enum a3xx_threadsize fssz
;
208 debug_assert(nr
<= ARRAY_SIZE(color_regid
));
210 if (emit
->key
.binning_pass
)
213 setup_stages(emit
, s
);
215 fssz
= (s
[FS
].i
->max_reg
>= 24) ? TWO_QUADS
: FOUR_QUADS
;
217 /* blob seems to always use constmode currently: */
220 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
221 if (pos_regid
== regid(63, 0)) {
222 /* hw dislikes when there is no position output, which can
223 * happen for transform-feedback vertex shaders. Just tell
224 * the hw to use r0.x, with whatever random value is there:
226 pos_regid
= regid(0, 0);
228 posz_regid
= ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DEPTH
);
229 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
230 if (s
[FS
].v
->color0_mrt
) {
231 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
232 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
233 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
235 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
236 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
237 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
238 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
239 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
240 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
241 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
242 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
245 face_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRONT_FACE
);
246 coord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRAG_COORD
);
247 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
248 vcoord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_VARYING_COORD
);
250 /* we could probably divide this up into things that need to be
251 * emitted if frag-prog is dirty vs if vert-prog is dirty..
254 OUT_PKT0(ring
, REG_A4XX_HLSQ_UPDATE_CONTROL
, 1);
255 OUT_RING(ring
, 0x00000003);
257 OUT_PKT0(ring
, REG_A4XX_HLSQ_CONTROL_0_REG
, 5);
258 OUT_RING(ring
, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz
) |
259 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode
) |
260 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE
|
261 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
262 * flush some caches? I think we only need to set those
263 * bits if we have updated const or shader..
265 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART
|
266 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE
);
267 OUT_RING(ring
, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS
) |
268 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE
|
269 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid
) |
270 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid
));
271 OUT_RING(ring
, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
272 0x3f3f000 | /* XXX */
273 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
));
274 OUT_RING(ring
, A4XX_HLSQ_CONTROL_3_REG_REGID(vcoord_regid
) |
276 OUT_RING(ring
, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
278 OUT_PKT0(ring
, REG_A4XX_HLSQ_VS_CONTROL_REG
, 5);
279 OUT_RING(ring
, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s
[VS
].constlen
) |
280 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
281 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s
[VS
].instrlen
) |
282 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s
[VS
].instroff
));
283 OUT_RING(ring
, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s
[FS
].constlen
) |
284 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
285 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s
[FS
].instrlen
) |
286 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
287 OUT_RING(ring
, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s
[HS
].constlen
) |
288 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
289 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s
[HS
].instrlen
) |
290 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s
[HS
].instroff
));
291 OUT_RING(ring
, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s
[DS
].constlen
) |
292 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
293 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s
[DS
].instrlen
) |
294 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s
[DS
].instroff
));
295 OUT_RING(ring
, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s
[GS
].constlen
) |
296 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
297 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s
[GS
].instrlen
) |
298 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s
[GS
].instroff
));
300 OUT_PKT0(ring
, REG_A4XX_SP_SP_CTRL_REG
, 1);
301 OUT_RING(ring
, 0x140010 | /* XXX */
302 COND(emit
->key
.binning_pass
, A4XX_SP_SP_CTRL_REG_BINNING_PASS
));
304 OUT_PKT0(ring
, REG_A4XX_SP_INSTR_CACHE_CTRL
, 1);
305 OUT_RING(ring
, 0x7f | /* XXX */
306 COND(s
[VS
].instrlen
, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER
) |
307 COND(s
[FS
].instrlen
, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER
) |
308 COND(s
[VS
].instrlen
&& s
[FS
].instrlen
,
309 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER
));
311 OUT_PKT0(ring
, REG_A4XX_SP_VS_LENGTH_REG
, 1);
312 OUT_RING(ring
, s
[VS
].v
->instrlen
); /* SP_VS_LENGTH_REG */
314 OUT_PKT0(ring
, REG_A4XX_SP_VS_CTRL_REG0
, 3);
315 OUT_RING(ring
, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI
) |
316 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s
[VS
].i
->max_half_reg
+ 1) |
317 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
318 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
319 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
320 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE
|
321 COND(s
[VS
].v
->has_samp
, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
322 OUT_RING(ring
, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s
[VS
].constlen
) |
323 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s
[VS
].v
->total_in
));
324 OUT_RING(ring
, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid
) |
325 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid
) |
326 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(s
[FS
].v
->varying_in
));
328 struct ir3_shader_linkage l
= {0};
329 ir3_link_shaders(&l
, s
[VS
].v
, s
[FS
].v
);
331 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
334 OUT_PKT0(ring
, REG_A4XX_SP_VS_OUT_REG(i
), 1);
336 reg
|= A4XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
337 reg
|= A4XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
340 reg
|= A4XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
341 reg
|= A4XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
347 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
350 OUT_PKT0(ring
, REG_A4XX_SP_VS_VPC_DST_REG(i
), 1);
352 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
+ 8);
353 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
+ 8);
354 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
+ 8);
355 reg
|= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
+ 8);
360 OUT_PKT0(ring
, REG_A4XX_SP_VS_OBJ_OFFSET_REG
, 2);
361 OUT_RING(ring
, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
362 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[VS
].instroff
));
363 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_REG */
365 if (emit
->key
.binning_pass
) {
366 OUT_PKT0(ring
, REG_A4XX_SP_FS_LENGTH_REG
, 1);
367 OUT_RING(ring
, 0x00000000); /* SP_FS_LENGTH_REG */
369 OUT_PKT0(ring
, REG_A4XX_SP_FS_CTRL_REG0
, 2);
370 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
371 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG0_VARYING
) |
372 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(0) |
373 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(0) |
374 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
375 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
376 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
);
377 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s
[FS
].constlen
) |
380 OUT_PKT0(ring
, REG_A4XX_SP_FS_OBJ_OFFSET_REG
, 2);
381 OUT_RING(ring
, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
382 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
383 OUT_RING(ring
, 0x00000000);
385 OUT_PKT0(ring
, REG_A4XX_SP_FS_LENGTH_REG
, 1);
386 OUT_RING(ring
, s
[FS
].v
->instrlen
); /* SP_FS_LENGTH_REG */
388 OUT_PKT0(ring
, REG_A4XX_SP_FS_CTRL_REG0
, 2);
389 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI
) |
390 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG0_VARYING
) |
391 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s
[FS
].i
->max_half_reg
+ 1) |
392 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
393 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
394 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
395 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE
|
396 COND(s
[FS
].v
->has_samp
, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
397 OUT_RING(ring
, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s
[FS
].constlen
) |
398 0x80000000 | /* XXX */
399 COND(s
[FS
].v
->frag_face
, A4XX_SP_FS_CTRL_REG1_FACENESS
) |
400 COND(s
[FS
].v
->total_in
> 0, A4XX_SP_FS_CTRL_REG1_VARYING
) |
401 COND(s
[FS
].v
->frag_coord
, A4XX_SP_FS_CTRL_REG1_FRAGCOORD
));
403 OUT_PKT0(ring
, REG_A4XX_SP_FS_OBJ_OFFSET_REG
, 2);
404 OUT_RING(ring
, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
405 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[FS
].instroff
));
406 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_REG */
409 OUT_PKT0(ring
, REG_A4XX_SP_HS_OBJ_OFFSET_REG
, 1);
410 OUT_RING(ring
, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
411 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[HS
].instroff
));
413 OUT_PKT0(ring
, REG_A4XX_SP_DS_OBJ_OFFSET_REG
, 1);
414 OUT_RING(ring
, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
415 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[DS
].instroff
));
417 OUT_PKT0(ring
, REG_A4XX_SP_GS_OBJ_OFFSET_REG
, 1);
418 OUT_RING(ring
, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
419 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s
[GS
].instroff
));
421 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL2
, 1);
422 OUT_RING(ring
, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
423 COND(s
[FS
].v
->total_in
> 0, A4XX_RB_RENDER_CONTROL2_VARYING
) |
424 COND(s
[FS
].v
->frag_face
, A4XX_RB_RENDER_CONTROL2_FACENESS
) |
425 COND(s
[FS
].v
->frag_coord
, A4XX_RB_RENDER_CONTROL2_XCOORD
|
426 A4XX_RB_RENDER_CONTROL2_YCOORD
|
427 A4XX_RB_RENDER_CONTROL2_ZCOORD
|
428 A4XX_RB_RENDER_CONTROL2_WCOORD
));
430 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT_REG
, 1);
431 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_REG_MRT(nr
) |
432 COND(s
[FS
].v
->writes_pos
, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z
));
434 OUT_PKT0(ring
, REG_A4XX_SP_FS_OUTPUT_REG
, 1);
435 OUT_RING(ring
, A4XX_SP_FS_OUTPUT_REG_MRT(nr
) |
436 COND(s
[FS
].v
->writes_pos
, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE
) |
437 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid
));
439 OUT_PKT0(ring
, REG_A4XX_SP_FS_MRT_REG(0), 8);
440 for (i
= 0; i
< 8; i
++) {
441 enum a4xx_color_fmt format
= 0;
444 format
= fd4_emit_format(bufs
[i
]);
445 if (bufs
[i
] && !emit
->no_decode_srgb
)
446 srgb
= util_format_is_srgb(bufs
[i
]->format
);
448 OUT_RING(ring
, A4XX_SP_FS_MRT_REG_REGID(color_regid
[i
]) |
449 A4XX_SP_FS_MRT_REG_MRTFORMAT(format
) |
450 COND(srgb
, A4XX_SP_FS_MRT_REG_COLOR_SRGB
) |
451 COND(emit
->key
.half_precision
,
452 A4XX_SP_FS_MRT_REG_HALF_PRECISION
));
455 if (emit
->key
.binning_pass
) {
456 OUT_PKT0(ring
, REG_A4XX_VPC_ATTR
, 2);
457 OUT_RING(ring
, A4XX_VPC_ATTR_THRDASSIGN(1) |
458 0x40000000 | /* XXX */
459 COND(s
[VS
].v
->writes_psize
, A4XX_VPC_ATTR_PSIZE
));
460 OUT_RING(ring
, 0x00000000);
462 uint32_t vinterp
[8], vpsrepl
[8];
464 memset(vinterp
, 0, sizeof(vinterp
));
465 memset(vpsrepl
, 0, sizeof(vpsrepl
));
467 /* looks like we need to do int varyings in the frag
468 * shader on a4xx (no flatshad reg? or a420.0 bug?):
471 * (sy)ldlv.u32 r0.x,l[r0.x], 1
472 * ldlv.u32 r0.y,l[r0.x+1], 1
473 * (ss)bary.f (ei)r63.x, 0, r0.x
474 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
476 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
478 * Possibly on later a4xx variants we'll be able to use
479 * something like the code below instead of workaround
482 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
483 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
484 /* NOTE: varyings are packed, so if compmask is 0xb
485 * then first, third, and fourth component occupy
486 * three consecutive varying slots:
488 unsigned compmask
= s
[FS
].v
->inputs
[j
].compmask
;
490 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
;
492 if ((s
[FS
].v
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
493 (s
[FS
].v
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
494 uint32_t loc
= inloc
;
496 for (i
= 0; i
< 4; i
++) {
497 if (compmask
& (1 << i
)) {
498 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
499 //flatshade[loc / 32] |= 1 << (loc % 32);
505 gl_varying_slot slot
= s
[FS
].v
->inputs
[j
].slot
;
507 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
508 if (slot
>= VARYING_SLOT_VAR0
) {
509 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
510 /* Replace the .xy coordinates with S/T from the point sprite. Set
511 * interpolation bits for .zw such that they become .01
513 if (emit
->sprite_coord_enable
& texmask
) {
514 /* mask is two 2-bit fields, where:
517 * '11' -> 1 - T (flip mode)
519 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
520 uint32_t loc
= inloc
;
521 if (compmask
& 0x1) {
522 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
525 if (compmask
& 0x2) {
526 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
529 if (compmask
& 0x4) {
531 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
534 if (compmask
& 0x8) {
536 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
543 OUT_PKT0(ring
, REG_A4XX_VPC_ATTR
, 2);
544 OUT_RING(ring
, A4XX_VPC_ATTR_TOTALATTR(s
[FS
].v
->total_in
) |
545 A4XX_VPC_ATTR_THRDASSIGN(1) |
546 COND(s
[FS
].v
->total_in
> 0, A4XX_VPC_ATTR_ENABLE
) |
547 0x40000000 | /* XXX */
548 COND(s
[VS
].v
->writes_psize
, A4XX_VPC_ATTR_PSIZE
));
549 OUT_RING(ring
, A4XX_VPC_PACK_NUMFPNONPOSVAR(s
[FS
].v
->total_in
) |
550 A4XX_VPC_PACK_NUMNONPOSVSVAR(s
[FS
].v
->total_in
));
552 OUT_PKT0(ring
, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
553 for (i
= 0; i
< 8; i
++)
554 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
556 OUT_PKT0(ring
, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
557 for (i
= 0; i
< 8; i
++)
558 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
562 emit_shader(ring
, s
[VS
].v
);
564 if (!emit
->key
.binning_pass
)
566 emit_shader(ring
, s
[FS
].v
);
570 fd4_prog_init(struct pipe_context
*pctx
)
572 pctx
->create_fs_state
= fd4_fp_state_create
;
573 pctx
->delete_fs_state
= fd4_fp_state_delete
;
575 pctx
->create_vs_state
= fd4_vp_state_create
;
576 pctx
->delete_vs_state
= fd4_vp_state_delete
;