freedreno/layout: layout simplifications and pitch from level 0 pitch
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_zsa.c
1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31
32 #include "fd4_zsa.h"
33 #include "fd4_context.h"
34 #include "fd4_format.h"
35
36 void *
37 fd4_zsa_state_create(struct pipe_context *pctx,
38 const struct pipe_depth_stencil_alpha_state *cso)
39 {
40 struct fd4_zsa_stateobj *so;
41
42 so = CALLOC_STRUCT(fd4_zsa_stateobj);
43 if (!so)
44 return NULL;
45
46 so->base = *cso;
47
48 so->rb_depth_control |=
49 A4XX_RB_DEPTH_CONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
50
51 if (cso->depth.enabled)
52 so->rb_depth_control |=
53 A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
54 A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE;
55
56 if (cso->depth.writemask)
57 so->rb_depth_control |= A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE;
58
59 if (cso->stencil[0].enabled) {
60 const struct pipe_stencil_state *s = &cso->stencil[0];
61
62 so->rb_stencil_control |=
63 A4XX_RB_STENCIL_CONTROL_STENCIL_READ |
64 A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
65 A4XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
66 A4XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
67 A4XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
68 A4XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
69 so->rb_stencil_control2 |=
70 A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER;
71 so->rb_stencilrefmask |=
72 0xff000000 | /* ??? */
73 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(s->writemask) |
74 A4XX_RB_STENCILREFMASK_STENCILMASK(s->valuemask);
75
76 if (cso->stencil[1].enabled) {
77 const struct pipe_stencil_state *bs = &cso->stencil[1];
78
79 so->rb_stencil_control |=
80 A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
81 A4XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
82 A4XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
83 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
84 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
85 so->rb_stencilrefmask_bf |=
86 0xff000000 | /* ??? */
87 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(bs->writemask) |
88 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(bs->valuemask);
89 }
90 }
91
92 if (cso->alpha.enabled) {
93 uint32_t ref = cso->alpha.ref_value * 255.0;
94 so->gras_alpha_control =
95 A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE;
96 so->rb_alpha_control =
97 A4XX_RB_ALPHA_CONTROL_ALPHA_TEST |
98 A4XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |
99 A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(cso->alpha.func);
100 so->rb_depth_control |=
101 A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
102 }
103
104 return so;
105 }