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a5xx: fix clip_halfz support
[mesa.git] / src / gallium / drivers / freedreno / a5xx / a5xx.xml.h
1 #ifndef A5XX_XML
2 #define A5XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/ilia/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 141292 bytes, from 2017-07-04 16:29:34)
12 - /home/ilia/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-11 01:04:14)
13 - /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-07-04 02:59:47)
14 - /home/ilia/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-07-04 02:59:47)
15
16 Copyright (C) 2013-2017 by the following authors:
17 - Rob Clark <robdclark@gmail.com> (robclark)
18 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
19
20 Permission is hereby granted, free of charge, to any person obtaining
21 a copy of this software and associated documentation files (the
22 "Software"), to deal in the Software without restriction, including
23 without limitation the rights to use, copy, modify, merge, publish,
24 distribute, sublicense, and/or sell copies of the Software, and to
25 permit persons to whom the Software is furnished to do so, subject to
26 the following conditions:
27
28 The above copyright notice and this permission notice (including the
29 next paragraph) shall be included in all copies or substantial
30 portions of the Software.
31
32 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
34 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
35 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
36 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
37 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
38 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41
42 enum a5xx_color_fmt {
43 RB5_A8_UNORM = 2,
44 RB5_R8_UNORM = 3,
45 RB5_R8_SNORM = 4,
46 RB5_R8_UINT = 5,
47 RB5_R8_SINT = 6,
48 RB5_R4G4B4A4_UNORM = 8,
49 RB5_R5G5B5A1_UNORM = 10,
50 RB5_R5G6B5_UNORM = 14,
51 RB5_R8G8_UNORM = 15,
52 RB5_R8G8_SNORM = 16,
53 RB5_R8G8_UINT = 17,
54 RB5_R8G8_SINT = 18,
55 RB5_R16_UNORM = 21,
56 RB5_R16_SNORM = 22,
57 RB5_R16_FLOAT = 23,
58 RB5_R16_UINT = 24,
59 RB5_R16_SINT = 25,
60 RB5_R8G8B8A8_UNORM = 48,
61 RB5_R8G8B8_UNORM = 49,
62 RB5_R8G8B8A8_SNORM = 50,
63 RB5_R8G8B8A8_UINT = 51,
64 RB5_R8G8B8A8_SINT = 52,
65 RB5_R10G10B10A2_UNORM = 55,
66 RB5_R10G10B10A2_UINT = 58,
67 RB5_R11G11B10_FLOAT = 66,
68 RB5_R16G16_UNORM = 67,
69 RB5_R16G16_SNORM = 68,
70 RB5_R16G16_FLOAT = 69,
71 RB5_R16G16_UINT = 70,
72 RB5_R16G16_SINT = 71,
73 RB5_R32_FLOAT = 74,
74 RB5_R32_UINT = 75,
75 RB5_R32_SINT = 76,
76 RB5_R16G16B16A16_UNORM = 96,
77 RB5_R16G16B16A16_SNORM = 97,
78 RB5_R16G16B16A16_FLOAT = 98,
79 RB5_R16G16B16A16_UINT = 99,
80 RB5_R16G16B16A16_SINT = 100,
81 RB5_R32G32_FLOAT = 103,
82 RB5_R32G32_UINT = 104,
83 RB5_R32G32_SINT = 105,
84 RB5_R32G32B32A32_FLOAT = 130,
85 RB5_R32G32B32A32_UINT = 131,
86 RB5_R32G32B32A32_SINT = 132,
87 };
88
89 enum a5xx_tile_mode {
90 TILE5_LINEAR = 0,
91 TILE5_2 = 2,
92 TILE5_3 = 3,
93 };
94
95 enum a5xx_vtx_fmt {
96 VFMT5_8_UNORM = 3,
97 VFMT5_8_SNORM = 4,
98 VFMT5_8_UINT = 5,
99 VFMT5_8_SINT = 6,
100 VFMT5_8_8_UNORM = 15,
101 VFMT5_8_8_SNORM = 16,
102 VFMT5_8_8_UINT = 17,
103 VFMT5_8_8_SINT = 18,
104 VFMT5_16_UNORM = 21,
105 VFMT5_16_SNORM = 22,
106 VFMT5_16_FLOAT = 23,
107 VFMT5_16_UINT = 24,
108 VFMT5_16_SINT = 25,
109 VFMT5_8_8_8_UNORM = 33,
110 VFMT5_8_8_8_SNORM = 34,
111 VFMT5_8_8_8_UINT = 35,
112 VFMT5_8_8_8_SINT = 36,
113 VFMT5_8_8_8_8_UNORM = 48,
114 VFMT5_8_8_8_8_SNORM = 50,
115 VFMT5_8_8_8_8_UINT = 51,
116 VFMT5_8_8_8_8_SINT = 52,
117 VFMT5_10_10_10_2_UNORM = 54,
118 VFMT5_10_10_10_2_SNORM = 57,
119 VFMT5_10_10_10_2_UINT = 58,
120 VFMT5_10_10_10_2_SINT = 59,
121 VFMT5_11_11_10_FLOAT = 66,
122 VFMT5_16_16_UNORM = 67,
123 VFMT5_16_16_SNORM = 68,
124 VFMT5_16_16_FLOAT = 69,
125 VFMT5_16_16_UINT = 70,
126 VFMT5_16_16_SINT = 71,
127 VFMT5_32_UNORM = 72,
128 VFMT5_32_SNORM = 73,
129 VFMT5_32_FLOAT = 74,
130 VFMT5_32_UINT = 75,
131 VFMT5_32_SINT = 76,
132 VFMT5_32_FIXED = 77,
133 VFMT5_16_16_16_UNORM = 88,
134 VFMT5_16_16_16_SNORM = 89,
135 VFMT5_16_16_16_FLOAT = 90,
136 VFMT5_16_16_16_UINT = 91,
137 VFMT5_16_16_16_SINT = 92,
138 VFMT5_16_16_16_16_UNORM = 96,
139 VFMT5_16_16_16_16_SNORM = 97,
140 VFMT5_16_16_16_16_FLOAT = 98,
141 VFMT5_16_16_16_16_UINT = 99,
142 VFMT5_16_16_16_16_SINT = 100,
143 VFMT5_32_32_UNORM = 101,
144 VFMT5_32_32_SNORM = 102,
145 VFMT5_32_32_FLOAT = 103,
146 VFMT5_32_32_UINT = 104,
147 VFMT5_32_32_SINT = 105,
148 VFMT5_32_32_FIXED = 106,
149 VFMT5_32_32_32_UNORM = 112,
150 VFMT5_32_32_32_SNORM = 113,
151 VFMT5_32_32_32_UINT = 114,
152 VFMT5_32_32_32_SINT = 115,
153 VFMT5_32_32_32_FLOAT = 116,
154 VFMT5_32_32_32_FIXED = 117,
155 VFMT5_32_32_32_32_UNORM = 128,
156 VFMT5_32_32_32_32_SNORM = 129,
157 VFMT5_32_32_32_32_FLOAT = 130,
158 VFMT5_32_32_32_32_UINT = 131,
159 VFMT5_32_32_32_32_SINT = 132,
160 VFMT5_32_32_32_32_FIXED = 133,
161 };
162
163 enum a5xx_tex_fmt {
164 TFMT5_A8_UNORM = 2,
165 TFMT5_8_UNORM = 3,
166 TFMT5_8_SNORM = 4,
167 TFMT5_8_UINT = 5,
168 TFMT5_8_SINT = 6,
169 TFMT5_4_4_4_4_UNORM = 8,
170 TFMT5_5_5_5_1_UNORM = 10,
171 TFMT5_5_6_5_UNORM = 14,
172 TFMT5_8_8_UNORM = 15,
173 TFMT5_8_8_SNORM = 16,
174 TFMT5_8_8_UINT = 17,
175 TFMT5_8_8_SINT = 18,
176 TFMT5_L8_A8_UNORM = 19,
177 TFMT5_16_UNORM = 21,
178 TFMT5_16_SNORM = 22,
179 TFMT5_16_FLOAT = 23,
180 TFMT5_16_UINT = 24,
181 TFMT5_16_SINT = 25,
182 TFMT5_8_8_8_8_UNORM = 48,
183 TFMT5_8_8_8_UNORM = 49,
184 TFMT5_8_8_8_8_SNORM = 50,
185 TFMT5_8_8_8_8_UINT = 51,
186 TFMT5_8_8_8_8_SINT = 52,
187 TFMT5_9_9_9_E5_FLOAT = 53,
188 TFMT5_10_10_10_2_UNORM = 54,
189 TFMT5_10_10_10_2_UINT = 58,
190 TFMT5_11_11_10_FLOAT = 66,
191 TFMT5_16_16_UNORM = 67,
192 TFMT5_16_16_SNORM = 68,
193 TFMT5_16_16_FLOAT = 69,
194 TFMT5_16_16_UINT = 70,
195 TFMT5_16_16_SINT = 71,
196 TFMT5_32_FLOAT = 74,
197 TFMT5_32_UINT = 75,
198 TFMT5_32_SINT = 76,
199 TFMT5_16_16_16_16_UNORM = 96,
200 TFMT5_16_16_16_16_SNORM = 97,
201 TFMT5_16_16_16_16_FLOAT = 98,
202 TFMT5_16_16_16_16_UINT = 99,
203 TFMT5_16_16_16_16_SINT = 100,
204 TFMT5_32_32_FLOAT = 103,
205 TFMT5_32_32_UINT = 104,
206 TFMT5_32_32_SINT = 105,
207 TFMT5_32_32_32_UINT = 114,
208 TFMT5_32_32_32_SINT = 115,
209 TFMT5_32_32_32_FLOAT = 116,
210 TFMT5_32_32_32_32_FLOAT = 130,
211 TFMT5_32_32_32_32_UINT = 131,
212 TFMT5_32_32_32_32_SINT = 132,
213 TFMT5_X8Z24_UNORM = 160,
214 TFMT5_ETC2_RG11_UNORM = 171,
215 TFMT5_ETC2_RG11_SNORM = 172,
216 TFMT5_ETC2_R11_UNORM = 173,
217 TFMT5_ETC2_R11_SNORM = 174,
218 TFMT5_ETC1 = 175,
219 TFMT5_ETC2_RGB8 = 176,
220 TFMT5_ETC2_RGBA8 = 177,
221 TFMT5_ETC2_RGB8A1 = 178,
222 TFMT5_DXT1 = 179,
223 TFMT5_DXT3 = 180,
224 TFMT5_DXT5 = 181,
225 TFMT5_RGTC1_UNORM = 183,
226 TFMT5_RGTC1_SNORM = 184,
227 TFMT5_RGTC2_UNORM = 187,
228 TFMT5_RGTC2_SNORM = 188,
229 TFMT5_BPTC_UFLOAT = 190,
230 TFMT5_BPTC_FLOAT = 191,
231 TFMT5_BPTC = 192,
232 TFMT5_ASTC_4x4 = 193,
233 TFMT5_ASTC_5x4 = 194,
234 TFMT5_ASTC_5x5 = 195,
235 TFMT5_ASTC_6x5 = 196,
236 TFMT5_ASTC_6x6 = 197,
237 TFMT5_ASTC_8x5 = 198,
238 TFMT5_ASTC_8x6 = 199,
239 TFMT5_ASTC_8x8 = 200,
240 TFMT5_ASTC_10x5 = 201,
241 TFMT5_ASTC_10x6 = 202,
242 TFMT5_ASTC_10x8 = 203,
243 TFMT5_ASTC_10x10 = 204,
244 TFMT5_ASTC_12x10 = 205,
245 TFMT5_ASTC_12x12 = 206,
246 };
247
248 enum a5xx_tex_fetchsize {
249 TFETCH5_1_BYTE = 0,
250 TFETCH5_2_BYTE = 1,
251 TFETCH5_4_BYTE = 2,
252 TFETCH5_8_BYTE = 3,
253 TFETCH5_16_BYTE = 4,
254 };
255
256 enum a5xx_depth_format {
257 DEPTH5_NONE = 0,
258 DEPTH5_16 = 1,
259 DEPTH5_24_8 = 2,
260 DEPTH5_32 = 4,
261 };
262
263 enum a5xx_blit_buf {
264 BLIT_MRT0 = 0,
265 BLIT_MRT1 = 1,
266 BLIT_MRT2 = 2,
267 BLIT_MRT3 = 3,
268 BLIT_MRT4 = 4,
269 BLIT_MRT5 = 5,
270 BLIT_MRT6 = 6,
271 BLIT_MRT7 = 7,
272 BLIT_ZS = 8,
273 BLIT_Z32 = 9,
274 };
275
276 enum a5xx_cp_perfcounter_select {
277 PERF_CP_ALWAYS_COUNT = 0,
278 PERF_CP_BUSY_GFX_CORE_IDLE = 1,
279 PERF_CP_BUSY_CYCLES = 2,
280 PERF_CP_PFP_IDLE = 3,
281 PERF_CP_PFP_BUSY_WORKING = 4,
282 PERF_CP_PFP_STALL_CYCLES_ANY = 5,
283 PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
284 PERF_CP_PFP_ICACHE_MISS = 7,
285 PERF_CP_PFP_ICACHE_HIT = 8,
286 PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
287 PERF_CP_ME_BUSY_WORKING = 10,
288 PERF_CP_ME_IDLE = 11,
289 PERF_CP_ME_STARVE_CYCLES_ANY = 12,
290 PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
291 PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
292 PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
293 PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
294 PERF_CP_ME_STALL_CYCLES_ANY = 17,
295 PERF_CP_ME_ICACHE_MISS = 18,
296 PERF_CP_ME_ICACHE_HIT = 19,
297 PERF_CP_NUM_PREEMPTIONS = 20,
298 PERF_CP_PREEMPTION_REACTION_DELAY = 21,
299 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
300 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
301 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
302 PERF_CP_PREDICATED_DRAWS_KILLED = 25,
303 PERF_CP_MODE_SWITCH = 26,
304 PERF_CP_ZPASS_DONE = 27,
305 PERF_CP_CONTEXT_DONE = 28,
306 PERF_CP_CACHE_FLUSH = 29,
307 PERF_CP_LONG_PREEMPTIONS = 30,
308 };
309
310 enum a5xx_rbbm_perfcounter_select {
311 PERF_RBBM_ALWAYS_COUNT = 0,
312 PERF_RBBM_ALWAYS_ON = 1,
313 PERF_RBBM_TSE_BUSY = 2,
314 PERF_RBBM_RAS_BUSY = 3,
315 PERF_RBBM_PC_DCALL_BUSY = 4,
316 PERF_RBBM_PC_VSD_BUSY = 5,
317 PERF_RBBM_STATUS_MASKED = 6,
318 PERF_RBBM_COM_BUSY = 7,
319 PERF_RBBM_DCOM_BUSY = 8,
320 PERF_RBBM_VBIF_BUSY = 9,
321 PERF_RBBM_VSC_BUSY = 10,
322 PERF_RBBM_TESS_BUSY = 11,
323 PERF_RBBM_UCHE_BUSY = 12,
324 PERF_RBBM_HLSQ_BUSY = 13,
325 };
326
327 enum a5xx_pc_perfcounter_select {
328 PERF_PC_BUSY_CYCLES = 0,
329 PERF_PC_WORKING_CYCLES = 1,
330 PERF_PC_STALL_CYCLES_VFD = 2,
331 PERF_PC_STALL_CYCLES_TSE = 3,
332 PERF_PC_STALL_CYCLES_VPC = 4,
333 PERF_PC_STALL_CYCLES_UCHE = 5,
334 PERF_PC_STALL_CYCLES_TESS = 6,
335 PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
336 PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
337 PERF_PC_PASS1_TF_STALL_CYCLES = 9,
338 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
339 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
340 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
341 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
342 PERF_PC_STARVE_CYCLES_DI = 14,
343 PERF_PC_VIS_STREAMS_LOADED = 15,
344 PERF_PC_INSTANCES = 16,
345 PERF_PC_VPC_PRIMITIVES = 17,
346 PERF_PC_DEAD_PRIM = 18,
347 PERF_PC_LIVE_PRIM = 19,
348 PERF_PC_VERTEX_HITS = 20,
349 PERF_PC_IA_VERTICES = 21,
350 PERF_PC_IA_PRIMITIVES = 22,
351 PERF_PC_GS_PRIMITIVES = 23,
352 PERF_PC_HS_INVOCATIONS = 24,
353 PERF_PC_DS_INVOCATIONS = 25,
354 PERF_PC_VS_INVOCATIONS = 26,
355 PERF_PC_GS_INVOCATIONS = 27,
356 PERF_PC_DS_PRIMITIVES = 28,
357 PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
358 PERF_PC_3D_DRAWCALLS = 30,
359 PERF_PC_2D_DRAWCALLS = 31,
360 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
361 PERF_TESS_BUSY_CYCLES = 33,
362 PERF_TESS_WORKING_CYCLES = 34,
363 PERF_TESS_STALL_CYCLES_PC = 35,
364 PERF_TESS_STARVE_CYCLES_PC = 36,
365 };
366
367 enum a5xx_vfd_perfcounter_select {
368 PERF_VFD_BUSY_CYCLES = 0,
369 PERF_VFD_STALL_CYCLES_UCHE = 1,
370 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
371 PERF_VFD_STALL_CYCLES_MISS_VB = 3,
372 PERF_VFD_STALL_CYCLES_MISS_Q = 4,
373 PERF_VFD_STALL_CYCLES_SP_INFO = 5,
374 PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
375 PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
376 PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
377 PERF_VFD_DECODER_PACKER_STALL = 9,
378 PERF_VFD_STARVE_CYCLES_UCHE = 10,
379 PERF_VFD_RBUFFER_FULL = 11,
380 PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
381 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
382 PERF_VFD_NUM_ATTRIBUTES = 14,
383 PERF_VFD_INSTRUCTIONS = 15,
384 PERF_VFD_UPPER_SHADER_FIBERS = 16,
385 PERF_VFD_LOWER_SHADER_FIBERS = 17,
386 PERF_VFD_MODE_0_FIBERS = 18,
387 PERF_VFD_MODE_1_FIBERS = 19,
388 PERF_VFD_MODE_2_FIBERS = 20,
389 PERF_VFD_MODE_3_FIBERS = 21,
390 PERF_VFD_MODE_4_FIBERS = 22,
391 PERF_VFD_TOTAL_VERTICES = 23,
392 PERF_VFD_NUM_ATTR_MISS = 24,
393 PERF_VFD_1_BURST_REQ = 25,
394 PERF_VFDP_STALL_CYCLES_VFD = 26,
395 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
396 PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
397 PERF_VFDP_STARVE_CYCLES_PC = 29,
398 PERF_VFDP_VS_STAGE_32_WAVES = 30,
399 };
400
401 enum a5xx_hlsq_perfcounter_select {
402 PERF_HLSQ_BUSY_CYCLES = 0,
403 PERF_HLSQ_STALL_CYCLES_UCHE = 1,
404 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
405 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
406 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
407 PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
408 PERF_HLSQ_FS_STAGE_32_WAVES = 6,
409 PERF_HLSQ_FS_STAGE_64_WAVES = 7,
410 PERF_HLSQ_QUADS = 8,
411 PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
412 PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
413 PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
414 PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
415 PERF_HLSQ_CS_INVOCATIONS = 13,
416 PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
417 };
418
419 enum a5xx_vpc_perfcounter_select {
420 PERF_VPC_BUSY_CYCLES = 0,
421 PERF_VPC_WORKING_CYCLES = 1,
422 PERF_VPC_STALL_CYCLES_UCHE = 2,
423 PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
424 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
425 PERF_VPC_STALL_CYCLES_PC = 5,
426 PERF_VPC_STALL_CYCLES_SP_LM = 6,
427 PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
428 PERF_VPC_STARVE_CYCLES_SP = 8,
429 PERF_VPC_STARVE_CYCLES_LRZ = 9,
430 PERF_VPC_PC_PRIMITIVES = 10,
431 PERF_VPC_SP_COMPONENTS = 11,
432 PERF_VPC_SP_LM_PRIMITIVES = 12,
433 PERF_VPC_SP_LM_COMPONENTS = 13,
434 PERF_VPC_SP_LM_DWORDS = 14,
435 PERF_VPC_STREAMOUT_COMPONENTS = 15,
436 PERF_VPC_GRANT_PHASES = 16,
437 };
438
439 enum a5xx_tse_perfcounter_select {
440 PERF_TSE_BUSY_CYCLES = 0,
441 PERF_TSE_CLIPPING_CYCLES = 1,
442 PERF_TSE_STALL_CYCLES_RAS = 2,
443 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
444 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
445 PERF_TSE_STARVE_CYCLES_PC = 5,
446 PERF_TSE_INPUT_PRIM = 6,
447 PERF_TSE_INPUT_NULL_PRIM = 7,
448 PERF_TSE_TRIVAL_REJ_PRIM = 8,
449 PERF_TSE_CLIPPED_PRIM = 9,
450 PERF_TSE_ZERO_AREA_PRIM = 10,
451 PERF_TSE_FACENESS_CULLED_PRIM = 11,
452 PERF_TSE_ZERO_PIXEL_PRIM = 12,
453 PERF_TSE_OUTPUT_NULL_PRIM = 13,
454 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
455 PERF_TSE_CINVOCATION = 15,
456 PERF_TSE_CPRIMITIVES = 16,
457 PERF_TSE_2D_INPUT_PRIM = 17,
458 PERF_TSE_2D_ALIVE_CLCLES = 18,
459 };
460
461 enum a5xx_ras_perfcounter_select {
462 PERF_RAS_BUSY_CYCLES = 0,
463 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
464 PERF_RAS_STALL_CYCLES_LRZ = 2,
465 PERF_RAS_STARVE_CYCLES_TSE = 3,
466 PERF_RAS_SUPER_TILES = 4,
467 PERF_RAS_8X4_TILES = 5,
468 PERF_RAS_MASKGEN_ACTIVE = 6,
469 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
470 PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
471 PERF_RAS_PRIM_KILLED_INVISILBE = 9,
472 };
473
474 enum a5xx_lrz_perfcounter_select {
475 PERF_LRZ_BUSY_CYCLES = 0,
476 PERF_LRZ_STARVE_CYCLES_RAS = 1,
477 PERF_LRZ_STALL_CYCLES_RB = 2,
478 PERF_LRZ_STALL_CYCLES_VSC = 3,
479 PERF_LRZ_STALL_CYCLES_VPC = 4,
480 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
481 PERF_LRZ_STALL_CYCLES_UCHE = 6,
482 PERF_LRZ_LRZ_READ = 7,
483 PERF_LRZ_LRZ_WRITE = 8,
484 PERF_LRZ_READ_LATENCY = 9,
485 PERF_LRZ_MERGE_CACHE_UPDATING = 10,
486 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
487 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
488 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
489 PERF_LRZ_FULL_8X8_TILES = 14,
490 PERF_LRZ_PARTIAL_8X8_TILES = 15,
491 PERF_LRZ_TILE_KILLED = 16,
492 PERF_LRZ_TOTAL_PIXEL = 17,
493 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
494 };
495
496 enum a5xx_uche_perfcounter_select {
497 PERF_UCHE_BUSY_CYCLES = 0,
498 PERF_UCHE_STALL_CYCLES_VBIF = 1,
499 PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
500 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
501 PERF_UCHE_VBIF_READ_BEATS_TP = 4,
502 PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
503 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
504 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
505 PERF_UCHE_VBIF_READ_BEATS_SP = 8,
506 PERF_UCHE_READ_REQUESTS_TP = 9,
507 PERF_UCHE_READ_REQUESTS_VFD = 10,
508 PERF_UCHE_READ_REQUESTS_HLSQ = 11,
509 PERF_UCHE_READ_REQUESTS_LRZ = 12,
510 PERF_UCHE_READ_REQUESTS_SP = 13,
511 PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
512 PERF_UCHE_WRITE_REQUESTS_SP = 15,
513 PERF_UCHE_WRITE_REQUESTS_VPC = 16,
514 PERF_UCHE_WRITE_REQUESTS_VSC = 17,
515 PERF_UCHE_EVICTS = 18,
516 PERF_UCHE_BANK_REQ0 = 19,
517 PERF_UCHE_BANK_REQ1 = 20,
518 PERF_UCHE_BANK_REQ2 = 21,
519 PERF_UCHE_BANK_REQ3 = 22,
520 PERF_UCHE_BANK_REQ4 = 23,
521 PERF_UCHE_BANK_REQ5 = 24,
522 PERF_UCHE_BANK_REQ6 = 25,
523 PERF_UCHE_BANK_REQ7 = 26,
524 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
525 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
526 PERF_UCHE_GMEM_READ_BEATS = 29,
527 PERF_UCHE_FLAG_COUNT = 30,
528 };
529
530 enum a5xx_tp_perfcounter_select {
531 PERF_TP_BUSY_CYCLES = 0,
532 PERF_TP_STALL_CYCLES_UCHE = 1,
533 PERF_TP_LATENCY_CYCLES = 2,
534 PERF_TP_LATENCY_TRANS = 3,
535 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
536 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
537 PERF_TP_L1_CACHELINE_REQUESTS = 6,
538 PERF_TP_L1_CACHELINE_MISSES = 7,
539 PERF_TP_SP_TP_TRANS = 8,
540 PERF_TP_TP_SP_TRANS = 9,
541 PERF_TP_OUTPUT_PIXELS = 10,
542 PERF_TP_FILTER_WORKLOAD_16BIT = 11,
543 PERF_TP_FILTER_WORKLOAD_32BIT = 12,
544 PERF_TP_QUADS_RECEIVED = 13,
545 PERF_TP_QUADS_OFFSET = 14,
546 PERF_TP_QUADS_SHADOW = 15,
547 PERF_TP_QUADS_ARRAY = 16,
548 PERF_TP_QUADS_GRADIENT = 17,
549 PERF_TP_QUADS_1D = 18,
550 PERF_TP_QUADS_2D = 19,
551 PERF_TP_QUADS_BUFFER = 20,
552 PERF_TP_QUADS_3D = 21,
553 PERF_TP_QUADS_CUBE = 22,
554 PERF_TP_STATE_CACHE_REQUESTS = 23,
555 PERF_TP_STATE_CACHE_MISSES = 24,
556 PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
557 PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
558 PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
559 PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
560 PERF_TP_OUTPUT_PIXELS_POINT = 29,
561 PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
562 PERF_TP_OUTPUT_PIXELS_MIP = 31,
563 PERF_TP_OUTPUT_PIXELS_ANISO = 32,
564 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
565 PERF_TP_FLAG_CACHE_REQUESTS = 34,
566 PERF_TP_FLAG_CACHE_MISSES = 35,
567 PERF_TP_L1_5_L2_REQUESTS = 36,
568 PERF_TP_2D_OUTPUT_PIXELS = 37,
569 PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
570 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
571 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
572 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
573 };
574
575 enum a5xx_sp_perfcounter_select {
576 PERF_SP_BUSY_CYCLES = 0,
577 PERF_SP_ALU_WORKING_CYCLES = 1,
578 PERF_SP_EFU_WORKING_CYCLES = 2,
579 PERF_SP_STALL_CYCLES_VPC = 3,
580 PERF_SP_STALL_CYCLES_TP = 4,
581 PERF_SP_STALL_CYCLES_UCHE = 5,
582 PERF_SP_STALL_CYCLES_RB = 6,
583 PERF_SP_SCHEDULER_NON_WORKING = 7,
584 PERF_SP_WAVE_CONTEXTS = 8,
585 PERF_SP_WAVE_CONTEXT_CYCLES = 9,
586 PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
587 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
588 PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
589 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
590 PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
591 PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
592 PERF_SP_WAVE_CTRL_CYCLES = 16,
593 PERF_SP_WAVE_LOAD_CYCLES = 17,
594 PERF_SP_WAVE_EMIT_CYCLES = 18,
595 PERF_SP_WAVE_NOP_CYCLES = 19,
596 PERF_SP_WAVE_WAIT_CYCLES = 20,
597 PERF_SP_WAVE_FETCH_CYCLES = 21,
598 PERF_SP_WAVE_IDLE_CYCLES = 22,
599 PERF_SP_WAVE_END_CYCLES = 23,
600 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
601 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
602 PERF_SP_WAVE_JOIN_CYCLES = 26,
603 PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
604 PERF_SP_LM_STORE_INSTRUCTIONS = 28,
605 PERF_SP_LM_ATOMICS = 29,
606 PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
607 PERF_SP_GM_STORE_INSTRUCTIONS = 31,
608 PERF_SP_GM_ATOMICS = 32,
609 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
610 PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
611 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
612 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
613 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
614 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
615 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
616 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
617 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
618 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
619 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
620 PERF_SP_VS_INSTRUCTIONS = 44,
621 PERF_SP_FS_INSTRUCTIONS = 45,
622 PERF_SP_ADDR_LOCK_COUNT = 46,
623 PERF_SP_UCHE_READ_TRANS = 47,
624 PERF_SP_UCHE_WRITE_TRANS = 48,
625 PERF_SP_EXPORT_VPC_TRANS = 49,
626 PERF_SP_EXPORT_RB_TRANS = 50,
627 PERF_SP_PIXELS_KILLED = 51,
628 PERF_SP_ICL1_REQUESTS = 52,
629 PERF_SP_ICL1_MISSES = 53,
630 PERF_SP_ICL0_REQUESTS = 54,
631 PERF_SP_ICL0_MISSES = 55,
632 PERF_SP_HS_INSTRUCTIONS = 56,
633 PERF_SP_DS_INSTRUCTIONS = 57,
634 PERF_SP_GS_INSTRUCTIONS = 58,
635 PERF_SP_CS_INSTRUCTIONS = 59,
636 PERF_SP_GPR_READ = 60,
637 PERF_SP_GPR_WRITE = 61,
638 PERF_SP_LM_CH0_REQUESTS = 62,
639 PERF_SP_LM_CH1_REQUESTS = 63,
640 PERF_SP_LM_BANK_CONFLICTS = 64,
641 };
642
643 enum a5xx_rb_perfcounter_select {
644 PERF_RB_BUSY_CYCLES = 0,
645 PERF_RB_STALL_CYCLES_CCU = 1,
646 PERF_RB_STALL_CYCLES_HLSQ = 2,
647 PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
648 PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
649 PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
650 PERF_RB_STARVE_CYCLES_SP = 6,
651 PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
652 PERF_RB_STARVE_CYCLES_CCU = 8,
653 PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
654 PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
655 PERF_RB_Z_WORKLOAD = 11,
656 PERF_RB_HLSQ_ACTIVE = 12,
657 PERF_RB_Z_READ = 13,
658 PERF_RB_Z_WRITE = 14,
659 PERF_RB_C_READ = 15,
660 PERF_RB_C_WRITE = 16,
661 PERF_RB_TOTAL_PASS = 17,
662 PERF_RB_Z_PASS = 18,
663 PERF_RB_Z_FAIL = 19,
664 PERF_RB_S_FAIL = 20,
665 PERF_RB_BLENDED_FXP_COMPONENTS = 21,
666 PERF_RB_BLENDED_FP16_COMPONENTS = 22,
667 RB_RESERVED = 23,
668 PERF_RB_2D_ALIVE_CYCLES = 24,
669 PERF_RB_2D_STALL_CYCLES_A2D = 25,
670 PERF_RB_2D_STARVE_CYCLES_SRC = 26,
671 PERF_RB_2D_STARVE_CYCLES_SP = 27,
672 PERF_RB_2D_STARVE_CYCLES_DST = 28,
673 PERF_RB_2D_VALID_PIXELS = 29,
674 };
675
676 enum a5xx_rb_samples_perfcounter_select {
677 TOTAL_SAMPLES = 0,
678 ZPASS_SAMPLES = 1,
679 ZFAIL_SAMPLES = 2,
680 SFAIL_SAMPLES = 3,
681 };
682
683 enum a5xx_vsc_perfcounter_select {
684 PERF_VSC_BUSY_CYCLES = 0,
685 PERF_VSC_WORKING_CYCLES = 1,
686 PERF_VSC_STALL_CYCLES_UCHE = 2,
687 PERF_VSC_EOT_NUM = 3,
688 };
689
690 enum a5xx_ccu_perfcounter_select {
691 PERF_CCU_BUSY_CYCLES = 0,
692 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
693 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
694 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
695 PERF_CCU_DEPTH_BLOCKS = 4,
696 PERF_CCU_COLOR_BLOCKS = 5,
697 PERF_CCU_DEPTH_BLOCK_HIT = 6,
698 PERF_CCU_COLOR_BLOCK_HIT = 7,
699 PERF_CCU_PARTIAL_BLOCK_READ = 8,
700 PERF_CCU_GMEM_READ = 9,
701 PERF_CCU_GMEM_WRITE = 10,
702 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
703 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
704 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
705 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
706 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
707 PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
708 PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
709 PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
710 PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
711 PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
712 PERF_CCU_2D_BUSY_CYCLES = 21,
713 PERF_CCU_2D_RD_REQ = 22,
714 PERF_CCU_2D_WR_REQ = 23,
715 PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
716 PERF_CCU_2D_PIXELS = 25,
717 };
718
719 enum a5xx_cmp_perfcounter_select {
720 PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
721 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
722 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
723 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
724 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
725 PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
726 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
727 PERF_CMPDECMP_VBIF_READ_DATA = 7,
728 PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
729 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
730 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
731 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
732 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
733 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
734 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
735 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
736 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
737 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
738 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
739 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
740 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
741 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
742 PERF_CMPDECMP_2D_RD_DATA = 22,
743 PERF_CMPDECMP_2D_WR_DATA = 23,
744 };
745
746 enum a5xx_vbif_perfcounter_select {
747 AXI_READ_REQUESTS_ID_0 = 0,
748 AXI_READ_REQUESTS_ID_1 = 1,
749 AXI_READ_REQUESTS_ID_2 = 2,
750 AXI_READ_REQUESTS_ID_3 = 3,
751 AXI_READ_REQUESTS_ID_4 = 4,
752 AXI_READ_REQUESTS_ID_5 = 5,
753 AXI_READ_REQUESTS_ID_6 = 6,
754 AXI_READ_REQUESTS_ID_7 = 7,
755 AXI_READ_REQUESTS_ID_8 = 8,
756 AXI_READ_REQUESTS_ID_9 = 9,
757 AXI_READ_REQUESTS_ID_10 = 10,
758 AXI_READ_REQUESTS_ID_11 = 11,
759 AXI_READ_REQUESTS_ID_12 = 12,
760 AXI_READ_REQUESTS_ID_13 = 13,
761 AXI_READ_REQUESTS_ID_14 = 14,
762 AXI_READ_REQUESTS_ID_15 = 15,
763 AXI0_READ_REQUESTS_TOTAL = 16,
764 AXI1_READ_REQUESTS_TOTAL = 17,
765 AXI2_READ_REQUESTS_TOTAL = 18,
766 AXI3_READ_REQUESTS_TOTAL = 19,
767 AXI_READ_REQUESTS_TOTAL = 20,
768 AXI_WRITE_REQUESTS_ID_0 = 21,
769 AXI_WRITE_REQUESTS_ID_1 = 22,
770 AXI_WRITE_REQUESTS_ID_2 = 23,
771 AXI_WRITE_REQUESTS_ID_3 = 24,
772 AXI_WRITE_REQUESTS_ID_4 = 25,
773 AXI_WRITE_REQUESTS_ID_5 = 26,
774 AXI_WRITE_REQUESTS_ID_6 = 27,
775 AXI_WRITE_REQUESTS_ID_7 = 28,
776 AXI_WRITE_REQUESTS_ID_8 = 29,
777 AXI_WRITE_REQUESTS_ID_9 = 30,
778 AXI_WRITE_REQUESTS_ID_10 = 31,
779 AXI_WRITE_REQUESTS_ID_11 = 32,
780 AXI_WRITE_REQUESTS_ID_12 = 33,
781 AXI_WRITE_REQUESTS_ID_13 = 34,
782 AXI_WRITE_REQUESTS_ID_14 = 35,
783 AXI_WRITE_REQUESTS_ID_15 = 36,
784 AXI0_WRITE_REQUESTS_TOTAL = 37,
785 AXI1_WRITE_REQUESTS_TOTAL = 38,
786 AXI2_WRITE_REQUESTS_TOTAL = 39,
787 AXI3_WRITE_REQUESTS_TOTAL = 40,
788 AXI_WRITE_REQUESTS_TOTAL = 41,
789 AXI_TOTAL_REQUESTS = 42,
790 AXI_READ_DATA_BEATS_ID_0 = 43,
791 AXI_READ_DATA_BEATS_ID_1 = 44,
792 AXI_READ_DATA_BEATS_ID_2 = 45,
793 AXI_READ_DATA_BEATS_ID_3 = 46,
794 AXI_READ_DATA_BEATS_ID_4 = 47,
795 AXI_READ_DATA_BEATS_ID_5 = 48,
796 AXI_READ_DATA_BEATS_ID_6 = 49,
797 AXI_READ_DATA_BEATS_ID_7 = 50,
798 AXI_READ_DATA_BEATS_ID_8 = 51,
799 AXI_READ_DATA_BEATS_ID_9 = 52,
800 AXI_READ_DATA_BEATS_ID_10 = 53,
801 AXI_READ_DATA_BEATS_ID_11 = 54,
802 AXI_READ_DATA_BEATS_ID_12 = 55,
803 AXI_READ_DATA_BEATS_ID_13 = 56,
804 AXI_READ_DATA_BEATS_ID_14 = 57,
805 AXI_READ_DATA_BEATS_ID_15 = 58,
806 AXI0_READ_DATA_BEATS_TOTAL = 59,
807 AXI1_READ_DATA_BEATS_TOTAL = 60,
808 AXI2_READ_DATA_BEATS_TOTAL = 61,
809 AXI3_READ_DATA_BEATS_TOTAL = 62,
810 AXI_READ_DATA_BEATS_TOTAL = 63,
811 AXI_WRITE_DATA_BEATS_ID_0 = 64,
812 AXI_WRITE_DATA_BEATS_ID_1 = 65,
813 AXI_WRITE_DATA_BEATS_ID_2 = 66,
814 AXI_WRITE_DATA_BEATS_ID_3 = 67,
815 AXI_WRITE_DATA_BEATS_ID_4 = 68,
816 AXI_WRITE_DATA_BEATS_ID_5 = 69,
817 AXI_WRITE_DATA_BEATS_ID_6 = 70,
818 AXI_WRITE_DATA_BEATS_ID_7 = 71,
819 AXI_WRITE_DATA_BEATS_ID_8 = 72,
820 AXI_WRITE_DATA_BEATS_ID_9 = 73,
821 AXI_WRITE_DATA_BEATS_ID_10 = 74,
822 AXI_WRITE_DATA_BEATS_ID_11 = 75,
823 AXI_WRITE_DATA_BEATS_ID_12 = 76,
824 AXI_WRITE_DATA_BEATS_ID_13 = 77,
825 AXI_WRITE_DATA_BEATS_ID_14 = 78,
826 AXI_WRITE_DATA_BEATS_ID_15 = 79,
827 AXI0_WRITE_DATA_BEATS_TOTAL = 80,
828 AXI1_WRITE_DATA_BEATS_TOTAL = 81,
829 AXI2_WRITE_DATA_BEATS_TOTAL = 82,
830 AXI3_WRITE_DATA_BEATS_TOTAL = 83,
831 AXI_WRITE_DATA_BEATS_TOTAL = 84,
832 AXI_DATA_BEATS_TOTAL = 85,
833 };
834
835 enum a5xx_tex_filter {
836 A5XX_TEX_NEAREST = 0,
837 A5XX_TEX_LINEAR = 1,
838 A5XX_TEX_ANISO = 2,
839 };
840
841 enum a5xx_tex_clamp {
842 A5XX_TEX_REPEAT = 0,
843 A5XX_TEX_CLAMP_TO_EDGE = 1,
844 A5XX_TEX_MIRROR_REPEAT = 2,
845 A5XX_TEX_CLAMP_TO_BORDER = 3,
846 A5XX_TEX_MIRROR_CLAMP = 4,
847 };
848
849 enum a5xx_tex_aniso {
850 A5XX_TEX_ANISO_1 = 0,
851 A5XX_TEX_ANISO_2 = 1,
852 A5XX_TEX_ANISO_4 = 2,
853 A5XX_TEX_ANISO_8 = 3,
854 A5XX_TEX_ANISO_16 = 4,
855 };
856
857 enum a5xx_tex_swiz {
858 A5XX_TEX_X = 0,
859 A5XX_TEX_Y = 1,
860 A5XX_TEX_Z = 2,
861 A5XX_TEX_W = 3,
862 A5XX_TEX_ZERO = 4,
863 A5XX_TEX_ONE = 5,
864 };
865
866 enum a5xx_tex_type {
867 A5XX_TEX_1D = 0,
868 A5XX_TEX_2D = 1,
869 A5XX_TEX_CUBE = 2,
870 A5XX_TEX_3D = 3,
871 };
872
873 #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
874 #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
875 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
876 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
877 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
878 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
879 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
880 #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
881 #define A5XX_INT0_CP_SW 0x00000100
882 #define A5XX_INT0_CP_HW_ERROR 0x00000200
883 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
884 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
885 #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
886 #define A5XX_INT0_CP_IB2 0x00002000
887 #define A5XX_INT0_CP_IB1 0x00004000
888 #define A5XX_INT0_CP_RB 0x00008000
889 #define A5XX_INT0_CP_UNUSED_1 0x00010000
890 #define A5XX_INT0_CP_RB_DONE_TS 0x00020000
891 #define A5XX_INT0_CP_WT_DONE_TS 0x00040000
892 #define A5XX_INT0_UNKNOWN_1 0x00080000
893 #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
894 #define A5XX_INT0_UNUSED_2 0x00200000
895 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
896 #define A5XX_INT0_MISC_HANG_DETECT 0x00800000
897 #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
898 #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
899 #define A5XX_INT0_DEBBUS_INTR_0 0x04000000
900 #define A5XX_INT0_DEBBUS_INTR_1 0x08000000
901 #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
902 #define A5XX_INT0_GPMU_FIRMWARE 0x20000000
903 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
904 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
905 #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
906 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
907 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
908 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
909 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
910 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
911 #define REG_A5XX_CP_RB_BASE 0x00000800
912
913 #define REG_A5XX_CP_RB_BASE_HI 0x00000801
914
915 #define REG_A5XX_CP_RB_CNTL 0x00000802
916
917 #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
918
919 #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
920
921 #define REG_A5XX_CP_RB_RPTR 0x00000806
922
923 #define REG_A5XX_CP_RB_WPTR 0x00000807
924
925 #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
926
927 #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
928
929 #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
930
931 #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
932
933 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
934
935 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
936
937 #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
938
939 #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
940
941 #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
942
943 #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
944
945 #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
946
947 #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
948
949 #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
950
951 #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
952
953 #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
954
955 #define REG_A5XX_CP_MERCIU_SIZE 0x00000826
956
957 #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
958
959 #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
960
961 #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
962
963 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
964
965 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
966
967 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
968
969 #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
970
971 #define REG_A5XX_CP_CNTL 0x00000831
972
973 #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
974
975 #define REG_A5XX_CP_CHICKEN_DBG 0x00000833
976
977 #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
978
979 #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
980
981 #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
982
983 #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
984
985 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
986
987 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
988
989 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
990
991 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
992
993 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
994
995 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
996
997 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
998
999 #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
1000
1001 #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
1002
1003 #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
1004
1005 #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
1006
1007 #define REG_A5XX_CP_HW_FAULT 0x00000b1a
1008
1009 #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
1010
1011 #define REG_A5XX_CP_IB1_BASE 0x00000b1f
1012
1013 #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
1014
1015 #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
1016
1017 #define REG_A5XX_CP_IB2_BASE 0x00000b22
1018
1019 #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
1020
1021 #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
1022
1023 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1024
1025 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1026
1027 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1028
1029 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1030 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
1031 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
1032 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1033 {
1034 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1035 }
1036 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
1037 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
1038 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1039 {
1040 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
1041 }
1042 #define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
1043 #define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
1044
1045 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
1046
1047 #define REG_A5XX_CP_AHB_FAULT 0x00000b1b
1048
1049 #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
1050
1051 #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
1052
1053 #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
1054
1055 #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
1056
1057 #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
1058
1059 #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
1060
1061 #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
1062
1063 #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
1064
1065 #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
1066
1067 #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
1068
1069 #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
1070
1071 #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
1072
1073 #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
1074
1075 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
1076
1077 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
1078
1079 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
1080
1081 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
1082
1083 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
1084
1085 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
1086
1087 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
1088
1089 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
1090
1091 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
1092
1093 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
1094
1095 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
1096
1097 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
1098
1099 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
1100
1101 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
1102
1103 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
1104
1105 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
1106
1107 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
1108
1109 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
1110
1111 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
1112
1113 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
1114
1115 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
1116
1117 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
1118
1119 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
1120
1121 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
1122
1123 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
1124
1125 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
1126
1127 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
1128
1129 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
1130
1131 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
1132
1133 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
1134
1135 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
1136
1137 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
1138
1139 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
1140
1141 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
1142
1143 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
1144
1145 #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
1146
1147 #define REG_A5XX_RBBM_INT_0_MASK 0x00000038
1148 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
1149 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
1150 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
1151 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
1152 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
1153 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
1154 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
1155 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
1156 #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
1157 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
1158 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
1159 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
1160 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
1161 #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
1162 #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
1163 #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
1164 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
1165 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
1166 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
1167 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
1168 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
1169 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
1170 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
1171 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
1172 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
1173 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
1174 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
1175 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
1176 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
1177
1178 #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
1179
1180 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
1181
1182 #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
1183
1184 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1185
1186 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1187
1188 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
1189
1190 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
1191
1192 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
1193
1194 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
1195
1196 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
1197
1198 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
1199
1200 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
1201
1202 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
1203
1204 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
1205
1206 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
1207
1208 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
1209
1210 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
1211
1212 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
1213
1214 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
1215
1216 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
1217
1218 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
1219
1220 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
1221
1222 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
1223
1224 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
1225
1226 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
1227
1228 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
1229
1230 #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
1231
1232 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
1233
1234 #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
1235
1236 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
1237
1238 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
1239
1240 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
1241
1242 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
1243
1244 #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
1245
1246 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
1247
1248 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
1249
1250 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
1251
1252 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
1253
1254 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
1255
1256 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
1257
1258 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
1259
1260 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
1261
1262 #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
1263
1264 #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
1265
1266 #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
1267
1268 #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
1269
1270 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
1271
1272 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
1273
1274 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
1275
1276 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
1277
1278 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
1279
1280 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
1281
1282 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
1283
1284 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
1285
1286 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
1287
1288 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
1289
1290 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
1291
1292 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
1293
1294 #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
1295
1296 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
1297
1298 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
1299
1300 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
1301
1302 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
1303
1304 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
1305
1306 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
1307
1308 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
1309
1310 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
1311
1312 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
1313
1314 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
1315
1316 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
1317
1318 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
1319
1320 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
1321
1322 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
1323
1324 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
1325
1326 #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
1327
1328 #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
1329
1330 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
1331
1332 #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
1333
1334 #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
1335
1336 #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
1337
1338 #define REG_A5XX_RBBM_AHB_CMD 0x00000096
1339
1340 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
1341
1342 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
1343
1344 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
1345
1346 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
1347
1348 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
1349
1350 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
1351
1352 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
1353
1354 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
1355
1356 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
1357
1358 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
1359
1360 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
1361
1362 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
1363
1364 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
1365
1366 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
1367
1368 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
1369
1370 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
1371
1372 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
1373
1374 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
1375
1376 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
1377
1378 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
1379
1380 #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
1381
1382 #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
1383
1384 #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
1385
1386 #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
1387
1388 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
1389
1390 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
1391
1392 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
1393
1394 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
1395
1396 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
1397
1398 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
1399
1400 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
1401
1402 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
1403
1404 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
1405
1406 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
1407
1408 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
1409
1410 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
1411
1412 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
1413
1414 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
1415
1416 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
1417
1418 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
1419
1420 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
1421
1422 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
1423
1424 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
1425
1426 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
1427
1428 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
1429
1430 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
1431
1432 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
1433
1434 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
1435
1436 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
1437
1438 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
1439
1440 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
1441
1442 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
1443
1444 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
1445
1446 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
1447
1448 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
1449
1450 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
1451
1452 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
1453
1454 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
1455
1456 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
1457
1458 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
1459
1460 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
1461
1462 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
1463
1464 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
1465
1466 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
1467
1468 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
1469
1470 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
1471
1472 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
1473
1474 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
1475
1476 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
1477
1478 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
1479
1480 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
1481
1482 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
1483
1484 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
1485
1486 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
1487
1488 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
1489
1490 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
1491
1492 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
1493
1494 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
1495
1496 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
1497
1498 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
1499
1500 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
1501
1502 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
1503
1504 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
1505
1506 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
1507
1508 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
1509
1510 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
1511
1512 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
1513
1514 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
1515
1516 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
1517
1518 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
1519
1520 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
1521
1522 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
1523
1524 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
1525
1526 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
1527
1528 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
1529
1530 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
1531
1532 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
1533
1534 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
1535
1536 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
1537
1538 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
1539
1540 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
1541
1542 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
1543
1544 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
1545
1546 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
1547
1548 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
1549
1550 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
1551
1552 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
1553
1554 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
1555
1556 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
1557
1558 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
1559
1560 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
1561
1562 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
1563
1564 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
1565
1566 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
1567
1568 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
1569
1570 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
1571
1572 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
1573
1574 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
1575
1576 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
1577
1578 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
1579
1580 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
1581
1582 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
1583
1584 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
1585
1586 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
1587
1588 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
1589
1590 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
1591
1592 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
1593
1594 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
1595
1596 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
1597
1598 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
1599
1600 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
1601
1602 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
1603
1604 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
1605
1606 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
1607
1608 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
1609
1610 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
1611
1612 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
1613
1614 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
1615
1616 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
1617
1618 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
1619
1620 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
1621
1622 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
1623
1624 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
1625
1626 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
1627
1628 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
1629
1630 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
1631
1632 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
1633
1634 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
1635
1636 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
1637
1638 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
1639
1640 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
1641
1642 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
1643
1644 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
1645
1646 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
1647
1648 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
1649
1650 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
1651
1652 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
1653
1654 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
1655
1656 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
1657
1658 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
1659
1660 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
1661
1662 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
1663
1664 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
1665
1666 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
1667
1668 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
1669
1670 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
1671
1672 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
1673
1674 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
1675
1676 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
1677
1678 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
1679
1680 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
1681
1682 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
1683
1684 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
1685
1686 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
1687
1688 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
1689
1690 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
1691
1692 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
1693
1694 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
1695
1696 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
1697
1698 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
1699
1700 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
1701
1702 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
1703
1704 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
1705
1706 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
1707
1708 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
1709
1710 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
1711
1712 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
1713
1714 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
1715
1716 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
1717
1718 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
1719
1720 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
1721
1722 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
1723
1724 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
1725
1726 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
1727
1728 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
1729
1730 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
1731
1732 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
1733
1734 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
1735
1736 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
1737
1738 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
1739
1740 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
1741
1742 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
1743
1744 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
1745
1746 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
1747
1748 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
1749
1750 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
1751
1752 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
1753
1754 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
1755
1756 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
1757
1758 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
1759
1760 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
1761
1762 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
1763
1764 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
1765
1766 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
1767
1768 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
1769
1770 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
1771
1772 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
1773
1774 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
1775
1776 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
1777
1778 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
1779
1780 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
1781
1782 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
1783
1784 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
1785
1786 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
1787
1788 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
1789
1790 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
1791
1792 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
1793
1794 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
1795
1796 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
1797
1798 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
1799
1800 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
1801
1802 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1803
1804 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1805
1806 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1807
1808 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1809
1810 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
1811
1812 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
1813
1814 #define REG_A5XX_RBBM_STATUS 0x000004f5
1815 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
1816 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
1817 #define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1818 #define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
1819 #define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
1820 #define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
1821 #define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
1822 #define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
1823 #define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
1824 #define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
1825 #define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
1826 #define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1827 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1828 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
1829 #define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
1830 #define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
1831 #define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
1832 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
1833 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
1834 #define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
1835 #define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
1836 #define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
1837 #define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
1838 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
1839 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
1840 #define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
1841 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
1842 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
1843 #define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
1844 #define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1845 #define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1846 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
1847
1848 #define REG_A5XX_RBBM_STATUS3 0x00000530
1849
1850 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
1851
1852 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
1853
1854 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
1855
1856 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
1857
1858 #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
1859
1860 #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
1861
1862 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
1863
1864 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
1865
1866 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
1867
1868 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
1869
1870 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
1871
1872 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
1873
1874 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1875
1876 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1877
1878 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1879
1880 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1881
1882 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
1883
1884 #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
1885
1886 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
1887
1888 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
1889
1890 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
1891
1892 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
1893
1894 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
1895
1896 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
1897
1898 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
1899
1900 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
1901
1902 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
1903
1904 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
1905
1906 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
1907
1908 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
1909
1910 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
1911
1912 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
1913
1914 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
1915
1916 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
1917
1918 #define REG_A5XX_RBBM_ISDB_CNT 0x00000533
1919
1920 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
1921
1922 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1923
1924 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1925
1926 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1927
1928 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1929
1930 #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1931
1932 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
1933
1934 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
1935
1936 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
1937
1938 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
1939
1940 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1941
1942 #define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
1943 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
1944 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1945 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1946 {
1947 assert(!(val & 0x1f));
1948 return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
1949 }
1950 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
1951 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
1952 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1953 {
1954 assert(!(val & 0x1f));
1955 return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
1956 }
1957
1958 #define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
1959
1960 #define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
1961
1962 #define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
1963
1964 #define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
1965
1966 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
1967
1968 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
1969 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1970 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1971 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1972 {
1973 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
1974 }
1975 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1976 #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1977 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1978 {
1979 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1980 }
1981 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1982 #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1983 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1984 {
1985 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
1986 }
1987 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1988 #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
1989 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1990 {
1991 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
1992 }
1993
1994 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
1995
1996 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
1997
1998 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
1999
2000 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2001
2002 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2003
2004 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
2005
2006 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
2007
2008 #define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
2009 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
2010 #define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
2011 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
2012 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
2013 {
2014 return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
2015 }
2016 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
2017 #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
2018 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
2019 {
2020 return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
2021 }
2022
2023 #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
2024
2025 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
2026
2027 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
2028
2029 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
2030
2031 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
2032
2033 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
2034
2035 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
2036
2037 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
2038
2039 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
2040
2041 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
2042
2043 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
2044
2045 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
2046
2047 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
2048
2049 #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
2050
2051 #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
2052
2053 #define REG_A5XX_RB_MODE_CNTL 0x00000cc6
2054
2055 #define REG_A5XX_RB_CCU_CNTL 0x00000cc7
2056
2057 #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
2058
2059 #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
2060
2061 #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
2062
2063 #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
2064
2065 #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
2066
2067 #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
2068
2069 #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
2070
2071 #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
2072
2073 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
2074
2075 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
2076
2077 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
2078
2079 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
2080
2081 #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
2082
2083 #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
2084
2085 #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
2086
2087 #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
2088
2089 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
2090
2091 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
2092
2093 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
2094
2095 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
2096
2097 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
2098
2099 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
2100
2101 #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
2102 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
2103
2104 #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
2105
2106 #define REG_A5XX_PC_MODE_CNTL 0x00000d02
2107
2108 #define REG_A5XX_UNKNOWN_0D08 0x00000d08
2109
2110 #define REG_A5XX_UNKNOWN_0D09 0x00000d09
2111
2112 #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2113
2114 #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
2115
2116 #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
2117
2118 #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
2119
2120 #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
2121
2122 #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
2123
2124 #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
2125
2126 #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2127
2128 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
2129
2130 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
2131
2132 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
2133
2134 #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
2135
2136 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
2137
2138 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
2139
2140 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
2141
2142 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
2143
2144 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
2145
2146 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
2147
2148 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
2149
2150 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
2151
2152 #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
2153
2154 #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
2155
2156 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
2157
2158 #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
2159
2160 #define REG_A5XX_VFD_MODE_CNTL 0x00000e42
2161
2162 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
2163
2164 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
2165
2166 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
2167
2168 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
2169
2170 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
2171
2172 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
2173
2174 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
2175
2176 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
2177
2178 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
2179
2180 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
2181
2182 #define REG_A5XX_VPC_MODE_CNTL 0x00000e62
2183 #define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
2184
2185 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
2186
2187 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
2188
2189 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
2190
2191 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
2192
2193 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
2194
2195 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
2196
2197 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
2198
2199 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
2200
2201 #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
2202
2203 #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
2204
2205 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
2206
2207 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
2208
2209 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
2210
2211 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
2212
2213 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
2214
2215 #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
2216
2217 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
2218
2219 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
2220
2221 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
2222
2223 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
2224
2225 #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
2226
2227 #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
2228
2229 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
2230
2231 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
2232
2233 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
2234
2235 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
2236
2237 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
2238
2239 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
2240
2241 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
2242
2243 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
2244
2245 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
2246
2247 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
2248
2249 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
2250
2251 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
2252
2253 #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
2254
2255 #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
2256
2257 #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
2258
2259 #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
2260
2261 #define REG_A5XX_SP_MODE_CNTL 0x00000ec2
2262
2263 #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
2264
2265 #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
2266
2267 #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
2268
2269 #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
2270
2271 #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
2272
2273 #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
2274
2275 #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
2276
2277 #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
2278
2279 #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
2280
2281 #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
2282
2283 #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
2284
2285 #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
2286
2287 #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
2288
2289 #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
2290
2291 #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
2292
2293 #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
2294
2295 #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
2296
2297 #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
2298
2299 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
2300
2301 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
2302
2303 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
2304
2305 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
2306
2307 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
2308
2309 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
2310
2311 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
2312
2313 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
2314
2315 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
2316
2317 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
2318
2319 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
2320
2321 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
2322
2323 #define REG_A5XX_VBIF_VERSION 0x00003000
2324
2325 #define REG_A5XX_VBIF_CLKON 0x00003001
2326
2327 #define REG_A5XX_VBIF_ABIT_SORT 0x00003028
2328
2329 #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
2330
2331 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2332
2333 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2334
2335 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2336
2337 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2338
2339 #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
2340
2341 #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
2342
2343 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
2344
2345 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
2346
2347 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
2348
2349 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
2350
2351 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
2352
2353 #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
2354
2355 #define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0
2356
2357 #define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1
2358
2359 #define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2
2360
2361 #define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3
2362
2363 #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
2364
2365 #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
2366
2367 #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
2368
2369 #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
2370
2371 #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
2372
2373 #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
2374
2375 #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
2376
2377 #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
2378
2379 #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
2380
2381 #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
2382
2383 #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
2384
2385 #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
2386
2387 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
2388
2389 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
2390
2391 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
2392
2393 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
2394
2395 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
2396
2397 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
2398
2399 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
2400
2401 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
2402
2403 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2404
2405 #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
2406
2407 #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
2408
2409 #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
2410
2411 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
2412
2413 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
2414
2415 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
2416 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
2417
2418 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
2419 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
2420
2421 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
2422
2423 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
2424
2425 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
2426
2427 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
2428
2429 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
2430
2431 #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
2432
2433 #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
2434
2435 #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
2436
2437 #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
2438
2439 #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
2440
2441 #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
2442
2443 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
2444
2445 #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
2446
2447 #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
2448
2449 #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
2450
2451 #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
2452
2453 #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
2454
2455 #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
2456
2457 #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
2458
2459 #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
2460
2461 #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
2462
2463 #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
2464
2465 #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
2466
2467 #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
2468
2469 #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
2470
2471 #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
2472
2473 #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
2474
2475 #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
2476
2477 #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
2478
2479 #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
2480
2481 #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
2482
2483 #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
2484
2485 #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
2486
2487 #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
2488
2489 #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
2490
2491 #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
2492
2493 #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
2494
2495 #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
2496
2497 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
2498
2499 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
2500
2501 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
2502
2503 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
2504
2505 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
2506
2507 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
2508
2509 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
2510
2511 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
2512
2513 #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
2514
2515 #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
2516
2517 #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
2518
2519 #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
2520
2521 #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
2522
2523 #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
2524
2525 #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
2526
2527 #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
2528
2529 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
2530
2531 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
2532
2533 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
2534
2535 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
2536
2537 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
2538
2539 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
2540
2541 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
2542
2543 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
2544
2545 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
2546
2547 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
2548
2549 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
2550
2551 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
2552
2553 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
2554
2555 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
2556
2557 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
2558
2559 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
2560
2561 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
2562
2563 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
2564
2565 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
2566
2567 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
2568
2569 #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
2570
2571 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
2572
2573 #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
2574
2575 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
2576
2577 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
2578
2579 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
2580
2581 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
2582
2583 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
2584
2585 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
2586
2587 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
2588
2589 #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
2590
2591 #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
2592
2593 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
2594
2595 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
2596
2597 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
2598
2599 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
2600
2601 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
2602
2603 #define REG_A5XX_GDPM_CONFIG1 0x0000b80c
2604
2605 #define REG_A5XX_GDPM_CONFIG2 0x0000b80d
2606
2607 #define REG_A5XX_GDPM_INT_EN 0x0000b80f
2608
2609 #define REG_A5XX_GDPM_INT_MASK 0x0000b811
2610
2611 #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
2612
2613 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
2614
2615 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
2616
2617 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
2618
2619 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
2620
2621 #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
2622
2623 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
2624
2625 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000
2626 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2627
2628 #define REG_A5XX_UNKNOWN_E001 0x0000e001
2629
2630 #define REG_A5XX_UNKNOWN_E004 0x0000e004
2631
2632 #define REG_A5XX_GRAS_CNTL 0x0000e005
2633 #define A5XX_GRAS_CNTL_VARYING 0x00000001
2634 #define A5XX_GRAS_CNTL_UNK3 0x00000008
2635 #define A5XX_GRAS_CNTL_XCOORD 0x00000040
2636 #define A5XX_GRAS_CNTL_YCOORD 0x00000080
2637 #define A5XX_GRAS_CNTL_ZCOORD 0x00000100
2638 #define A5XX_GRAS_CNTL_WCOORD 0x00000200
2639
2640 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
2641 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
2642 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
2643 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2644 {
2645 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2646 }
2647 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
2648 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
2649 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2650 {
2651 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2652 }
2653
2654 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
2655 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2656 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2657 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2658 {
2659 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2660 }
2661
2662 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
2663 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2664 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2665 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
2666 {
2667 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2668 }
2669
2670 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
2671 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2672 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2673 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2674 {
2675 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2676 }
2677
2678 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
2679 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2680 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2681 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
2682 {
2683 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2684 }
2685
2686 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
2687 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2688 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2689 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2690 {
2691 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2692 }
2693
2694 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
2695 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2696 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2697 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2698 {
2699 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2700 }
2701
2702 #define REG_A5XX_GRAS_SU_CNTL 0x0000e090
2703 #define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2704 #define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2705 #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2706 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2707 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
2708 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2709 {
2710 return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2711 }
2712 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2713 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2714
2715 #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
2716 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2717 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2718 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2719 {
2720 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2721 }
2722 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2723 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2724 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2725 {
2726 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2727 }
2728
2729 #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
2730 #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2731 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
2732 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
2733 {
2734 return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
2735 }
2736
2737 #define REG_A5XX_UNKNOWN_E093 0x0000e093
2738
2739 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
2740 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2741 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002
2742
2743 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
2744 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2745 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2746 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2747 {
2748 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2749 }
2750
2751 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
2752 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2753 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2754 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2755 {
2756 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2757 }
2758
2759 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
2760 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2761 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2762 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2763 {
2764 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2765 }
2766
2767 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
2768 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2769 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2770 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2771 {
2772 return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2773 }
2774
2775 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
2776
2777 #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
2778 #define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
2779 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
2780
2781 #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
2782
2783 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
2784 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2785 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2786 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2787 {
2788 return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
2789 }
2790
2791 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
2792 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2793 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2794 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2795 {
2796 return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
2797 }
2798 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2799
2800 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
2801
2802 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
2803 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2804 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2805 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2806 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2807 {
2808 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2809 }
2810 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2811 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2812 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2813 {
2814 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2815 }
2816
2817 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
2818 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2819 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
2820 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
2821 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2822 {
2823 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2824 }
2825 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
2826 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
2827 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2828 {
2829 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2830 }
2831
2832 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
2833 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2834 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
2835 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
2836 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2837 {
2838 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2839 }
2840 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
2841 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
2842 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2843 {
2844 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2845 }
2846
2847 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
2848 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2849 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
2850 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
2851 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2852 {
2853 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2854 }
2855 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
2856 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
2857 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2858 {
2859 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2860 }
2861
2862 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
2863 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2864 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2865 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2866 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2867 {
2868 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2869 }
2870 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2871 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2872 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2873 {
2874 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2875 }
2876
2877 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
2878 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2879 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2880 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2881 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2882 {
2883 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2884 }
2885 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2886 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2887 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2888 {
2889 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2890 }
2891
2892 #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
2893 #define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2894 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2895 #define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2896
2897 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
2898
2899 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
2900
2901 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
2902 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff
2903 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0
2904 static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
2905 {
2906 assert(!(val & 0x1f));
2907 return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
2908 }
2909
2910 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
2911
2912 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
2913
2914 #define REG_A5XX_RB_CNTL 0x0000e140
2915 #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
2916 #define A5XX_RB_CNTL_WIDTH__SHIFT 0
2917 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
2918 {
2919 assert(!(val & 0x1f));
2920 return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
2921 }
2922 #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
2923 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9
2924 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
2925 {
2926 assert(!(val & 0x1f));
2927 return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
2928 }
2929 #define A5XX_RB_CNTL_BYPASS 0x00020000
2930
2931 #define REG_A5XX_RB_RENDER_CNTL 0x0000e141
2932 #define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
2933 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
2934 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
2935 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
2936 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
2937 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
2938 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
2939 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
2940 {
2941 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
2942 }
2943 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
2944 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
2945 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
2946 {
2947 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
2948 }
2949
2950 #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
2951 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2952 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2953 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2954 {
2955 return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
2956 }
2957
2958 #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
2959 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2960 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2961 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2962 {
2963 return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
2964 }
2965 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2966
2967 #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
2968 #define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
2969 #define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008
2970 #define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
2971 #define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
2972 #define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
2973 #define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
2974
2975 #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
2976 #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
2977
2978 #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
2979 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
2980 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
2981 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
2982 {
2983 return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
2984 }
2985 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
2986
2987 #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
2988 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
2989 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
2990 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
2991 {
2992 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
2993 }
2994 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
2995 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
2996 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
2997 {
2998 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
2999 }
3000 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3001 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
3002 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3003 {
3004 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
3005 }
3006 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3007 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
3008 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3009 {
3010 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
3011 }
3012 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3013 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
3014 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3015 {
3016 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
3017 }
3018 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3019 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
3020 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3021 {
3022 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
3023 }
3024 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3025 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
3026 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3027 {
3028 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
3029 }
3030 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3031 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
3032 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3033 {
3034 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
3035 }
3036
3037 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3038
3039 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3040 #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
3041 #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
3042 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3043 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
3044 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3045 {
3046 return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3047 }
3048
3049 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
3050 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3051 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
3052 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3053 {
3054 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3055 }
3056 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3057 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
3058 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3059 {
3060 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3061 }
3062 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3063 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
3064 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3065 {
3066 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3067 }
3068 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3069 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
3070 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3071 {
3072 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3073 }
3074 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3075 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
3076 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3077 {
3078 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3079 }
3080 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3081 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
3082 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3083 {
3084 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3085 }
3086
3087 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
3088 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3089 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
3090 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3091 {
3092 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3093 }
3094 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3095 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
3096 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
3097 {
3098 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3099 }
3100 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3101 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
3102 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3103 {
3104 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3105 }
3106 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
3107
3108 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
3109 #define A5XX_RB_MRT_PITCH__MASK 0xffffffff
3110 #define A5XX_RB_MRT_PITCH__SHIFT 0
3111 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
3112 {
3113 assert(!(val & 0x3f));
3114 return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
3115 }
3116
3117 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
3118 #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
3119 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
3120 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3121 {
3122 assert(!(val & 0x3f));
3123 return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
3124 }
3125
3126 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
3127
3128 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
3129
3130 #define REG_A5XX_RB_BLEND_RED 0x0000e1a0
3131 #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
3132 #define A5XX_RB_BLEND_RED_UINT__SHIFT 0
3133 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
3134 {
3135 return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
3136 }
3137 #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
3138 #define A5XX_RB_BLEND_RED_SINT__SHIFT 8
3139 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
3140 {
3141 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
3142 }
3143 #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
3144 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
3145 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3146 {
3147 return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3148 }
3149
3150 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
3151 #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
3152 #define A5XX_RB_BLEND_RED_F32__SHIFT 0
3153 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
3154 {
3155 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
3156 }
3157
3158 #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
3159 #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
3160 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
3161 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
3162 {
3163 return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
3164 }
3165 #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
3166 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
3167 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
3168 {
3169 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
3170 }
3171 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
3172 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
3173 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3174 {
3175 return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3176 }
3177
3178 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
3179 #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3180 #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
3181 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
3182 {
3183 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
3184 }
3185
3186 #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
3187 #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
3188 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
3189 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
3190 {
3191 return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
3192 }
3193 #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
3194 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
3195 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
3196 {
3197 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
3198 }
3199 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
3200 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
3201 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3202 {
3203 return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3204 }
3205
3206 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
3207 #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3208 #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
3209 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
3210 {
3211 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
3212 }
3213
3214 #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
3215 #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
3216 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
3217 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
3218 {
3219 return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
3220 }
3221 #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
3222 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
3223 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
3224 {
3225 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
3226 }
3227 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
3228 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
3229 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3230 {
3231 return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3232 }
3233
3234 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
3235 #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3236 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
3237 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
3238 {
3239 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
3240 }
3241
3242 #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
3243 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3244 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
3245 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3246 {
3247 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3248 }
3249 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3250 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3251 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
3252 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3253 {
3254 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3255 }
3256
3257 #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
3258 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3259 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
3260 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3261 {
3262 return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3263 }
3264 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3265 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3266 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
3267 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3268 {
3269 return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3270 }
3271
3272 #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
3273 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
3274 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
3275
3276 #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
3277 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
3278 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3279 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3280 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
3281 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3282 {
3283 return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3284 }
3285 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
3286
3287 #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
3288 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
3289 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
3290 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
3291 {
3292 return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3293 }
3294
3295 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
3296
3297 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
3298
3299 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
3300 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
3301 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
3302 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3303 {
3304 assert(!(val & 0x3f));
3305 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
3306 }
3307
3308 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
3309 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3310 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
3311 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3312 {
3313 assert(!(val & 0x3f));
3314 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3315 }
3316
3317 #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
3318 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
3319 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
3320 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
3321 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
3322 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
3323 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3324 {
3325 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
3326 }
3327 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
3328 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
3329 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3330 {
3331 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
3332 }
3333 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
3334 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
3335 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3336 {
3337 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3338 }
3339 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
3340 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
3341 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3342 {
3343 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3344 }
3345 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3346 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
3347 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3348 {
3349 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3350 }
3351 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3352 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
3353 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3354 {
3355 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3356 }
3357 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3358 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
3359 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3360 {
3361 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3362 }
3363 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3364 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
3365 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3366 {
3367 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3368 }
3369
3370 #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
3371 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3372
3373 #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
3374
3375 #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
3376
3377 #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
3378 #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
3379 #define A5XX_RB_STENCIL_PITCH__SHIFT 0
3380 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
3381 {
3382 assert(!(val & 0x3f));
3383 return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
3384 }
3385
3386 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
3387 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
3388 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
3389 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
3390 {
3391 assert(!(val & 0x3f));
3392 return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
3393 }
3394
3395 #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
3396 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
3397 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
3398 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
3399 {
3400 return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
3401 }
3402 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
3403 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
3404 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
3405 {
3406 return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
3407 }
3408 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
3409 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
3410 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
3411 {
3412 return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
3413 }
3414
3415 #define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7
3416
3417 #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
3418 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
3419 #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
3420 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
3421 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
3422 {
3423 return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
3424 }
3425 #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
3426 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
3427 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3428 {
3429 return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
3430 }
3431
3432 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1
3433 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3434
3435 #define REG_A5XX_RB_BLIT_CNTL 0x0000e210
3436 #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
3437 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
3438 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
3439 {
3440 return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
3441 }
3442
3443 #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
3444 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
3445 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
3446 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
3447 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
3448 {
3449 return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
3450 }
3451 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
3452 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
3453 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
3454 {
3455 return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
3456 }
3457
3458 #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
3459 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
3460 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
3461 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
3462 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
3463 {
3464 return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
3465 }
3466 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
3467 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
3468 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
3469 {
3470 return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
3471 }
3472
3473 #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
3474
3475 #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
3476
3477 #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
3478
3479 #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
3480 #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
3481 #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
3482 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
3483 {
3484 assert(!(val & 0x3f));
3485 return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
3486 }
3487
3488 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
3489 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
3490 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
3491 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3492 {
3493 assert(!(val & 0x3f));
3494 return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3495 }
3496
3497 #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
3498
3499 #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
3500
3501 #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
3502
3503 #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
3504
3505 #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
3506 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
3507 #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
3508 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
3509 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
3510 {
3511 return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
3512 }
3513
3514 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
3515
3516 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
3517
3518 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
3519
3520 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3521
3522 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3523
3524 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
3525
3526 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
3527 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
3528 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
3529 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
3530 {
3531 assert(!(val & 0x3f));
3532 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
3533 }
3534
3535 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
3536 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3537 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
3538 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
3539 {
3540 assert(!(val & 0x3f));
3541 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
3542 }
3543
3544 #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
3545
3546 #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
3547
3548 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
3549 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
3550 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
3551 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
3552 {
3553 assert(!(val & 0x3f));
3554 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
3555 }
3556
3557 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
3558 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
3559 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
3560 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
3561 {
3562 assert(!(val & 0x3f));
3563 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
3564 }
3565
3566 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
3567
3568 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268
3569
3570 #define REG_A5XX_VPC_CNTL_0 0x0000e280
3571 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
3572 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
3573 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
3574 {
3575 return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
3576 }
3577 #define A5XX_VPC_CNTL_0_VARYING 0x00000800
3578
3579 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3580
3581 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3582
3583 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3584
3585 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3586
3587 #define REG_A5XX_UNKNOWN_E292 0x0000e292
3588
3589 #define REG_A5XX_UNKNOWN_E293 0x0000e293
3590
3591 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3592
3593 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3594
3595 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
3596
3597 #define REG_A5XX_UNKNOWN_E29A 0x0000e29a
3598
3599 #define REG_A5XX_VPC_PACK 0x0000e29d
3600 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
3601 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
3602 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3603 {
3604 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
3605 }
3606 #define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00
3607 #define A5XX_VPC_PACK_PSIZELOC__SHIFT 8
3608 static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
3609 {
3610 return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
3611 }
3612
3613 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
3614
3615 #define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
3616 #define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
3617 #define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
3618 #define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
3619 #define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
3620 #define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
3621
3622 #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
3623 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
3624
3625 #define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
3626 #define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
3627
3628 #define REG_A5XX_VPC_SO_PROG 0x0000e2a4
3629 #define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
3630 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
3631 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
3632 {
3633 return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
3634 }
3635 #define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
3636 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
3637 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
3638 {
3639 assert(!(val & 0x3));
3640 return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
3641 }
3642 #define A5XX_VPC_SO_PROG_A_EN 0x00000800
3643 #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
3644 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
3645 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
3646 {
3647 return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
3648 }
3649 #define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
3650 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
3651 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
3652 {
3653 assert(!(val & 0x3));
3654 return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
3655 }
3656 #define A5XX_VPC_SO_PROG_B_EN 0x00800000
3657
3658 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3659
3660 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3661
3662 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
3663
3664 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
3665
3666 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
3667
3668 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
3669
3670 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
3671
3672 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
3673
3674 #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
3675 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
3676 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
3677 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
3678 {
3679 return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
3680 }
3681 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
3682
3683 #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
3684 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
3685
3686 #define REG_A5XX_PC_RASTER_CNTL 0x0000e388
3687
3688 #define REG_A5XX_UNKNOWN_E389 0x0000e389
3689
3690 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
3691
3692 #define REG_A5XX_UNKNOWN_E38D 0x0000e38d
3693
3694 #define REG_A5XX_PC_GS_PARAM 0x0000e38e
3695
3696 #define REG_A5XX_PC_HS_PARAM 0x0000e38f
3697
3698 #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
3699
3700 #define REG_A5XX_VFD_CONTROL_0 0x0000e400
3701 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
3702 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
3703 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
3704 {
3705 return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
3706 }
3707
3708 #define REG_A5XX_VFD_CONTROL_1 0x0000e401
3709 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
3710 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
3711 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
3712 {
3713 return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
3714 }
3715 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
3716 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
3717 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
3718 {
3719 return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
3720 }
3721
3722 #define REG_A5XX_VFD_CONTROL_2 0x0000e402
3723
3724 #define REG_A5XX_VFD_CONTROL_3 0x0000e403
3725
3726 #define REG_A5XX_VFD_CONTROL_4 0x0000e404
3727
3728 #define REG_A5XX_VFD_CONTROL_5 0x0000e405
3729
3730 #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
3731
3732 #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
3733
3734 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
3735
3736 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
3737
3738 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
3739
3740 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
3741
3742 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
3743
3744 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
3745
3746 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
3747 #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
3748 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
3749 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
3750 {
3751 return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
3752 }
3753 #define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
3754 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
3755 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
3756 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
3757 {
3758 return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
3759 }
3760 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
3761 #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
3762 static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3763 {
3764 return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
3765 }
3766 #define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
3767 #define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
3768
3769 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
3770
3771 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
3772
3773 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
3774 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
3775 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
3776 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
3777 {
3778 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
3779 }
3780 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
3781 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
3782 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
3783 {
3784 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
3785 }
3786
3787 #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
3788
3789 #define REG_A5XX_SP_SP_CNTL 0x0000e580
3790
3791 #define REG_A5XX_SP_VS_CONFIG 0x0000e584
3792 #define A5XX_SP_VS_CONFIG_ENABLED 0x00000001
3793 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3794 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3795 static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3796 {
3797 return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
3798 }
3799 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3800 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3801 static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3802 {
3803 return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
3804 }
3805
3806 #define REG_A5XX_SP_FS_CONFIG 0x0000e585
3807 #define A5XX_SP_FS_CONFIG_ENABLED 0x00000001
3808 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3809 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3810 static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3811 {
3812 return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
3813 }
3814 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3815 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3816 static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3817 {
3818 return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
3819 }
3820
3821 #define REG_A5XX_SP_HS_CONFIG 0x0000e586
3822 #define A5XX_SP_HS_CONFIG_ENABLED 0x00000001
3823 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3824 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3825 static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3826 {
3827 return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
3828 }
3829 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3830 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3831 static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3832 {
3833 return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
3834 }
3835
3836 #define REG_A5XX_SP_DS_CONFIG 0x0000e587
3837 #define A5XX_SP_DS_CONFIG_ENABLED 0x00000001
3838 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3839 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3840 static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3841 {
3842 return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
3843 }
3844 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3845 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3846 static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3847 {
3848 return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
3849 }
3850
3851 #define REG_A5XX_SP_GS_CONFIG 0x0000e588
3852 #define A5XX_SP_GS_CONFIG_ENABLED 0x00000001
3853 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3854 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3855 static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3856 {
3857 return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
3858 }
3859 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3860 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3861 static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3862 {
3863 return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
3864 }
3865
3866 #define REG_A5XX_SP_CS_CONFIG 0x0000e589
3867 #define A5XX_SP_CS_CONFIG_ENABLED 0x00000001
3868 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3869 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3870 static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3871 {
3872 return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
3873 }
3874 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3875 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3876 static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3877 {
3878 return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
3879 }
3880
3881 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
3882
3883 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
3884
3885 #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
3886 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008
3887 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3
3888 static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
3889 {
3890 return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
3891 }
3892 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3893 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3894 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3895 {
3896 return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3897 }
3898 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3899 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3900 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3901 {
3902 return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3903 }
3904 #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
3905 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
3906 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
3907 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
3908 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
3909 {
3910 return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
3911 }
3912
3913 #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
3914 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
3915 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
3916 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
3917 {
3918 return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
3919 }
3920
3921 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
3922
3923 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
3924 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
3925 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
3926 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
3927 {
3928 return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
3929 }
3930 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
3931 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
3932 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
3933 {
3934 return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
3935 }
3936 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
3937 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
3938 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
3939 {
3940 return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
3941 }
3942 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
3943 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
3944 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
3945 {
3946 return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
3947 }
3948
3949 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
3950
3951 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
3952 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
3953 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
3954 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
3955 {
3956 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
3957 }
3958 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
3959 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
3960 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
3961 {
3962 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
3963 }
3964 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
3965 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
3966 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
3967 {
3968 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
3969 }
3970 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
3971 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
3972 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
3973 {
3974 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
3975 }
3976
3977 #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
3978
3979 #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
3980
3981 #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
3982
3983 #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
3984 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
3985 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3
3986 static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
3987 {
3988 return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
3989 }
3990 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3991 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3992 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3993 {
3994 return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3995 }
3996 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3997 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3998 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3999 {
4000 return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4001 }
4002 #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
4003 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
4004 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4005 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4006 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4007 {
4008 return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4009 }
4010
4011 #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
4012
4013 #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
4014
4015 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
4016
4017 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
4018 #define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
4019 #define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
4020
4021 #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
4022 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
4023 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
4024 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
4025 {
4026 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
4027 }
4028 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
4029 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
4030 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
4031 {
4032 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
4033 }
4034 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
4035 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
4036 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
4037 {
4038 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
4039 }
4040
4041 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4042
4043 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4044 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
4045 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
4046 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4047 {
4048 return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
4049 }
4050 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
4051
4052 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4053
4054 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4055 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
4056 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
4057 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
4058 {
4059 return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4060 }
4061 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
4062
4063 #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
4064
4065 #define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
4066
4067 #define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
4068
4069 #define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
4070
4071 #define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
4072 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4073 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
4074 static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4075 {
4076 return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4077 }
4078 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4079 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4080 static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4081 {
4082 return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4083 }
4084 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4085 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4086 static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4087 {
4088 return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4089 }
4090 #define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000
4091 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000
4092 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4093 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4094 static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4095 {
4096 return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4097 }
4098
4099 #define REG_A5XX_UNKNOWN_E600 0x0000e600
4100
4101 #define REG_A5XX_UNKNOWN_E602 0x0000e602
4102
4103 #define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603
4104
4105 #define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
4106
4107 #define REG_A5XX_UNKNOWN_E62B 0x0000e62b
4108
4109 #define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
4110
4111 #define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
4112
4113 #define REG_A5XX_UNKNOWN_E640 0x0000e640
4114
4115 #define REG_A5XX_UNKNOWN_E65B 0x0000e65b
4116
4117 #define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c
4118
4119 #define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
4120
4121 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
4122 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
4123 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
4124 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4125 {
4126 return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4127 }
4128
4129 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
4130 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
4131 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
4132 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4133 {
4134 return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4135 }
4136 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
4137
4138 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
4139
4140 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
4141
4142 #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
4143
4144 #define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701
4145
4146 #define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702
4147
4148 #define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703
4149
4150 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
4151
4152 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
4153
4154 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724
4155
4156 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725
4157
4158 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726
4159
4160 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727
4161
4162 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728
4163
4164 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729
4165
4166 #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
4167
4168 #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
4169
4170 #define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c
4171
4172 #define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d
4173
4174 #define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e
4175
4176 #define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f
4177
4178 #define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730
4179
4180 #define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731
4181
4182 #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
4183
4184 #define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751
4185
4186 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
4187
4188 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
4189
4190 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
4191
4192 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d
4193
4194 #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
4195
4196 #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
4197
4198 #define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
4199
4200 #define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761
4201
4202 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
4203
4204 #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
4205 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001
4206 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0
4207 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
4208 {
4209 return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
4210 }
4211 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004
4212 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2
4213 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
4214 {
4215 return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
4216 }
4217
4218 #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
4219 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
4220 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
4221 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
4222 {
4223 return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
4224 }
4225
4226 #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
4227 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
4228 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
4229 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4230 {
4231 return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4232 }
4233
4234 #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
4235 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
4236 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
4237 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
4238 {
4239 return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
4240 }
4241
4242 #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
4243 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
4244 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
4245 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4246 {
4247 return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4248 }
4249 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
4250 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
4251 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4252 {
4253 return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4254 }
4255
4256 #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
4257
4258 #define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b
4259 #define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001
4260 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4261 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4262 static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4263 {
4264 return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4265 }
4266 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4267 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4268 static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4269 {
4270 return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
4271 }
4272
4273 #define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c
4274 #define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001
4275 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4276 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4277 static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4278 {
4279 return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4280 }
4281 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4282 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4283 static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4284 {
4285 return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
4286 }
4287
4288 #define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d
4289 #define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001
4290 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4291 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4292 static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4293 {
4294 return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4295 }
4296 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4297 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4298 static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4299 {
4300 return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
4301 }
4302
4303 #define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e
4304 #define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001
4305 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4306 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4307 static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4308 {
4309 return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4310 }
4311 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4312 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4313 static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4314 {
4315 return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
4316 }
4317
4318 #define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f
4319 #define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001
4320 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4321 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4322 static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4323 {
4324 return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4325 }
4326 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4327 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4328 static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4329 {
4330 return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
4331 }
4332
4333 #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
4334 #define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001
4335 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4336 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4337 static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4338 {
4339 return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4340 }
4341 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4342 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4343 static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4344 {
4345 return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
4346 }
4347
4348 #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
4349 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001
4350 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
4351 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
4352 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
4353 {
4354 return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
4355 }
4356
4357 #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
4358 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001
4359 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
4360 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
4361 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
4362 {
4363 return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
4364 }
4365
4366 #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
4367 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001
4368 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
4369 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
4370 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
4371 {
4372 return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
4373 }
4374
4375 #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
4376 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001
4377 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
4378 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
4379 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
4380 {
4381 return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
4382 }
4383
4384 #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
4385 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001
4386 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
4387 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
4388 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
4389 {
4390 return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
4391 }
4392
4393 #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
4394 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001
4395 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
4396 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
4397 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
4398 {
4399 return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
4400 }
4401
4402 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
4403
4404 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
4405
4406 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
4407
4408 #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
4409 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
4410 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
4411 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4412 {
4413 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4414 }
4415 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
4416 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
4417 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4418 {
4419 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4420 }
4421 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
4422 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
4423 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4424 {
4425 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4426 }
4427 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
4428 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
4429 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4430 {
4431 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4432 }
4433
4434 #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
4435 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK 0xffffffff
4436 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT 0
4437 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(uint32_t val)
4438 {
4439 return ((val) << A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK;
4440 }
4441
4442 #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
4443
4444 #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
4445 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK 0xffffffff
4446 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT 0
4447 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(uint32_t val)
4448 {
4449 return ((val) << A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK;
4450 }
4451
4452 #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
4453
4454 #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
4455 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK 0xffffffff
4456 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT 0
4457 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(uint32_t val)
4458 {
4459 return ((val) << A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK;
4460 }
4461
4462 #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
4463
4464 #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
4465 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
4466 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
4467 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
4468 {
4469 return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
4470 }
4471 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
4472 #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
4473 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
4474 {
4475 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
4476 }
4477 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
4478 #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
4479 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
4480 {
4481 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
4482 }
4483 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
4484 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
4485 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
4486 {
4487 return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
4488 }
4489
4490 #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
4491
4492 #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
4493
4494 #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
4495
4496 #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
4497
4498 #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
4499
4500 #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
4501
4502 #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
4503
4504 #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
4505
4506 #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
4507
4508 #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
4509
4510 #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
4511
4512 #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
4513
4514 #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
4515
4516 #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
4517
4518 #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
4519
4520 #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
4521
4522 #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
4523
4524 #define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc
4525
4526 #define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
4527
4528 #define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
4529
4530 #define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
4531
4532 #define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
4533
4534 #define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
4535
4536 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107
4537 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
4538 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
4539 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4540 {
4541 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
4542 }
4543 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
4544 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
4545 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4546 {
4547 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
4548 }
4549
4550 #define REG_A5XX_RB_2D_SRC_LO 0x00002108
4551
4552 #define REG_A5XX_RB_2D_SRC_HI 0x00002109
4553
4554 #define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
4555 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
4556 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
4557 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
4558 {
4559 assert(!(val & 0x3f));
4560 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
4561 }
4562 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
4563 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
4564 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
4565 {
4566 assert(!(val & 0x3f));
4567 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
4568 }
4569
4570 #define REG_A5XX_RB_2D_DST_INFO 0x00002110
4571 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
4572 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
4573 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4574 {
4575 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
4576 }
4577 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
4578 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
4579 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4580 {
4581 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
4582 }
4583
4584 #define REG_A5XX_RB_2D_DST_LO 0x00002111
4585
4586 #define REG_A5XX_RB_2D_DST_HI 0x00002112
4587
4588 #define REG_A5XX_RB_2D_DST_SIZE 0x00002113
4589 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
4590 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
4591 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
4592 {
4593 assert(!(val & 0x3f));
4594 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
4595 }
4596 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
4597 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
4598 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
4599 {
4600 assert(!(val & 0x3f));
4601 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
4602 }
4603
4604 #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
4605
4606 #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
4607
4608 #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
4609
4610 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
4611
4612 #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
4613 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
4614 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
4615 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4616 {
4617 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
4618 }
4619 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
4620 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
4621 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4622 {
4623 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
4624 }
4625
4626 #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
4627 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
4628 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
4629 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4630 {
4631 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
4632 }
4633 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
4634 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
4635 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4636 {
4637 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
4638 }
4639
4640 #define REG_A5XX_UNKNOWN_2100 0x00002100
4641
4642 #define REG_A5XX_UNKNOWN_2180 0x00002180
4643
4644 #define REG_A5XX_UNKNOWN_2184 0x00002184
4645
4646 #define REG_A5XX_TEX_SAMP_0 0x00000000
4647 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
4648 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
4649 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
4650 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
4651 {
4652 return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
4653 }
4654 #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
4655 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
4656 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
4657 {
4658 return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
4659 }
4660 #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
4661 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
4662 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
4663 {
4664 return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
4665 }
4666 #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
4667 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
4668 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
4669 {
4670 return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
4671 }
4672 #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
4673 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
4674 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
4675 {
4676 return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
4677 }
4678 #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
4679 #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
4680 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
4681 {
4682 return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
4683 }
4684 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
4685 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
4686 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
4687 {
4688 return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
4689 }
4690
4691 #define REG_A5XX_TEX_SAMP_1 0x00000001
4692 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
4693 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
4694 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
4695 {
4696 return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
4697 }
4698 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
4699 #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
4700 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
4701 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
4702 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
4703 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
4704 {
4705 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
4706 }
4707 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
4708 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
4709 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
4710 {
4711 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
4712 }
4713
4714 #define REG_A5XX_TEX_SAMP_2 0x00000002
4715 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
4716 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
4717 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
4718 {
4719 return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
4720 }
4721
4722 #define REG_A5XX_TEX_SAMP_3 0x00000003
4723
4724 #define REG_A5XX_TEX_CONST_0 0x00000000
4725 #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
4726 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
4727 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
4728 {
4729 return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
4730 }
4731 #define A5XX_TEX_CONST_0_SRGB 0x00000004
4732 #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
4733 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
4734 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
4735 {
4736 return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
4737 }
4738 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
4739 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
4740 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
4741 {
4742 return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
4743 }
4744 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
4745 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
4746 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
4747 {
4748 return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
4749 }
4750 #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
4751 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
4752 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
4753 {
4754 return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
4755 }
4756 #define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
4757 #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16
4758 static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
4759 {
4760 return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
4761 }
4762 #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
4763 #define A5XX_TEX_CONST_0_FMT__SHIFT 22
4764 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
4765 {
4766 return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
4767 }
4768 #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
4769 #define A5XX_TEX_CONST_0_SWAP__SHIFT 30
4770 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
4771 {
4772 return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
4773 }
4774
4775 #define REG_A5XX_TEX_CONST_1 0x00000001
4776 #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
4777 #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
4778 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
4779 {
4780 return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
4781 }
4782 #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
4783 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
4784 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
4785 {
4786 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
4787 }
4788
4789 #define REG_A5XX_TEX_CONST_2 0x00000002
4790 #define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
4791 #define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
4792 static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val)
4793 {
4794 return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK;
4795 }
4796 #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
4797 #define A5XX_TEX_CONST_2_PITCH__SHIFT 7
4798 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
4799 {
4800 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
4801 }
4802 #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
4803 #define A5XX_TEX_CONST_2_TYPE__SHIFT 29
4804 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
4805 {
4806 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
4807 }
4808
4809 #define REG_A5XX_TEX_CONST_3 0x00000003
4810 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
4811 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
4812 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
4813 {
4814 assert(!(val & 0xfff));
4815 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
4816 }
4817 #define A5XX_TEX_CONST_3_FLAG 0x10000000
4818
4819 #define REG_A5XX_TEX_CONST_4 0x00000004
4820 #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
4821 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
4822 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
4823 {
4824 assert(!(val & 0x1f));
4825 return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
4826 }
4827
4828 #define REG_A5XX_TEX_CONST_5 0x00000005
4829 #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
4830 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
4831 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
4832 {
4833 return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
4834 }
4835 #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
4836 #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
4837 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
4838 {
4839 return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
4840 }
4841
4842 #define REG_A5XX_TEX_CONST_6 0x00000006
4843
4844 #define REG_A5XX_TEX_CONST_7 0x00000007
4845
4846 #define REG_A5XX_TEX_CONST_8 0x00000008
4847
4848 #define REG_A5XX_TEX_CONST_9 0x00000009
4849
4850 #define REG_A5XX_TEX_CONST_10 0x0000000a
4851
4852 #define REG_A5XX_TEX_CONST_11 0x0000000b
4853
4854
4855 #endif /* A5XX_XML */