4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 23277 bytes, from 2016-12-24 05:01:47)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2016-12-26 17:51:07)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 99224 bytes, from 2016-12-26 18:40:41)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
21 Copyright (C) 2013-2016 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
51 RB5_R4G4B4A4_UNORM
= 8,
52 RB5_R5G5B5A1_UNORM
= 10,
53 RB5_R5G6B5_UNORM
= 14,
63 RB5_R8G8B8A8_UNORM
= 48,
64 RB5_R8G8B8_UNORM
= 49,
65 RB5_R8G8B8A8_UINT
= 51,
66 RB5_R8G8B8A8_SINT
= 52,
67 RB5_R10G10B10A2_UNORM
= 55,
68 RB5_R10G10B10A2_UINT
= 58,
69 RB5_R11G11B10_FLOAT
= 66,
70 RB5_R16G16_UNORM
= 67,
71 RB5_R16G16_SNORM
= 68,
72 RB5_R16G16_FLOAT
= 69,
78 RB5_R16G16B16A16_FLOAT
= 98,
79 RB5_R16G16B16A16_UINT
= 99,
80 RB5_R16G16B16A16_SINT
= 100,
81 RB5_R32G32_FLOAT
= 103,
82 RB5_R32G32_UINT
= 104,
83 RB5_R32G32_SINT
= 105,
84 RB5_R32G32B32A32_FLOAT
= 130,
85 RB5_R32G32B32A32_UINT
= 131,
86 RB5_R32G32B32A32_SINT
= 132,
100 VFMT5_8_8_UNORM
= 15,
101 VFMT5_8_8_SNORM
= 16,
109 VFMT5_8_8_8_UNORM
= 33,
110 VFMT5_8_8_8_SNORM
= 34,
111 VFMT5_8_8_8_UINT
= 35,
112 VFMT5_8_8_8_SINT
= 36,
113 VFMT5_8_8_8_8_UNORM
= 48,
114 VFMT5_8_8_8_8_SNORM
= 50,
115 VFMT5_8_8_8_8_UINT
= 51,
116 VFMT5_8_8_8_8_SINT
= 52,
117 VFMT5_16_16_UNORM
= 67,
118 VFMT5_16_16_SNORM
= 68,
119 VFMT5_16_16_FLOAT
= 69,
120 VFMT5_16_16_UINT
= 70,
121 VFMT5_16_16_SINT
= 71,
128 VFMT5_16_16_16_UNORM
= 88,
129 VFMT5_16_16_16_SNORM
= 89,
130 VFMT5_16_16_16_FLOAT
= 90,
131 VFMT5_16_16_16_UINT
= 91,
132 VFMT5_16_16_16_SINT
= 92,
133 VFMT5_16_16_16_16_UNORM
= 96,
134 VFMT5_16_16_16_16_SNORM
= 97,
135 VFMT5_16_16_16_16_FLOAT
= 98,
136 VFMT5_16_16_16_16_UINT
= 99,
137 VFMT5_16_16_16_16_SINT
= 100,
138 VFMT5_32_32_UNORM
= 101,
139 VFMT5_32_32_SNORM
= 102,
140 VFMT5_32_32_FLOAT
= 103,
141 VFMT5_32_32_UINT
= 104,
142 VFMT5_32_32_SINT
= 105,
143 VFMT5_32_32_FIXED
= 106,
144 VFMT5_32_32_32_UNORM
= 112,
145 VFMT5_32_32_32_SNORM
= 113,
146 VFMT5_32_32_32_UINT
= 114,
147 VFMT5_32_32_32_SINT
= 115,
148 VFMT5_32_32_32_FLOAT
= 116,
149 VFMT5_32_32_32_FIXED
= 117,
150 VFMT5_32_32_32_32_UNORM
= 128,
151 VFMT5_32_32_32_32_SNORM
= 129,
152 VFMT5_32_32_32_32_FLOAT
= 130,
153 VFMT5_32_32_32_32_UINT
= 131,
154 VFMT5_32_32_32_32_SINT
= 132,
155 VFMT5_32_32_32_32_FIXED
= 133,
163 TFMT5_4_4_4_4_UNORM
= 8,
164 TFMT5_5_5_5_1_UNORM
= 10,
165 TFMT5_5_6_5_UNORM
= 14,
166 TFMT5_8_8_UNORM
= 15,
167 TFMT5_8_8_SNORM
= 16,
170 TFMT5_L8_A8_UNORM
= 19,
176 TFMT5_8_8_8_8_UNORM
= 48,
177 TFMT5_8_8_8_UNORM
= 49,
178 TFMT5_8_8_8_SNORM
= 50,
179 TFMT5_8_8_8_8_UINT
= 51,
180 TFMT5_8_8_8_8_SINT
= 52,
181 TFMT5_9_9_9_E5_FLOAT
= 53,
182 TFMT5_10_10_10_2_UNORM
= 54,
183 TFMT5_10_10_10_2_UINT
= 58,
184 TFMT5_11_11_10_FLOAT
= 66,
185 TFMT5_16_16_UNORM
= 67,
186 TFMT5_16_16_SNORM
= 68,
187 TFMT5_16_16_FLOAT
= 69,
188 TFMT5_16_16_UINT
= 70,
189 TFMT5_16_16_SINT
= 71,
193 TFMT5_16_16_16_16_FLOAT
= 98,
194 TFMT5_16_16_16_16_UINT
= 99,
195 TFMT5_16_16_16_16_SINT
= 100,
196 TFMT5_32_32_FLOAT
= 103,
197 TFMT5_32_32_UINT
= 104,
198 TFMT5_32_32_SINT
= 105,
199 TFMT5_32_32_32_32_FLOAT
= 130,
200 TFMT5_32_32_32_32_UINT
= 131,
201 TFMT5_32_32_32_32_SINT
= 132,
202 TFMT5_X8Z24_UNORM
= 160,
205 enum a5xx_tex_fetchsize
{
213 enum a5xx_depth_format
{
233 enum a5xx_tex_filter
{
234 A5XX_TEX_NEAREST
= 0,
239 enum a5xx_tex_clamp
{
241 A5XX_TEX_CLAMP_TO_EDGE
= 1,
242 A5XX_TEX_MIRROR_REPEAT
= 2,
243 A5XX_TEX_CLAMP_TO_BORDER
= 3,
244 A5XX_TEX_MIRROR_CLAMP
= 4,
247 enum a5xx_tex_aniso
{
248 A5XX_TEX_ANISO_1
= 0,
249 A5XX_TEX_ANISO_2
= 1,
250 A5XX_TEX_ANISO_4
= 2,
251 A5XX_TEX_ANISO_8
= 3,
252 A5XX_TEX_ANISO_16
= 4,
271 #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
272 #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
273 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
274 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
275 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
276 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
277 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
278 #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
279 #define A5XX_INT0_CP_SW 0x00000100
280 #define A5XX_INT0_CP_HW_ERROR 0x00000200
281 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
282 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
283 #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
284 #define A5XX_INT0_CP_IB2 0x00002000
285 #define A5XX_INT0_CP_IB1 0x00004000
286 #define A5XX_INT0_CP_RB 0x00008000
287 #define A5XX_INT0_CP_UNUSED_1 0x00010000
288 #define A5XX_INT0_CP_RB_DONE_TS 0x00020000
289 #define A5XX_INT0_CP_WT_DONE_TS 0x00040000
290 #define A5XX_INT0_UNKNOWN_1 0x00080000
291 #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
292 #define A5XX_INT0_UNUSED_2 0x00200000
293 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
294 #define A5XX_INT0_MISC_HANG_DETECT 0x00800000
295 #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
296 #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
297 #define A5XX_INT0_DEBBUS_INTR_0 0x04000000
298 #define A5XX_INT0_DEBBUS_INTR_1 0x08000000
299 #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
300 #define A5XX_INT0_GPMU_FIRMWARE 0x20000000
301 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
302 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
303 #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
304 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
305 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
306 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
307 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
308 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
309 #define REG_A5XX_CP_RB_BASE 0x00000800
311 #define REG_A5XX_CP_RB_BASE_HI 0x00000801
313 #define REG_A5XX_CP_RB_CNTL 0x00000802
315 #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
317 #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
319 #define REG_A5XX_CP_RB_RPTR 0x00000806
321 #define REG_A5XX_CP_RB_WPTR 0x00000807
323 #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
325 #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
327 #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
329 #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
331 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
333 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
335 #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
337 #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
339 #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
341 #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
343 #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
345 #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
347 #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
349 #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
351 #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
353 #define REG_A5XX_CP_MERCIU_SIZE 0x00000826
355 #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
357 #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
359 #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
361 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
363 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
365 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
367 #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
369 #define REG_A5XX_CP_CNTL 0x00000831
371 #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
373 #define REG_A5XX_CP_CHICKEN_DBG 0x00000833
375 #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
377 #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
379 #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
381 #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
383 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
385 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
387 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
389 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
391 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
393 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
395 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
397 #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
399 #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
401 #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
403 #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
405 #define REG_A5XX_CP_HW_FAULT 0x00000b1a
407 #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
409 #define REG_A5XX_CP_IB1_BASE 0x00000b1f
411 #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
413 #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
415 #define REG_A5XX_CP_IB2_BASE 0x00000b22
417 #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
419 #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
421 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0
) { return 0x00000b78 + 0x1*i0
; }
423 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0
) { return 0x00000b78 + 0x1*i0
; }
425 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0
) { return 0x00000880 + 0x1*i0
; }
427 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0
) { return 0x00000880 + 0x1*i0
; }
428 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
429 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
430 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val
)
432 return ((val
) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT
) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK
;
434 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
435 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
436 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val
)
438 return ((val
) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT
) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK
;
440 #define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
441 #define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
443 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
445 #define REG_A5XX_CP_AHB_FAULT 0x00000b1b
447 #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
449 #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
451 #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
453 #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
455 #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
457 #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
459 #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
461 #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
463 #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
465 #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
467 #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
469 #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
471 #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
473 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
475 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
477 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
479 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
481 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
483 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
485 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
487 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
489 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
491 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
493 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
495 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
497 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
499 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
501 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
503 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
505 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
507 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
509 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
511 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
513 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
515 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
517 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
519 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
521 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
523 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
525 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
527 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
529 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
531 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
533 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
535 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
537 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
539 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
541 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
543 #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
545 #define REG_A5XX_RBBM_INT_0_MASK 0x00000038
546 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
547 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
548 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
549 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
550 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
551 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
552 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
553 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
554 #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
555 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
556 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
557 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
558 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
559 #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
560 #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
561 #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
562 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
563 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
564 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
565 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
566 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
567 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
568 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
569 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
570 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
571 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
572 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
573 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
574 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
576 #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
578 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
580 #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
582 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
584 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
586 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
588 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
590 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
592 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
594 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
596 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
598 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
600 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
602 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
604 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
606 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
608 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
610 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
612 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
614 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
616 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
618 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
620 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
622 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
624 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
626 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
628 #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
630 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
632 #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
634 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
636 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
638 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
640 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
642 #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
644 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
646 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
648 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
650 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
652 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
654 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
656 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
658 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
660 #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
662 #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
664 #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
666 #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
668 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
670 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
672 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
674 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
676 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
678 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
680 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
682 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
684 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
686 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
688 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
690 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
692 #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
694 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
696 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
698 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
700 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
702 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
704 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
706 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
708 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
710 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
712 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
714 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
716 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
718 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
720 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
722 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
724 #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
726 #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
728 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
730 #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
732 #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
734 #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
736 #define REG_A5XX_RBBM_AHB_CMD 0x00000096
738 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
740 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
742 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
744 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
746 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
748 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
750 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
752 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
754 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
756 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
758 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
760 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
762 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
764 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
766 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
768 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
770 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
772 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
774 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
776 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
778 #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
780 #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
782 #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
784 #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
786 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
788 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
790 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
792 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
794 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
796 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
798 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
800 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
802 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
804 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
806 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
808 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
810 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
812 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
814 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
816 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
818 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
820 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
822 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
824 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
826 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
828 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
830 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
832 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
834 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
836 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
838 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
840 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
842 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
844 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
846 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
848 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
850 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
852 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
854 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
856 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
858 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
860 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
862 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
864 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
866 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
868 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
870 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
872 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
874 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
876 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
878 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
880 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
882 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
884 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
886 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
888 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
890 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
892 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
894 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
896 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
898 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
900 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
902 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
904 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
906 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
908 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
910 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
912 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
914 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
916 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
918 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
920 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
922 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
924 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
926 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
928 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
930 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
932 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
934 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
936 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
938 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
940 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
942 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
944 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
946 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
948 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
950 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
952 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
954 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
956 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
958 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
960 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
962 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
964 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
966 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
968 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
970 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
972 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
974 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
976 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
978 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
980 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
982 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
984 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
986 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
988 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
990 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
992 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
994 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
996 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
998 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
1000 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
1002 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
1004 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
1006 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
1008 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
1010 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
1012 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
1014 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
1016 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
1018 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
1020 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
1022 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
1024 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
1026 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
1028 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
1030 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
1032 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
1034 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
1036 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
1038 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
1040 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
1042 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
1044 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
1046 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
1048 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
1050 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
1052 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
1054 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
1056 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
1058 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
1060 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
1062 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
1064 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
1066 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
1068 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
1070 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
1072 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
1074 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
1076 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
1078 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
1080 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
1082 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
1084 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
1086 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
1088 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
1090 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
1092 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
1094 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
1096 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
1098 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
1100 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
1102 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
1104 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
1106 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
1108 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
1110 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
1112 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
1114 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
1116 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
1118 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
1120 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
1122 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
1124 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
1126 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
1128 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
1130 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
1132 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
1134 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
1136 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
1138 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
1140 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
1142 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
1144 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
1146 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
1148 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
1150 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
1152 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
1154 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
1156 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
1158 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
1160 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
1162 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
1164 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
1166 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
1168 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
1170 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
1172 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
1174 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
1176 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
1178 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
1180 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
1182 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
1184 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
1186 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
1188 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
1190 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
1192 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
1194 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
1196 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
1198 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
1200 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1202 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1204 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1206 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1208 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
1210 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
1212 #define REG_A5XX_RBBM_STATUS 0x000004f5
1213 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
1214 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
1215 #define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1216 #define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
1217 #define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
1218 #define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
1219 #define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
1220 #define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
1221 #define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
1222 #define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
1223 #define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
1224 #define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1225 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1226 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
1227 #define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
1228 #define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
1229 #define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
1230 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
1231 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
1232 #define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
1233 #define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
1234 #define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
1235 #define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
1236 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
1237 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
1238 #define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
1239 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
1240 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
1241 #define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
1242 #define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1243 #define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1244 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
1246 #define REG_A5XX_RBBM_STATUS3 0x00000530
1248 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
1250 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
1252 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
1254 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
1256 #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
1258 #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
1260 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
1262 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
1264 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
1266 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
1268 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
1270 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
1272 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1274 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1276 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1278 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1280 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
1282 #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
1284 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
1286 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
1288 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
1290 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
1292 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
1294 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
1296 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
1298 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
1300 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
1302 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
1304 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
1306 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
1308 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
1310 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
1312 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
1314 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
1316 #define REG_A5XX_RBBM_ISDB_CNT 0x00000533
1318 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
1320 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1322 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1324 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1326 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1328 #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1330 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
1332 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
1334 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
1336 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
1338 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1340 #define REG_A5XX_VSC_PIPE_DATA_LENGTH_0 0x00000c00
1342 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
1344 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
1346 #define REG_A5XX_VSC_BIN_SIZE 0x00000cdd
1347 #define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE 0x80000000
1348 #define A5XX_VSC_BIN_SIZE_X__MASK 0x00007fff
1349 #define A5XX_VSC_BIN_SIZE_X__SHIFT 0
1350 static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val
)
1352 return ((val
) << A5XX_VSC_BIN_SIZE_X__SHIFT
) & A5XX_VSC_BIN_SIZE_X__MASK
;
1354 #define A5XX_VSC_BIN_SIZE_Y__MASK 0x7fff0000
1355 #define A5XX_VSC_BIN_SIZE_Y__SHIFT 16
1356 static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val
)
1358 return ((val
) << A5XX_VSC_BIN_SIZE_Y__SHIFT
) & A5XX_VSC_BIN_SIZE_Y__MASK
;
1361 #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
1363 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
1365 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
1367 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
1369 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
1371 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
1373 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
1375 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
1377 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
1379 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
1381 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
1383 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
1385 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
1387 #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
1389 #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
1391 #define REG_A5XX_RB_MODE_CNTL 0x00000cc6
1393 #define REG_A5XX_RB_CCU_CNTL 0x00000cc7
1395 #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
1397 #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
1399 #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
1401 #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
1403 #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
1405 #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
1407 #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
1409 #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
1411 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
1413 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
1415 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
1417 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
1419 #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
1421 #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
1423 #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
1425 #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
1427 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
1429 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
1431 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
1433 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
1435 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
1437 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
1439 #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
1440 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
1442 #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
1444 #define REG_A5XX_PC_MODE_CNTL 0x00000d02
1446 #define REG_A5XX_UNKNOWN_0D08 0x00000d08
1448 #define REG_A5XX_UNKNOWN_0D09 0x00000d09
1450 #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
1452 #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
1454 #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
1456 #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
1458 #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
1460 #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
1462 #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
1464 #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
1466 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
1468 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
1470 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
1472 #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
1474 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
1476 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
1478 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
1480 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
1482 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
1484 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
1486 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
1488 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
1490 #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
1492 #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
1494 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
1496 #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
1498 #define REG_A5XX_VFD_MODE_CNTL 0x00000e42
1500 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
1502 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
1504 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
1506 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
1508 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
1510 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
1512 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
1514 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
1516 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
1518 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
1520 #define REG_A5XX_VPC_MODE_CNTL 0x00000e62
1522 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
1524 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
1526 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
1528 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
1530 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
1532 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
1534 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
1536 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
1538 #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
1540 #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
1542 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
1544 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
1546 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
1548 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
1550 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
1552 #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
1554 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
1556 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
1558 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
1560 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
1562 #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
1564 #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
1566 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
1568 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
1570 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
1572 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
1574 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
1576 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
1578 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
1580 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
1582 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
1584 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
1586 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
1588 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
1590 #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
1592 #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
1594 #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
1596 #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
1598 #define REG_A5XX_SP_MODE_CNTL 0x00000ec2
1600 #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
1602 #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
1604 #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
1606 #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
1608 #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
1610 #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
1612 #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
1614 #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
1616 #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
1618 #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
1620 #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
1622 #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
1624 #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
1626 #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
1628 #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
1630 #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
1632 #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
1634 #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
1636 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
1638 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
1640 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
1642 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
1644 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
1646 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
1648 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
1650 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
1652 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
1654 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
1656 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
1658 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
1660 #define REG_A5XX_VBIF_VERSION 0x00003000
1662 #define REG_A5XX_VBIF_CLKON 0x00003001
1664 #define REG_A5XX_VBIF_ABIT_SORT 0x00003028
1666 #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
1668 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
1670 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1672 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
1674 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
1676 #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
1678 #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
1680 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
1682 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
1684 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
1686 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
1688 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
1690 #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
1692 #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
1694 #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
1696 #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
1698 #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
1700 #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
1702 #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
1704 #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
1706 #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
1708 #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
1710 #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
1712 #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
1714 #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
1716 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
1718 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
1720 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
1722 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
1724 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
1726 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
1728 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
1730 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
1732 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
1734 #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
1736 #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
1738 #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
1740 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
1742 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
1744 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
1745 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
1747 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
1748 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
1750 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
1752 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
1754 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
1756 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
1758 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
1760 #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
1762 #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
1764 #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
1766 #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
1768 #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
1770 #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
1772 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
1774 #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
1776 #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
1778 #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
1780 #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
1782 #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
1784 #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
1786 #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
1788 #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
1790 #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
1792 #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
1794 #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
1796 #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
1798 #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
1800 #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
1802 #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
1804 #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
1806 #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
1808 #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
1810 #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
1812 #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
1814 #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
1816 #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
1818 #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
1820 #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
1822 #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
1824 #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
1826 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
1828 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
1830 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
1832 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
1834 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
1836 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
1838 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
1840 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
1842 #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
1844 #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
1846 #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
1848 #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
1850 #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
1852 #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
1854 #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
1856 #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
1858 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
1860 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
1862 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
1864 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
1866 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
1868 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
1870 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
1872 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
1874 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
1876 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
1878 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
1880 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
1882 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
1884 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
1886 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
1888 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
1890 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
1892 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
1894 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
1896 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
1898 #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
1900 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
1902 #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
1904 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
1906 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
1908 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
1910 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
1912 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
1914 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
1916 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
1918 #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
1920 #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
1922 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
1924 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
1926 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
1928 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
1930 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
1932 #define REG_A5XX_GDPM_CONFIG1 0x0000b80c
1934 #define REG_A5XX_GDPM_CONFIG2 0x0000b80d
1936 #define REG_A5XX_GDPM_INT_EN 0x0000b80f
1938 #define REG_A5XX_GDPM_INT_MASK 0x0000b811
1940 #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
1942 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
1944 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
1946 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
1948 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
1950 #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
1952 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
1954 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000
1956 #define REG_A5XX_UNKNOWN_E001 0x0000e001
1958 #define REG_A5XX_UNKNOWN_E004 0x0000e004
1960 #define REG_A5XX_GRAS_CNTL 0x0000e005
1961 #define A5XX_GRAS_CNTL_VARYING 0x00000001
1962 #define A5XX_GRAS_CNTL_UNK3 0x00000008
1963 #define A5XX_GRAS_CNTL_XCOORD 0x00000040
1964 #define A5XX_GRAS_CNTL_YCOORD 0x00000080
1965 #define A5XX_GRAS_CNTL_ZCOORD 0x00000100
1966 #define A5XX_GRAS_CNTL_WCOORD 0x00000200
1968 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
1969 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
1970 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
1971 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val
)
1973 return ((val
) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT
) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK
;
1975 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
1976 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
1977 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val
)
1979 return ((val
) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT
) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK
;
1982 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
1983 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
1984 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
1985 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val
)
1987 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT
) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK
;
1990 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
1991 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
1992 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
1993 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val
)
1995 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT
) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK
;
1998 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
1999 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2000 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2001 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val
)
2003 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT
) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK
;
2006 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
2007 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2008 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2009 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val
)
2011 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT
) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK
;
2014 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
2015 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2016 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2017 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val
)
2019 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT
) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK
;
2022 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
2023 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2024 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2025 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val
)
2027 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT
) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK
;
2030 #define REG_A5XX_GRAS_SU_CNTL 0x0000e090
2031 #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2032 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2033 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
2034 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val
)
2036 return ((((int32_t)(val
* 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT
) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2038 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2039 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2041 #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
2042 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2043 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2044 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val
)
2046 return ((((uint32_t)(val
* 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT
) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK
;
2048 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2049 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2050 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val
)
2052 return ((((uint32_t)(val
* 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT
) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK
;
2055 #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
2056 #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2057 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
2058 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val
)
2060 return ((((int32_t)(val
* 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT
) & A5XX_GRAS_SU_POINT_SIZE__MASK
;
2063 #define REG_A5XX_UNKNOWN_E093 0x0000e093
2065 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
2066 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2068 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
2069 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2070 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2071 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val
)
2073 return ((fui(val
)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT
) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK
;
2076 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
2077 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2078 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2079 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val
)
2081 return ((fui(val
)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
;
2084 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
2085 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2086 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2087 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val
)
2089 return ((fui(val
)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT
) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK
;
2092 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
2093 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2094 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2095 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val
)
2097 return ((val
) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT
) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
;
2100 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
2102 #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
2103 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
2105 #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
2107 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
2108 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2109 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2110 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
2112 return ((val
) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK
;
2115 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
2116 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2117 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2118 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
2120 return ((val
) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK
;
2122 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2124 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
2126 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
2127 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2128 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2129 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2130 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val
)
2132 return ((val
) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT
) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK
;
2134 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2135 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2136 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val
)
2138 return ((val
) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT
) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK
;
2141 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
2142 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2143 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
2144 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
2145 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val
)
2147 return ((val
) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT
) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK
;
2149 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
2150 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
2151 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val
)
2153 return ((val
) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT
) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK
;
2156 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
2157 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2158 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
2159 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
2160 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val
)
2162 return ((val
) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT
) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK
;
2164 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
2165 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
2166 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val
)
2168 return ((val
) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT
) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK
;
2171 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
2172 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2173 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
2174 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
2175 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val
)
2177 return ((val
) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT
) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK
;
2179 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
2180 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
2181 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val
)
2183 return ((val
) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT
) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK
;
2186 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
2187 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2188 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2189 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2190 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val
)
2192 return ((val
) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
;
2194 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2195 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2196 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val
)
2198 return ((val
) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
;
2201 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
2202 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2203 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2204 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2205 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val
)
2207 return ((val
) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
;
2209 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2210 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2211 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val
)
2213 return ((val
) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
;
2216 #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
2218 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
2220 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
2222 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
2224 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
2226 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
2228 #define REG_A5XX_RB_CNTL 0x0000e140
2229 #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
2230 #define A5XX_RB_CNTL_WIDTH__SHIFT 0
2231 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val
)
2233 assert(!(val
& 0x1f));
2234 return ((val
>> 5) << A5XX_RB_CNTL_WIDTH__SHIFT
) & A5XX_RB_CNTL_WIDTH__MASK
;
2236 #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
2237 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9
2238 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val
)
2240 assert(!(val
& 0x1f));
2241 return ((val
>> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT
) & A5XX_RB_CNTL_HEIGHT__MASK
;
2243 #define A5XX_RB_CNTL_BYPASS 0x00020000
2245 #define REG_A5XX_RB_RENDER_CNTL 0x0000e141
2246 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
2247 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
2248 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
2249 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
2250 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
2251 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val
)
2253 return ((val
) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT
) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK
;
2255 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
2256 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
2257 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val
)
2259 return ((val
) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT
) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK
;
2262 #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
2263 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2264 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2265 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
2267 return ((val
) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK
;
2270 #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
2271 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2272 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2273 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
2275 return ((val
) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK
;
2277 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2279 #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
2280 #define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
2281 #define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008
2282 #define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
2283 #define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
2284 #define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
2285 #define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
2287 #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
2288 #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
2290 #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
2291 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
2292 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
2293 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val
)
2295 return ((val
) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT
) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK
;
2297 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
2299 #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
2300 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
2301 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
2302 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val
)
2304 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK
;
2306 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
2307 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
2308 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val
)
2310 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK
;
2312 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
2313 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
2314 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val
)
2316 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK
;
2318 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
2319 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
2320 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val
)
2322 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK
;
2324 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
2325 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
2326 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val
)
2328 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK
;
2330 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
2331 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
2332 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val
)
2334 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK
;
2336 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
2337 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
2338 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val
)
2340 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK
;
2342 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
2343 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
2344 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val
)
2346 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK
;
2349 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0
) { return 0x0000e150 + 0x7*i0
; }
2351 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0
) { return 0x0000e150 + 0x7*i0
; }
2352 #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
2353 #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
2354 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
2355 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
2356 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val
)
2358 return ((val
) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
2361 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0
) { return 0x0000e151 + 0x7*i0
; }
2362 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
2363 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
2364 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val
)
2366 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
;
2368 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
2369 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
2370 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val
)
2372 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
;
2374 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
2375 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
2376 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val
)
2378 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
;
2380 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
2381 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
2382 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val
)
2384 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
;
2386 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
2387 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
2388 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val
)
2390 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
;
2392 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
2393 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
2394 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val
)
2396 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
;
2399 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0
) { return 0x0000e152 + 0x7*i0
; }
2400 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
2401 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
2402 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
2404 return ((val
) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
;
2406 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
2407 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
2408 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val
)
2410 return ((val
) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
;
2412 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
2413 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
2414 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
2416 return ((val
) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
;
2418 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
2420 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0
) { return 0x0000e153 + 0x7*i0
; }
2421 #define A5XX_RB_MRT_PITCH__MASK 0xffffffff
2422 #define A5XX_RB_MRT_PITCH__SHIFT 0
2423 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val
)
2425 assert(!(val
& 0x3f));
2426 return ((val
>> 6) << A5XX_RB_MRT_PITCH__SHIFT
) & A5XX_RB_MRT_PITCH__MASK
;
2429 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0
) { return 0x0000e154 + 0x7*i0
; }
2430 #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
2431 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
2432 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val
)
2434 assert(!(val
& 0x3f));
2435 return ((val
>> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT
) & A5XX_RB_MRT_ARRAY_PITCH__MASK
;
2438 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0
) { return 0x0000e155 + 0x7*i0
; }
2440 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0
) { return 0x0000e156 + 0x7*i0
; }
2442 #define REG_A5XX_RB_BLEND_RED 0x0000e1a0
2443 #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
2444 #define A5XX_RB_BLEND_RED_UINT__SHIFT 0
2445 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val
)
2447 return ((val
) << A5XX_RB_BLEND_RED_UINT__SHIFT
) & A5XX_RB_BLEND_RED_UINT__MASK
;
2449 #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
2450 #define A5XX_RB_BLEND_RED_SINT__SHIFT 8
2451 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val
)
2453 return ((val
) << A5XX_RB_BLEND_RED_SINT__SHIFT
) & A5XX_RB_BLEND_RED_SINT__MASK
;
2455 #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
2456 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
2457 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val
)
2459 return ((util_float_to_half(val
)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT
) & A5XX_RB_BLEND_RED_FLOAT__MASK
;
2462 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
2463 #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
2464 #define A5XX_RB_BLEND_RED_F32__SHIFT 0
2465 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val
)
2467 return ((fui(val
)) << A5XX_RB_BLEND_RED_F32__SHIFT
) & A5XX_RB_BLEND_RED_F32__MASK
;
2470 #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
2471 #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
2472 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
2473 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val
)
2475 return ((val
) << A5XX_RB_BLEND_GREEN_UINT__SHIFT
) & A5XX_RB_BLEND_GREEN_UINT__MASK
;
2477 #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
2478 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
2479 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val
)
2481 return ((val
) << A5XX_RB_BLEND_GREEN_SINT__SHIFT
) & A5XX_RB_BLEND_GREEN_SINT__MASK
;
2483 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
2484 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
2485 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val
)
2487 return ((util_float_to_half(val
)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT
) & A5XX_RB_BLEND_GREEN_FLOAT__MASK
;
2490 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
2491 #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
2492 #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
2493 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val
)
2495 return ((fui(val
)) << A5XX_RB_BLEND_GREEN_F32__SHIFT
) & A5XX_RB_BLEND_GREEN_F32__MASK
;
2498 #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
2499 #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
2500 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
2501 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val
)
2503 return ((val
) << A5XX_RB_BLEND_BLUE_UINT__SHIFT
) & A5XX_RB_BLEND_BLUE_UINT__MASK
;
2505 #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
2506 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
2507 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val
)
2509 return ((val
) << A5XX_RB_BLEND_BLUE_SINT__SHIFT
) & A5XX_RB_BLEND_BLUE_SINT__MASK
;
2511 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
2512 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
2513 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val
)
2515 return ((util_float_to_half(val
)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT
) & A5XX_RB_BLEND_BLUE_FLOAT__MASK
;
2518 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
2519 #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
2520 #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
2521 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val
)
2523 return ((fui(val
)) << A5XX_RB_BLEND_BLUE_F32__SHIFT
) & A5XX_RB_BLEND_BLUE_F32__MASK
;
2526 #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
2527 #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
2528 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
2529 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val
)
2531 return ((val
) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT
) & A5XX_RB_BLEND_ALPHA_UINT__MASK
;
2533 #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
2534 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
2535 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val
)
2537 return ((val
) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT
) & A5XX_RB_BLEND_ALPHA_SINT__MASK
;
2539 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
2540 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
2541 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val
)
2543 return ((util_float_to_half(val
)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT
) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK
;
2546 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
2547 #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
2548 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
2549 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val
)
2551 return ((fui(val
)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT
) & A5XX_RB_BLEND_ALPHA_F32__MASK
;
2554 #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
2555 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
2556 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
2557 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val
)
2559 return ((val
) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT
) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK
;
2561 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
2562 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
2563 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
2564 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val
)
2566 return ((val
) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT
) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK
;
2569 #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
2570 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
2571 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
2572 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val
)
2574 return ((val
) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT
) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK
;
2576 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
2577 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
2578 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
2579 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val
)
2581 return ((val
) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT
) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK
;
2584 #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
2585 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2587 #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
2588 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
2589 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
2590 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
2591 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
2592 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val
)
2594 return ((val
) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT
) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK
;
2596 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
2598 #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
2599 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2600 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2601 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val
)
2603 return ((val
) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT
) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
;
2606 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
2608 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
2610 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
2611 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
2612 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
2613 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val
)
2615 assert(!(val
& 0x3f));
2616 return ((val
>> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT
) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK
;
2619 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
2620 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
2621 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
2622 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val
)
2624 assert(!(val
& 0x3f));
2625 return ((val
>> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT
) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK
;
2628 #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
2629 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
2630 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
2631 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
2632 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
2633 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
2634 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val
)
2636 return ((val
) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT
) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK
;
2638 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
2639 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
2640 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val
)
2642 return ((val
) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT
) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK
;
2644 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
2645 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
2646 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val
)
2648 return ((val
) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK
;
2650 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
2651 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
2652 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val
)
2654 return ((val
) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK
;
2656 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
2657 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
2658 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val
)
2660 return ((val
) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
;
2662 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
2663 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
2664 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val
)
2666 return ((val
) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
;
2668 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
2669 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
2670 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val
)
2672 return ((val
) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
;
2674 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
2675 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
2676 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val
)
2678 return ((val
) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
;
2681 #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
2682 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
2684 #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
2686 #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
2688 #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
2689 #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
2690 #define A5XX_RB_STENCIL_PITCH__SHIFT 0
2691 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val
)
2693 assert(!(val
& 0x3f));
2694 return ((val
>> 6) << A5XX_RB_STENCIL_PITCH__SHIFT
) & A5XX_RB_STENCIL_PITCH__MASK
;
2697 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
2698 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
2699 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
2700 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val
)
2702 assert(!(val
& 0x3f));
2703 return ((val
>> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT
) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK
;
2706 #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
2707 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
2708 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
2709 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val
)
2711 return ((val
) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT
) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK
;
2713 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
2714 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
2715 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val
)
2717 return ((val
) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK
;
2719 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
2720 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
2721 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val
)
2723 return ((val
) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
;
2726 #define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7
2728 #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
2729 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2730 #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
2731 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
2732 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val
)
2734 return ((val
) << A5XX_RB_WINDOW_OFFSET_X__SHIFT
) & A5XX_RB_WINDOW_OFFSET_X__MASK
;
2736 #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
2737 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
2738 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val
)
2740 return ((val
) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT
) & A5XX_RB_WINDOW_OFFSET_Y__MASK
;
2743 #define REG_A5XX_RB_BLIT_CNTL 0x0000e210
2744 #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
2745 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
2746 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val
)
2748 return ((val
) << A5XX_RB_BLIT_CNTL_BUF__SHIFT
) & A5XX_RB_BLIT_CNTL_BUF__MASK
;
2751 #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
2752 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
2753 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
2754 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
2755 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val
)
2757 return ((val
) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT
) & A5XX_RB_RESOLVE_CNTL_1_X__MASK
;
2759 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
2760 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
2761 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val
)
2763 return ((val
) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT
) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK
;
2766 #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
2767 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
2768 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
2769 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
2770 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val
)
2772 return ((val
) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT
) & A5XX_RB_RESOLVE_CNTL_2_X__MASK
;
2774 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
2775 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
2776 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val
)
2778 return ((val
) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT
) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK
;
2781 #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
2783 #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
2785 #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
2787 #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
2788 #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
2789 #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
2790 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val
)
2792 assert(!(val
& 0x3f));
2793 return ((val
>> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT
) & A5XX_RB_BLIT_DST_PITCH__MASK
;
2796 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
2797 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
2798 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
2799 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val
)
2801 assert(!(val
& 0x3f));
2802 return ((val
>> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT
) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK
;
2805 #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
2807 #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
2809 #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
2811 #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
2813 #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
2814 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
2815 #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
2816 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
2817 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val
)
2819 return ((val
) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT
) & A5XX_RB_CLEAR_CNTL_MASK__MASK
;
2822 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
2824 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
2826 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
2828 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0
) { return 0x0000e243 + 0x4*i0
; }
2830 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0
) { return 0x0000e243 + 0x4*i0
; }
2832 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0
) { return 0x0000e244 + 0x4*i0
; }
2834 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0
) { return 0x0000e245 + 0x4*i0
; }
2835 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
2836 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
2837 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val
)
2839 assert(!(val
& 0x3f));
2840 return ((val
>> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT
) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK
;
2843 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0
) { return 0x0000e246 + 0x4*i0
; }
2844 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
2845 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
2846 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val
)
2848 assert(!(val
& 0x3f));
2849 return ((val
>> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT
) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK
;
2852 #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
2854 #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
2856 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
2857 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
2858 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
2859 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val
)
2861 assert(!(val
& 0x3f));
2862 return ((val
>> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT
) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK
;
2865 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
2866 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
2867 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
2868 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val
)
2870 assert(!(val
& 0x3f));
2871 return ((val
>> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT
) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK
;
2874 #define REG_A5XX_VPC_CNTL_0 0x0000e280
2875 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
2876 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
2877 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val
)
2879 return ((val
) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT
) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK
;
2881 #define A5XX_VPC_CNTL_0_VARYING 0x00000800
2883 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0
) { return 0x0000e282 + 0x1*i0
; }
2885 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0
) { return 0x0000e282 + 0x1*i0
; }
2887 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0
) { return 0x0000e28a + 0x1*i0
; }
2889 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0
) { return 0x0000e28a + 0x1*i0
; }
2891 #define REG_A5XX_UNKNOWN_E292 0x0000e292
2893 #define REG_A5XX_UNKNOWN_E293 0x0000e293
2895 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0
) { return 0x0000e294 + 0x1*i0
; }
2897 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0
) { return 0x0000e294 + 0x1*i0
; }
2899 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
2901 #define REG_A5XX_UNKNOWN_E29A 0x0000e29a
2903 #define REG_A5XX_VPC_PACK 0x0000e29d
2904 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
2905 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
2906 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val
)
2908 return ((val
) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT
) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK
;
2911 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
2913 #define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
2914 #define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
2915 #define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
2916 #define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
2917 #define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
2918 #define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
2920 #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
2921 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
2923 #define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
2924 #define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
2926 #define REG_A5XX_VPC_SO_PROG 0x0000e2a4
2927 #define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
2928 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
2929 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val
)
2931 return ((val
) << A5XX_VPC_SO_PROG_A_BUF__SHIFT
) & A5XX_VPC_SO_PROG_A_BUF__MASK
;
2933 #define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
2934 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
2935 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val
)
2937 assert(!(val
& 0x3));
2938 return ((val
>> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT
) & A5XX_VPC_SO_PROG_A_OFF__MASK
;
2940 #define A5XX_VPC_SO_PROG_A_EN 0x00000800
2941 #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
2942 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
2943 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val
)
2945 return ((val
) << A5XX_VPC_SO_PROG_B_BUF__SHIFT
) & A5XX_VPC_SO_PROG_B_BUF__MASK
;
2947 #define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
2948 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
2949 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val
)
2951 assert(!(val
& 0x3));
2952 return ((val
>> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT
) & A5XX_VPC_SO_PROG_B_OFF__MASK
;
2954 #define A5XX_VPC_SO_PROG_B_EN 0x00800000
2956 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0
) { return 0x0000e2a7 + 0x7*i0
; }
2958 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0
) { return 0x0000e2a7 + 0x7*i0
; }
2960 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0
) { return 0x0000e2a8 + 0x7*i0
; }
2962 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0
) { return 0x0000e2a9 + 0x7*i0
; }
2964 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0
) { return 0x0000e2aa + 0x7*i0
; }
2966 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0
) { return 0x0000e2ab + 0x7*i0
; }
2968 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0
) { return 0x0000e2ac + 0x7*i0
; }
2970 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0
) { return 0x0000e2ad + 0x7*i0
; }
2972 #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
2973 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
2974 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
2975 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val
)
2977 return ((val
) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT
) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK
;
2980 #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
2981 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
2983 #define REG_A5XX_PC_RASTER_CNTL 0x0000e388
2985 #define REG_A5XX_UNKNOWN_E389 0x0000e389
2987 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
2989 #define REG_A5XX_UNKNOWN_E38D 0x0000e38d
2991 #define REG_A5XX_PC_GS_PARAM 0x0000e38e
2993 #define REG_A5XX_PC_HS_PARAM 0x0000e38f
2995 #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
2997 #define REG_A5XX_VFD_CONTROL_0 0x0000e400
2998 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
2999 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
3000 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val
)
3002 return ((val
) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT
) & A5XX_VFD_CONTROL_0_VTXCNT__MASK
;
3005 #define REG_A5XX_VFD_CONTROL_1 0x0000e401
3006 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
3007 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
3008 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val
)
3010 return ((val
) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT
) & A5XX_VFD_CONTROL_1_REGID4INST__MASK
;
3012 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
3013 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
3014 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val
)
3016 return ((val
) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT
) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK
;
3019 #define REG_A5XX_VFD_CONTROL_2 0x0000e402
3021 #define REG_A5XX_VFD_CONTROL_3 0x0000e403
3023 #define REG_A5XX_VFD_CONTROL_4 0x0000e404
3025 #define REG_A5XX_VFD_CONTROL_5 0x0000e405
3027 #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
3029 #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
3031 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0
) { return 0x0000e40a + 0x4*i0
; }
3033 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0
) { return 0x0000e40a + 0x4*i0
; }
3035 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0
) { return 0x0000e40b + 0x4*i0
; }
3037 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0
) { return 0x0000e40c + 0x4*i0
; }
3039 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0
) { return 0x0000e40d + 0x4*i0
; }
3041 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0
) { return 0x0000e48a + 0x2*i0
; }
3043 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0
) { return 0x0000e48a + 0x2*i0
; }
3044 #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
3045 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
3046 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val
)
3048 return ((val
) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT
) & A5XX_VFD_DECODE_INSTR_IDX__MASK
;
3050 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000
3051 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
3052 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val
)
3054 return ((val
) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT
) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK
;
3056 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0xc0000000
3057 #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 30
3058 static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val
)
3060 return ((val
) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT
) & A5XX_VFD_DECODE_INSTR_SWAP__MASK
;
3063 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0
) { return 0x0000e48b + 0x2*i0
; }
3065 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0
) { return 0x0000e4ca + 0x1*i0
; }
3067 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0
) { return 0x0000e4ca + 0x1*i0
; }
3068 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
3069 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
3070 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val
)
3072 return ((val
) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT
) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK
;
3074 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
3075 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
3076 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val
)
3078 return ((val
) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT
) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK
;
3081 #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
3083 #define REG_A5XX_SP_SP_CNTL 0x0000e580
3085 #define REG_A5XX_SP_VS_CONTROL_REG 0x0000e584
3086 #define A5XX_SP_VS_CONTROL_REG_ENABLED 0x00000001
3087 #define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3088 #define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3089 static inline uint32_t A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3091 return ((val
) << A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3093 #define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3094 #define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3095 static inline uint32_t A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3097 return ((val
) << A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3100 #define REG_A5XX_SP_FS_CONTROL_REG 0x0000e585
3101 #define A5XX_SP_FS_CONTROL_REG_ENABLED 0x00000001
3102 #define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3103 #define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3104 static inline uint32_t A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3106 return ((val
) << A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3108 #define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3109 #define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3110 static inline uint32_t A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3112 return ((val
) << A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3115 #define REG_A5XX_SP_HS_CONTROL_REG 0x0000e586
3116 #define A5XX_SP_HS_CONTROL_REG_ENABLED 0x00000001
3117 #define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3118 #define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3119 static inline uint32_t A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3121 return ((val
) << A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3123 #define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3124 #define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3125 static inline uint32_t A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3127 return ((val
) << A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3130 #define REG_A5XX_SP_DS_CONTROL_REG 0x0000e587
3131 #define A5XX_SP_DS_CONTROL_REG_ENABLED 0x00000001
3132 #define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3133 #define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3134 static inline uint32_t A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3136 return ((val
) << A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3138 #define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3139 #define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3140 static inline uint32_t A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3142 return ((val
) << A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3145 #define REG_A5XX_SP_GS_CONTROL_REG 0x0000e588
3146 #define A5XX_SP_GS_CONTROL_REG_ENABLED 0x00000001
3147 #define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3148 #define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3149 static inline uint32_t A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3151 return ((val
) << A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3153 #define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3154 #define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3155 static inline uint32_t A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3157 return ((val
) << A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3160 #define REG_A5XX_SP_CS_CONFIG 0x0000e589
3162 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
3164 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
3166 #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
3167 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3168 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3169 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
3171 return ((val
) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
3173 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3174 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3175 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
3177 return ((val
) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
3179 #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
3180 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
3181 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
3182 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
3183 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val
)
3185 return ((val
) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT
) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK
;
3188 #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
3189 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
3190 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
3191 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val
)
3193 return ((val
) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT
) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK
;
3196 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0
) { return 0x0000e593 + 0x1*i0
; }
3198 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0
) { return 0x0000e593 + 0x1*i0
; }
3199 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
3200 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
3201 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val
)
3203 return ((val
) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT
) & A5XX_SP_VS_OUT_REG_A_REGID__MASK
;
3205 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
3206 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
3207 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val
)
3209 return ((val
) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK
;
3211 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
3212 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
3213 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val
)
3215 return ((val
) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT
) & A5XX_SP_VS_OUT_REG_B_REGID__MASK
;
3217 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
3218 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
3219 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val
)
3221 return ((val
) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK
;
3224 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0
) { return 0x0000e5a3 + 0x1*i0
; }
3226 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0
) { return 0x0000e5a3 + 0x1*i0
; }
3227 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
3228 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
3229 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val
)
3231 return ((val
) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
;
3233 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
3234 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
3235 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val
)
3237 return ((val
) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
;
3239 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
3240 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
3241 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val
)
3243 return ((val
) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
;
3245 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
3246 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
3247 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val
)
3249 return ((val
) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
;
3252 #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
3254 #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
3256 #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
3258 #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
3259 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3260 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3261 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
3263 return ((val
) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
3265 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3266 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3267 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
3269 return ((val
) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
3271 #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
3272 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
3273 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
3274 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
3275 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val
)
3277 return ((val
) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT
) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK
;
3280 #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
3282 #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
3284 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
3286 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
3288 #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
3289 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
3290 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
3291 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val
)
3293 return ((val
) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT
) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK
;
3295 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
3296 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
3297 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val
)
3299 return ((val
) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT
) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK
;
3301 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
3302 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
3303 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val
)
3305 return ((val
) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT
) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK
;
3308 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0
) { return 0x0000e5cb + 0x1*i0
; }
3310 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0
) { return 0x0000e5cb + 0x1*i0
; }
3311 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
3312 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
3313 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val
)
3315 return ((val
) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT
) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK
;
3317 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
3319 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0
) { return 0x0000e5d3 + 0x1*i0
; }
3321 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0
) { return 0x0000e5d3 + 0x1*i0
; }
3322 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
3323 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
3324 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val
)
3326 return ((val
) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT
) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK
;
3329 #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
3331 #define REG_A5XX_SP_CS_CNTL_0 0x0000e5f0
3333 #define REG_A5XX_UNKNOWN_E600 0x0000e600
3335 #define REG_A5XX_UNKNOWN_E640 0x0000e640
3337 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
3338 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3339 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
3340 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
3342 return ((val
) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK
;
3345 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
3346 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3347 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
3348 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
3350 return ((val
) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK
;
3352 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3354 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
3356 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
3358 #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
3360 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
3362 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
3364 #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
3366 #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
3368 #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
3370 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
3372 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
3374 #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
3376 #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
3378 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
3380 #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
3382 #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
3383 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
3384 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
3385 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val
)
3387 return ((val
) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT
) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK
;
3390 #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
3391 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
3392 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
3393 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val
)
3395 return ((val
) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT
) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK
;
3398 #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
3399 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
3400 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
3401 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val
)
3403 return ((val
) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT
) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK
;
3406 #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
3407 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
3408 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
3409 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val
)
3411 return ((val
) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT
) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK
;
3413 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
3414 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
3415 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val
)
3417 return ((val
) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT
) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK
;
3420 #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
3422 #define REG_A5XX_HLSQ_VS_CONTROL_REG 0x0000e78b
3423 #define A5XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00000001
3424 #define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3425 #define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3426 static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3428 return ((val
) << A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3430 #define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3431 #define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3432 static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3434 return ((val
) << A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3437 #define REG_A5XX_HLSQ_FS_CONTROL_REG 0x0000e78c
3438 #define A5XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00000001
3439 #define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3440 #define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3441 static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3443 return ((val
) << A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3445 #define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3446 #define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3447 static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3449 return ((val
) << A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3452 #define REG_A5XX_HLSQ_HS_CONTROL_REG 0x0000e78d
3453 #define A5XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00000001
3454 #define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3455 #define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3456 static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3458 return ((val
) << A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3460 #define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3461 #define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3462 static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3464 return ((val
) << A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3467 #define REG_A5XX_HLSQ_DS_CONTROL_REG 0x0000e78e
3468 #define A5XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00000001
3469 #define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3470 #define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3471 static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3473 return ((val
) << A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3475 #define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3476 #define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3477 static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3479 return ((val
) << A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3482 #define REG_A5XX_HLSQ_GS_CONTROL_REG 0x0000e78f
3483 #define A5XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00000001
3484 #define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
3485 #define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
3486 static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val
)
3488 return ((val
) << A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK
;
3490 #define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
3491 #define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
3492 static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val
)
3494 return ((val
) << A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK
;
3497 #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
3499 #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
3500 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
3501 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
3502 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val
)
3504 return ((val
) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK
;
3507 #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
3508 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
3509 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
3510 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val
)
3512 return ((val
) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK
;
3515 #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
3516 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
3517 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
3518 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val
)
3520 return ((val
) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK
;
3523 #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
3524 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
3525 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
3526 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val
)
3528 return ((val
) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK
;
3531 #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
3532 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
3533 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
3534 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val
)
3536 return ((val
) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK
;
3539 #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
3540 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
3541 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
3542 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val
)
3544 return ((val
) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK
;
3547 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
3549 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
3551 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
3553 #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
3555 #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
3557 #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
3559 #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
3561 #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
3563 #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
3565 #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
3567 #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
3569 #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
3571 #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
3573 #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
3575 #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
3577 #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
3579 #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
3581 #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
3583 #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
3585 #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
3587 #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
3589 #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
3591 #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
3593 #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
3595 #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
3597 #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
3599 #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
3601 #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
3603 #define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3 0x0000e7dc
3605 #define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_4 0x0000e7dd
3607 #define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
3609 #define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
3611 #define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
3613 #define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
3615 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107
3616 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
3617 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
3618 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
3620 return ((val
) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT
) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK
;
3622 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
3623 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
3624 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
3626 return ((val
) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT
) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK
;
3629 #define REG_A5XX_RB_2D_SRC_LO 0x00002108
3631 #define REG_A5XX_RB_2D_SRC_HI 0x00002109
3633 #define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
3634 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
3635 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
3636 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val
)
3638 assert(!(val
& 0x3f));
3639 return ((val
>> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT
) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK
;
3641 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
3642 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
3643 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val
)
3645 assert(!(val
& 0x3f));
3646 return ((val
>> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT
) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK
;
3649 #define REG_A5XX_RB_2D_DST_INFO 0x00002110
3650 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3651 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3652 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
3654 return ((val
) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT
) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK
;
3656 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3657 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3658 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
3660 return ((val
) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT
) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK
;
3663 #define REG_A5XX_RB_2D_DST_LO 0x00002111
3665 #define REG_A5XX_RB_2D_DST_HI 0x00002112
3667 #define REG_A5XX_RB_2D_DST_SIZE 0x00002113
3668 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
3669 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
3670 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val
)
3672 assert(!(val
& 0x3f));
3673 return ((val
>> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT
) & A5XX_RB_2D_DST_SIZE_PITCH__MASK
;
3675 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
3676 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
3677 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val
)
3679 assert(!(val
& 0x3f));
3680 return ((val
>> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT
) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK
;
3683 #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
3685 #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
3687 #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
3689 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
3691 #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
3692 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
3693 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
3694 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
3696 return ((val
) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT
) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK
;
3698 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
3699 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
3700 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
3702 return ((val
) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT
) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK
;
3705 #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
3706 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3707 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3708 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
3710 return ((val
) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT
) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK
;
3712 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3713 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3714 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
3716 return ((val
) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT
) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK
;
3719 #define REG_A5XX_UNKNOWN_2100 0x00002100
3721 #define REG_A5XX_UNKNOWN_2180 0x00002180
3723 #define REG_A5XX_UNKNOWN_2184 0x00002184
3725 #define REG_A5XX_TEX_SAMP_0 0x00000000
3726 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
3727 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
3728 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
3729 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val
)
3731 return ((val
) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT
) & A5XX_TEX_SAMP_0_XY_MAG__MASK
;
3733 #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
3734 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
3735 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val
)
3737 return ((val
) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT
) & A5XX_TEX_SAMP_0_XY_MIN__MASK
;
3739 #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
3740 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
3741 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val
)
3743 return ((val
) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT
) & A5XX_TEX_SAMP_0_WRAP_S__MASK
;
3745 #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
3746 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
3747 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val
)
3749 return ((val
) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT
) & A5XX_TEX_SAMP_0_WRAP_T__MASK
;
3751 #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
3752 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
3753 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val
)
3755 return ((val
) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT
) & A5XX_TEX_SAMP_0_WRAP_R__MASK
;
3757 #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
3758 #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
3759 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val
)
3761 return ((val
) << A5XX_TEX_SAMP_0_ANISO__SHIFT
) & A5XX_TEX_SAMP_0_ANISO__MASK
;
3763 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
3764 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
3765 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val
)
3767 return ((((int32_t)(val
* 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT
) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK
;
3770 #define REG_A5XX_TEX_SAMP_1 0x00000001
3771 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
3772 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
3773 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val
)
3775 return ((val
) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT
) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK
;
3777 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
3778 #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
3779 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
3780 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
3781 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
3782 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val
)
3784 return ((((uint32_t)(val
* 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT
) & A5XX_TEX_SAMP_1_MAX_LOD__MASK
;
3786 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
3787 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
3788 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val
)
3790 return ((((uint32_t)(val
* 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT
) & A5XX_TEX_SAMP_1_MIN_LOD__MASK
;
3793 #define REG_A5XX_TEX_SAMP_2 0x00000002
3794 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
3795 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
3796 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val
)
3798 return ((val
) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT
) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK
;
3801 #define REG_A5XX_TEX_SAMP_3 0x00000003
3803 #define REG_A5XX_TEX_CONST_0 0x00000000
3804 #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
3805 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
3806 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val
)
3808 return ((val
) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT
) & A5XX_TEX_CONST_0_TILE_MODE__MASK
;
3810 #define A5XX_TEX_CONST_0_SRGB 0x00000004
3811 #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
3812 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
3813 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val
)
3815 return ((val
) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT
) & A5XX_TEX_CONST_0_SWIZ_X__MASK
;
3817 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
3818 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
3819 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val
)
3821 return ((val
) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT
) & A5XX_TEX_CONST_0_SWIZ_Y__MASK
;
3823 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
3824 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
3825 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val
)
3827 return ((val
) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT
) & A5XX_TEX_CONST_0_SWIZ_Z__MASK
;
3829 #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
3830 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
3831 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val
)
3833 return ((val
) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT
) & A5XX_TEX_CONST_0_SWIZ_W__MASK
;
3835 #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
3836 #define A5XX_TEX_CONST_0_FMT__SHIFT 22
3837 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val
)
3839 return ((val
) << A5XX_TEX_CONST_0_FMT__SHIFT
) & A5XX_TEX_CONST_0_FMT__MASK
;
3841 #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
3842 #define A5XX_TEX_CONST_0_SWAP__SHIFT 30
3843 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val
)
3845 return ((val
) << A5XX_TEX_CONST_0_SWAP__SHIFT
) & A5XX_TEX_CONST_0_SWAP__MASK
;
3848 #define REG_A5XX_TEX_CONST_1 0x00000001
3849 #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
3850 #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
3851 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val
)
3853 return ((val
) << A5XX_TEX_CONST_1_WIDTH__SHIFT
) & A5XX_TEX_CONST_1_WIDTH__MASK
;
3855 #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
3856 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
3857 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val
)
3859 return ((val
) << A5XX_TEX_CONST_1_HEIGHT__SHIFT
) & A5XX_TEX_CONST_1_HEIGHT__MASK
;
3862 #define REG_A5XX_TEX_CONST_2 0x00000002
3863 #define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
3864 #define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
3865 static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val
)
3867 return ((val
) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT
) & A5XX_TEX_CONST_2_FETCHSIZE__MASK
;
3869 #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
3870 #define A5XX_TEX_CONST_2_PITCH__SHIFT 7
3871 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val
)
3873 return ((val
) << A5XX_TEX_CONST_2_PITCH__SHIFT
) & A5XX_TEX_CONST_2_PITCH__MASK
;
3875 #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
3876 #define A5XX_TEX_CONST_2_TYPE__SHIFT 29
3877 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val
)
3879 return ((val
) << A5XX_TEX_CONST_2_TYPE__SHIFT
) & A5XX_TEX_CONST_2_TYPE__MASK
;
3882 #define REG_A5XX_TEX_CONST_3 0x00000003
3883 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
3884 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
3885 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val
)
3887 assert(!(val
& 0xfff));
3888 return ((val
>> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT
) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK
;
3890 #define A5XX_TEX_CONST_3_FLAG 0x10000000
3892 #define REG_A5XX_TEX_CONST_4 0x00000004
3893 #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
3894 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
3895 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val
)
3897 assert(!(val
& 0x1f));
3898 return ((val
>> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT
) & A5XX_TEX_CONST_4_BASE_LO__MASK
;
3901 #define REG_A5XX_TEX_CONST_5 0x00000005
3902 #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
3903 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
3904 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val
)
3906 return ((val
) << A5XX_TEX_CONST_5_BASE_HI__SHIFT
) & A5XX_TEX_CONST_5_BASE_HI__MASK
;
3908 #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
3909 #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
3910 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val
)
3912 return ((val
) << A5XX_TEX_CONST_5_DEPTH__SHIFT
) & A5XX_TEX_CONST_5_DEPTH__MASK
;
3915 #define REG_A5XX_TEX_CONST_6 0x00000006
3917 #define REG_A5XX_TEX_CONST_7 0x00000007
3919 #define REG_A5XX_TEX_CONST_8 0x00000008
3921 #define REG_A5XX_TEX_CONST_9 0x00000009
3923 #define REG_A5XX_TEX_CONST_10 0x0000000a
3925 #define REG_A5XX_TEX_CONST_11 0x0000000b
3928 #endif /* A5XX_XML */