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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a5xx / a5xx.xml.h
1 #ifndef A5XX_XML
2 #define A5XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 33379 bytes, from 2017-11-14 21:00:47)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143420 bytes, from 2017-11-16 20:29:34)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
20
21 Copyright (C) 2013-2017 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46
47 enum a5xx_color_fmt {
48 RB5_A8_UNORM = 2,
49 RB5_R8_UNORM = 3,
50 RB5_R8_SNORM = 4,
51 RB5_R8_UINT = 5,
52 RB5_R8_SINT = 6,
53 RB5_R4G4B4A4_UNORM = 8,
54 RB5_R5G5B5A1_UNORM = 10,
55 RB5_R5G6B5_UNORM = 14,
56 RB5_R8G8_UNORM = 15,
57 RB5_R8G8_SNORM = 16,
58 RB5_R8G8_UINT = 17,
59 RB5_R8G8_SINT = 18,
60 RB5_R16_UNORM = 21,
61 RB5_R16_SNORM = 22,
62 RB5_R16_FLOAT = 23,
63 RB5_R16_UINT = 24,
64 RB5_R16_SINT = 25,
65 RB5_R8G8B8A8_UNORM = 48,
66 RB5_R8G8B8_UNORM = 49,
67 RB5_R8G8B8A8_SNORM = 50,
68 RB5_R8G8B8A8_UINT = 51,
69 RB5_R8G8B8A8_SINT = 52,
70 RB5_R10G10B10A2_UNORM = 55,
71 RB5_R10G10B10A2_UINT = 58,
72 RB5_R11G11B10_FLOAT = 66,
73 RB5_R16G16_UNORM = 67,
74 RB5_R16G16_SNORM = 68,
75 RB5_R16G16_FLOAT = 69,
76 RB5_R16G16_UINT = 70,
77 RB5_R16G16_SINT = 71,
78 RB5_R32_FLOAT = 74,
79 RB5_R32_UINT = 75,
80 RB5_R32_SINT = 76,
81 RB5_R16G16B16A16_UNORM = 96,
82 RB5_R16G16B16A16_SNORM = 97,
83 RB5_R16G16B16A16_FLOAT = 98,
84 RB5_R16G16B16A16_UINT = 99,
85 RB5_R16G16B16A16_SINT = 100,
86 RB5_R32G32_FLOAT = 103,
87 RB5_R32G32_UINT = 104,
88 RB5_R32G32_SINT = 105,
89 RB5_R32G32B32A32_FLOAT = 130,
90 RB5_R32G32B32A32_UINT = 131,
91 RB5_R32G32B32A32_SINT = 132,
92 };
93
94 enum a5xx_tile_mode {
95 TILE5_LINEAR = 0,
96 TILE5_2 = 2,
97 TILE5_3 = 3,
98 };
99
100 enum a5xx_vtx_fmt {
101 VFMT5_8_UNORM = 3,
102 VFMT5_8_SNORM = 4,
103 VFMT5_8_UINT = 5,
104 VFMT5_8_SINT = 6,
105 VFMT5_8_8_UNORM = 15,
106 VFMT5_8_8_SNORM = 16,
107 VFMT5_8_8_UINT = 17,
108 VFMT5_8_8_SINT = 18,
109 VFMT5_16_UNORM = 21,
110 VFMT5_16_SNORM = 22,
111 VFMT5_16_FLOAT = 23,
112 VFMT5_16_UINT = 24,
113 VFMT5_16_SINT = 25,
114 VFMT5_8_8_8_UNORM = 33,
115 VFMT5_8_8_8_SNORM = 34,
116 VFMT5_8_8_8_UINT = 35,
117 VFMT5_8_8_8_SINT = 36,
118 VFMT5_8_8_8_8_UNORM = 48,
119 VFMT5_8_8_8_8_SNORM = 50,
120 VFMT5_8_8_8_8_UINT = 51,
121 VFMT5_8_8_8_8_SINT = 52,
122 VFMT5_10_10_10_2_UNORM = 54,
123 VFMT5_10_10_10_2_SNORM = 57,
124 VFMT5_10_10_10_2_UINT = 58,
125 VFMT5_10_10_10_2_SINT = 59,
126 VFMT5_11_11_10_FLOAT = 66,
127 VFMT5_16_16_UNORM = 67,
128 VFMT5_16_16_SNORM = 68,
129 VFMT5_16_16_FLOAT = 69,
130 VFMT5_16_16_UINT = 70,
131 VFMT5_16_16_SINT = 71,
132 VFMT5_32_UNORM = 72,
133 VFMT5_32_SNORM = 73,
134 VFMT5_32_FLOAT = 74,
135 VFMT5_32_UINT = 75,
136 VFMT5_32_SINT = 76,
137 VFMT5_32_FIXED = 77,
138 VFMT5_16_16_16_UNORM = 88,
139 VFMT5_16_16_16_SNORM = 89,
140 VFMT5_16_16_16_FLOAT = 90,
141 VFMT5_16_16_16_UINT = 91,
142 VFMT5_16_16_16_SINT = 92,
143 VFMT5_16_16_16_16_UNORM = 96,
144 VFMT5_16_16_16_16_SNORM = 97,
145 VFMT5_16_16_16_16_FLOAT = 98,
146 VFMT5_16_16_16_16_UINT = 99,
147 VFMT5_16_16_16_16_SINT = 100,
148 VFMT5_32_32_UNORM = 101,
149 VFMT5_32_32_SNORM = 102,
150 VFMT5_32_32_FLOAT = 103,
151 VFMT5_32_32_UINT = 104,
152 VFMT5_32_32_SINT = 105,
153 VFMT5_32_32_FIXED = 106,
154 VFMT5_32_32_32_UNORM = 112,
155 VFMT5_32_32_32_SNORM = 113,
156 VFMT5_32_32_32_UINT = 114,
157 VFMT5_32_32_32_SINT = 115,
158 VFMT5_32_32_32_FLOAT = 116,
159 VFMT5_32_32_32_FIXED = 117,
160 VFMT5_32_32_32_32_UNORM = 128,
161 VFMT5_32_32_32_32_SNORM = 129,
162 VFMT5_32_32_32_32_FLOAT = 130,
163 VFMT5_32_32_32_32_UINT = 131,
164 VFMT5_32_32_32_32_SINT = 132,
165 VFMT5_32_32_32_32_FIXED = 133,
166 };
167
168 enum a5xx_tex_fmt {
169 TFMT5_A8_UNORM = 2,
170 TFMT5_8_UNORM = 3,
171 TFMT5_8_SNORM = 4,
172 TFMT5_8_UINT = 5,
173 TFMT5_8_SINT = 6,
174 TFMT5_4_4_4_4_UNORM = 8,
175 TFMT5_5_5_5_1_UNORM = 10,
176 TFMT5_5_6_5_UNORM = 14,
177 TFMT5_8_8_UNORM = 15,
178 TFMT5_8_8_SNORM = 16,
179 TFMT5_8_8_UINT = 17,
180 TFMT5_8_8_SINT = 18,
181 TFMT5_L8_A8_UNORM = 19,
182 TFMT5_16_UNORM = 21,
183 TFMT5_16_SNORM = 22,
184 TFMT5_16_FLOAT = 23,
185 TFMT5_16_UINT = 24,
186 TFMT5_16_SINT = 25,
187 TFMT5_8_8_8_8_UNORM = 48,
188 TFMT5_8_8_8_UNORM = 49,
189 TFMT5_8_8_8_8_SNORM = 50,
190 TFMT5_8_8_8_8_UINT = 51,
191 TFMT5_8_8_8_8_SINT = 52,
192 TFMT5_9_9_9_E5_FLOAT = 53,
193 TFMT5_10_10_10_2_UNORM = 54,
194 TFMT5_10_10_10_2_UINT = 58,
195 TFMT5_11_11_10_FLOAT = 66,
196 TFMT5_16_16_UNORM = 67,
197 TFMT5_16_16_SNORM = 68,
198 TFMT5_16_16_FLOAT = 69,
199 TFMT5_16_16_UINT = 70,
200 TFMT5_16_16_SINT = 71,
201 TFMT5_32_FLOAT = 74,
202 TFMT5_32_UINT = 75,
203 TFMT5_32_SINT = 76,
204 TFMT5_16_16_16_16_UNORM = 96,
205 TFMT5_16_16_16_16_SNORM = 97,
206 TFMT5_16_16_16_16_FLOAT = 98,
207 TFMT5_16_16_16_16_UINT = 99,
208 TFMT5_16_16_16_16_SINT = 100,
209 TFMT5_32_32_FLOAT = 103,
210 TFMT5_32_32_UINT = 104,
211 TFMT5_32_32_SINT = 105,
212 TFMT5_32_32_32_UINT = 114,
213 TFMT5_32_32_32_SINT = 115,
214 TFMT5_32_32_32_FLOAT = 116,
215 TFMT5_32_32_32_32_FLOAT = 130,
216 TFMT5_32_32_32_32_UINT = 131,
217 TFMT5_32_32_32_32_SINT = 132,
218 TFMT5_X8Z24_UNORM = 160,
219 TFMT5_ETC2_RG11_UNORM = 171,
220 TFMT5_ETC2_RG11_SNORM = 172,
221 TFMT5_ETC2_R11_UNORM = 173,
222 TFMT5_ETC2_R11_SNORM = 174,
223 TFMT5_ETC1 = 175,
224 TFMT5_ETC2_RGB8 = 176,
225 TFMT5_ETC2_RGBA8 = 177,
226 TFMT5_ETC2_RGB8A1 = 178,
227 TFMT5_DXT1 = 179,
228 TFMT5_DXT3 = 180,
229 TFMT5_DXT5 = 181,
230 TFMT5_RGTC1_UNORM = 183,
231 TFMT5_RGTC1_SNORM = 184,
232 TFMT5_RGTC2_UNORM = 187,
233 TFMT5_RGTC2_SNORM = 188,
234 TFMT5_BPTC_UFLOAT = 190,
235 TFMT5_BPTC_FLOAT = 191,
236 TFMT5_BPTC = 192,
237 TFMT5_ASTC_4x4 = 193,
238 TFMT5_ASTC_5x4 = 194,
239 TFMT5_ASTC_5x5 = 195,
240 TFMT5_ASTC_6x5 = 196,
241 TFMT5_ASTC_6x6 = 197,
242 TFMT5_ASTC_8x5 = 198,
243 TFMT5_ASTC_8x6 = 199,
244 TFMT5_ASTC_8x8 = 200,
245 TFMT5_ASTC_10x5 = 201,
246 TFMT5_ASTC_10x6 = 202,
247 TFMT5_ASTC_10x8 = 203,
248 TFMT5_ASTC_10x10 = 204,
249 TFMT5_ASTC_12x10 = 205,
250 TFMT5_ASTC_12x12 = 206,
251 };
252
253 enum a5xx_tex_fetchsize {
254 TFETCH5_1_BYTE = 0,
255 TFETCH5_2_BYTE = 1,
256 TFETCH5_4_BYTE = 2,
257 TFETCH5_8_BYTE = 3,
258 TFETCH5_16_BYTE = 4,
259 };
260
261 enum a5xx_depth_format {
262 DEPTH5_NONE = 0,
263 DEPTH5_16 = 1,
264 DEPTH5_24_8 = 2,
265 DEPTH5_32 = 4,
266 };
267
268 enum a5xx_blit_buf {
269 BLIT_MRT0 = 0,
270 BLIT_MRT1 = 1,
271 BLIT_MRT2 = 2,
272 BLIT_MRT3 = 3,
273 BLIT_MRT4 = 4,
274 BLIT_MRT5 = 5,
275 BLIT_MRT6 = 6,
276 BLIT_MRT7 = 7,
277 BLIT_ZS = 8,
278 BLIT_S = 9,
279 };
280
281 enum a5xx_cp_perfcounter_select {
282 PERF_CP_ALWAYS_COUNT = 0,
283 PERF_CP_BUSY_GFX_CORE_IDLE = 1,
284 PERF_CP_BUSY_CYCLES = 2,
285 PERF_CP_PFP_IDLE = 3,
286 PERF_CP_PFP_BUSY_WORKING = 4,
287 PERF_CP_PFP_STALL_CYCLES_ANY = 5,
288 PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
289 PERF_CP_PFP_ICACHE_MISS = 7,
290 PERF_CP_PFP_ICACHE_HIT = 8,
291 PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
292 PERF_CP_ME_BUSY_WORKING = 10,
293 PERF_CP_ME_IDLE = 11,
294 PERF_CP_ME_STARVE_CYCLES_ANY = 12,
295 PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
296 PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
297 PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
298 PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
299 PERF_CP_ME_STALL_CYCLES_ANY = 17,
300 PERF_CP_ME_ICACHE_MISS = 18,
301 PERF_CP_ME_ICACHE_HIT = 19,
302 PERF_CP_NUM_PREEMPTIONS = 20,
303 PERF_CP_PREEMPTION_REACTION_DELAY = 21,
304 PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
305 PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
306 PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
307 PERF_CP_PREDICATED_DRAWS_KILLED = 25,
308 PERF_CP_MODE_SWITCH = 26,
309 PERF_CP_ZPASS_DONE = 27,
310 PERF_CP_CONTEXT_DONE = 28,
311 PERF_CP_CACHE_FLUSH = 29,
312 PERF_CP_LONG_PREEMPTIONS = 30,
313 };
314
315 enum a5xx_rbbm_perfcounter_select {
316 PERF_RBBM_ALWAYS_COUNT = 0,
317 PERF_RBBM_ALWAYS_ON = 1,
318 PERF_RBBM_TSE_BUSY = 2,
319 PERF_RBBM_RAS_BUSY = 3,
320 PERF_RBBM_PC_DCALL_BUSY = 4,
321 PERF_RBBM_PC_VSD_BUSY = 5,
322 PERF_RBBM_STATUS_MASKED = 6,
323 PERF_RBBM_COM_BUSY = 7,
324 PERF_RBBM_DCOM_BUSY = 8,
325 PERF_RBBM_VBIF_BUSY = 9,
326 PERF_RBBM_VSC_BUSY = 10,
327 PERF_RBBM_TESS_BUSY = 11,
328 PERF_RBBM_UCHE_BUSY = 12,
329 PERF_RBBM_HLSQ_BUSY = 13,
330 };
331
332 enum a5xx_pc_perfcounter_select {
333 PERF_PC_BUSY_CYCLES = 0,
334 PERF_PC_WORKING_CYCLES = 1,
335 PERF_PC_STALL_CYCLES_VFD = 2,
336 PERF_PC_STALL_CYCLES_TSE = 3,
337 PERF_PC_STALL_CYCLES_VPC = 4,
338 PERF_PC_STALL_CYCLES_UCHE = 5,
339 PERF_PC_STALL_CYCLES_TESS = 6,
340 PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
341 PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
342 PERF_PC_PASS1_TF_STALL_CYCLES = 9,
343 PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
344 PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
345 PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
346 PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
347 PERF_PC_STARVE_CYCLES_DI = 14,
348 PERF_PC_VIS_STREAMS_LOADED = 15,
349 PERF_PC_INSTANCES = 16,
350 PERF_PC_VPC_PRIMITIVES = 17,
351 PERF_PC_DEAD_PRIM = 18,
352 PERF_PC_LIVE_PRIM = 19,
353 PERF_PC_VERTEX_HITS = 20,
354 PERF_PC_IA_VERTICES = 21,
355 PERF_PC_IA_PRIMITIVES = 22,
356 PERF_PC_GS_PRIMITIVES = 23,
357 PERF_PC_HS_INVOCATIONS = 24,
358 PERF_PC_DS_INVOCATIONS = 25,
359 PERF_PC_VS_INVOCATIONS = 26,
360 PERF_PC_GS_INVOCATIONS = 27,
361 PERF_PC_DS_PRIMITIVES = 28,
362 PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
363 PERF_PC_3D_DRAWCALLS = 30,
364 PERF_PC_2D_DRAWCALLS = 31,
365 PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
366 PERF_TESS_BUSY_CYCLES = 33,
367 PERF_TESS_WORKING_CYCLES = 34,
368 PERF_TESS_STALL_CYCLES_PC = 35,
369 PERF_TESS_STARVE_CYCLES_PC = 36,
370 };
371
372 enum a5xx_vfd_perfcounter_select {
373 PERF_VFD_BUSY_CYCLES = 0,
374 PERF_VFD_STALL_CYCLES_UCHE = 1,
375 PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
376 PERF_VFD_STALL_CYCLES_MISS_VB = 3,
377 PERF_VFD_STALL_CYCLES_MISS_Q = 4,
378 PERF_VFD_STALL_CYCLES_SP_INFO = 5,
379 PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
380 PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
381 PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
382 PERF_VFD_DECODER_PACKER_STALL = 9,
383 PERF_VFD_STARVE_CYCLES_UCHE = 10,
384 PERF_VFD_RBUFFER_FULL = 11,
385 PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
386 PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
387 PERF_VFD_NUM_ATTRIBUTES = 14,
388 PERF_VFD_INSTRUCTIONS = 15,
389 PERF_VFD_UPPER_SHADER_FIBERS = 16,
390 PERF_VFD_LOWER_SHADER_FIBERS = 17,
391 PERF_VFD_MODE_0_FIBERS = 18,
392 PERF_VFD_MODE_1_FIBERS = 19,
393 PERF_VFD_MODE_2_FIBERS = 20,
394 PERF_VFD_MODE_3_FIBERS = 21,
395 PERF_VFD_MODE_4_FIBERS = 22,
396 PERF_VFD_TOTAL_VERTICES = 23,
397 PERF_VFD_NUM_ATTR_MISS = 24,
398 PERF_VFD_1_BURST_REQ = 25,
399 PERF_VFDP_STALL_CYCLES_VFD = 26,
400 PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
401 PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
402 PERF_VFDP_STARVE_CYCLES_PC = 29,
403 PERF_VFDP_VS_STAGE_32_WAVES = 30,
404 };
405
406 enum a5xx_hlsq_perfcounter_select {
407 PERF_HLSQ_BUSY_CYCLES = 0,
408 PERF_HLSQ_STALL_CYCLES_UCHE = 1,
409 PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
410 PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
411 PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
412 PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
413 PERF_HLSQ_FS_STAGE_32_WAVES = 6,
414 PERF_HLSQ_FS_STAGE_64_WAVES = 7,
415 PERF_HLSQ_QUADS = 8,
416 PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
417 PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
418 PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
419 PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
420 PERF_HLSQ_CS_INVOCATIONS = 13,
421 PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
422 };
423
424 enum a5xx_vpc_perfcounter_select {
425 PERF_VPC_BUSY_CYCLES = 0,
426 PERF_VPC_WORKING_CYCLES = 1,
427 PERF_VPC_STALL_CYCLES_UCHE = 2,
428 PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
429 PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
430 PERF_VPC_STALL_CYCLES_PC = 5,
431 PERF_VPC_STALL_CYCLES_SP_LM = 6,
432 PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
433 PERF_VPC_STARVE_CYCLES_SP = 8,
434 PERF_VPC_STARVE_CYCLES_LRZ = 9,
435 PERF_VPC_PC_PRIMITIVES = 10,
436 PERF_VPC_SP_COMPONENTS = 11,
437 PERF_VPC_SP_LM_PRIMITIVES = 12,
438 PERF_VPC_SP_LM_COMPONENTS = 13,
439 PERF_VPC_SP_LM_DWORDS = 14,
440 PERF_VPC_STREAMOUT_COMPONENTS = 15,
441 PERF_VPC_GRANT_PHASES = 16,
442 };
443
444 enum a5xx_tse_perfcounter_select {
445 PERF_TSE_BUSY_CYCLES = 0,
446 PERF_TSE_CLIPPING_CYCLES = 1,
447 PERF_TSE_STALL_CYCLES_RAS = 2,
448 PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
449 PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
450 PERF_TSE_STARVE_CYCLES_PC = 5,
451 PERF_TSE_INPUT_PRIM = 6,
452 PERF_TSE_INPUT_NULL_PRIM = 7,
453 PERF_TSE_TRIVAL_REJ_PRIM = 8,
454 PERF_TSE_CLIPPED_PRIM = 9,
455 PERF_TSE_ZERO_AREA_PRIM = 10,
456 PERF_TSE_FACENESS_CULLED_PRIM = 11,
457 PERF_TSE_ZERO_PIXEL_PRIM = 12,
458 PERF_TSE_OUTPUT_NULL_PRIM = 13,
459 PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
460 PERF_TSE_CINVOCATION = 15,
461 PERF_TSE_CPRIMITIVES = 16,
462 PERF_TSE_2D_INPUT_PRIM = 17,
463 PERF_TSE_2D_ALIVE_CLCLES = 18,
464 };
465
466 enum a5xx_ras_perfcounter_select {
467 PERF_RAS_BUSY_CYCLES = 0,
468 PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
469 PERF_RAS_STALL_CYCLES_LRZ = 2,
470 PERF_RAS_STARVE_CYCLES_TSE = 3,
471 PERF_RAS_SUPER_TILES = 4,
472 PERF_RAS_8X4_TILES = 5,
473 PERF_RAS_MASKGEN_ACTIVE = 6,
474 PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
475 PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
476 PERF_RAS_PRIM_KILLED_INVISILBE = 9,
477 };
478
479 enum a5xx_lrz_perfcounter_select {
480 PERF_LRZ_BUSY_CYCLES = 0,
481 PERF_LRZ_STARVE_CYCLES_RAS = 1,
482 PERF_LRZ_STALL_CYCLES_RB = 2,
483 PERF_LRZ_STALL_CYCLES_VSC = 3,
484 PERF_LRZ_STALL_CYCLES_VPC = 4,
485 PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
486 PERF_LRZ_STALL_CYCLES_UCHE = 6,
487 PERF_LRZ_LRZ_READ = 7,
488 PERF_LRZ_LRZ_WRITE = 8,
489 PERF_LRZ_READ_LATENCY = 9,
490 PERF_LRZ_MERGE_CACHE_UPDATING = 10,
491 PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
492 PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
493 PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
494 PERF_LRZ_FULL_8X8_TILES = 14,
495 PERF_LRZ_PARTIAL_8X8_TILES = 15,
496 PERF_LRZ_TILE_KILLED = 16,
497 PERF_LRZ_TOTAL_PIXEL = 17,
498 PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
499 };
500
501 enum a5xx_uche_perfcounter_select {
502 PERF_UCHE_BUSY_CYCLES = 0,
503 PERF_UCHE_STALL_CYCLES_VBIF = 1,
504 PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
505 PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
506 PERF_UCHE_VBIF_READ_BEATS_TP = 4,
507 PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
508 PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
509 PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
510 PERF_UCHE_VBIF_READ_BEATS_SP = 8,
511 PERF_UCHE_READ_REQUESTS_TP = 9,
512 PERF_UCHE_READ_REQUESTS_VFD = 10,
513 PERF_UCHE_READ_REQUESTS_HLSQ = 11,
514 PERF_UCHE_READ_REQUESTS_LRZ = 12,
515 PERF_UCHE_READ_REQUESTS_SP = 13,
516 PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
517 PERF_UCHE_WRITE_REQUESTS_SP = 15,
518 PERF_UCHE_WRITE_REQUESTS_VPC = 16,
519 PERF_UCHE_WRITE_REQUESTS_VSC = 17,
520 PERF_UCHE_EVICTS = 18,
521 PERF_UCHE_BANK_REQ0 = 19,
522 PERF_UCHE_BANK_REQ1 = 20,
523 PERF_UCHE_BANK_REQ2 = 21,
524 PERF_UCHE_BANK_REQ3 = 22,
525 PERF_UCHE_BANK_REQ4 = 23,
526 PERF_UCHE_BANK_REQ5 = 24,
527 PERF_UCHE_BANK_REQ6 = 25,
528 PERF_UCHE_BANK_REQ7 = 26,
529 PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
530 PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
531 PERF_UCHE_GMEM_READ_BEATS = 29,
532 PERF_UCHE_FLAG_COUNT = 30,
533 };
534
535 enum a5xx_tp_perfcounter_select {
536 PERF_TP_BUSY_CYCLES = 0,
537 PERF_TP_STALL_CYCLES_UCHE = 1,
538 PERF_TP_LATENCY_CYCLES = 2,
539 PERF_TP_LATENCY_TRANS = 3,
540 PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
541 PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
542 PERF_TP_L1_CACHELINE_REQUESTS = 6,
543 PERF_TP_L1_CACHELINE_MISSES = 7,
544 PERF_TP_SP_TP_TRANS = 8,
545 PERF_TP_TP_SP_TRANS = 9,
546 PERF_TP_OUTPUT_PIXELS = 10,
547 PERF_TP_FILTER_WORKLOAD_16BIT = 11,
548 PERF_TP_FILTER_WORKLOAD_32BIT = 12,
549 PERF_TP_QUADS_RECEIVED = 13,
550 PERF_TP_QUADS_OFFSET = 14,
551 PERF_TP_QUADS_SHADOW = 15,
552 PERF_TP_QUADS_ARRAY = 16,
553 PERF_TP_QUADS_GRADIENT = 17,
554 PERF_TP_QUADS_1D = 18,
555 PERF_TP_QUADS_2D = 19,
556 PERF_TP_QUADS_BUFFER = 20,
557 PERF_TP_QUADS_3D = 21,
558 PERF_TP_QUADS_CUBE = 22,
559 PERF_TP_STATE_CACHE_REQUESTS = 23,
560 PERF_TP_STATE_CACHE_MISSES = 24,
561 PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
562 PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
563 PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
564 PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
565 PERF_TP_OUTPUT_PIXELS_POINT = 29,
566 PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
567 PERF_TP_OUTPUT_PIXELS_MIP = 31,
568 PERF_TP_OUTPUT_PIXELS_ANISO = 32,
569 PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
570 PERF_TP_FLAG_CACHE_REQUESTS = 34,
571 PERF_TP_FLAG_CACHE_MISSES = 35,
572 PERF_TP_L1_5_L2_REQUESTS = 36,
573 PERF_TP_2D_OUTPUT_PIXELS = 37,
574 PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
575 PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
576 PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
577 PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
578 };
579
580 enum a5xx_sp_perfcounter_select {
581 PERF_SP_BUSY_CYCLES = 0,
582 PERF_SP_ALU_WORKING_CYCLES = 1,
583 PERF_SP_EFU_WORKING_CYCLES = 2,
584 PERF_SP_STALL_CYCLES_VPC = 3,
585 PERF_SP_STALL_CYCLES_TP = 4,
586 PERF_SP_STALL_CYCLES_UCHE = 5,
587 PERF_SP_STALL_CYCLES_RB = 6,
588 PERF_SP_SCHEDULER_NON_WORKING = 7,
589 PERF_SP_WAVE_CONTEXTS = 8,
590 PERF_SP_WAVE_CONTEXT_CYCLES = 9,
591 PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
592 PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
593 PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
594 PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
595 PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
596 PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
597 PERF_SP_WAVE_CTRL_CYCLES = 16,
598 PERF_SP_WAVE_LOAD_CYCLES = 17,
599 PERF_SP_WAVE_EMIT_CYCLES = 18,
600 PERF_SP_WAVE_NOP_CYCLES = 19,
601 PERF_SP_WAVE_WAIT_CYCLES = 20,
602 PERF_SP_WAVE_FETCH_CYCLES = 21,
603 PERF_SP_WAVE_IDLE_CYCLES = 22,
604 PERF_SP_WAVE_END_CYCLES = 23,
605 PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
606 PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
607 PERF_SP_WAVE_JOIN_CYCLES = 26,
608 PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
609 PERF_SP_LM_STORE_INSTRUCTIONS = 28,
610 PERF_SP_LM_ATOMICS = 29,
611 PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
612 PERF_SP_GM_STORE_INSTRUCTIONS = 31,
613 PERF_SP_GM_ATOMICS = 32,
614 PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
615 PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
616 PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
617 PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
618 PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
619 PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
620 PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
621 PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
622 PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
623 PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
624 PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
625 PERF_SP_VS_INSTRUCTIONS = 44,
626 PERF_SP_FS_INSTRUCTIONS = 45,
627 PERF_SP_ADDR_LOCK_COUNT = 46,
628 PERF_SP_UCHE_READ_TRANS = 47,
629 PERF_SP_UCHE_WRITE_TRANS = 48,
630 PERF_SP_EXPORT_VPC_TRANS = 49,
631 PERF_SP_EXPORT_RB_TRANS = 50,
632 PERF_SP_PIXELS_KILLED = 51,
633 PERF_SP_ICL1_REQUESTS = 52,
634 PERF_SP_ICL1_MISSES = 53,
635 PERF_SP_ICL0_REQUESTS = 54,
636 PERF_SP_ICL0_MISSES = 55,
637 PERF_SP_HS_INSTRUCTIONS = 56,
638 PERF_SP_DS_INSTRUCTIONS = 57,
639 PERF_SP_GS_INSTRUCTIONS = 58,
640 PERF_SP_CS_INSTRUCTIONS = 59,
641 PERF_SP_GPR_READ = 60,
642 PERF_SP_GPR_WRITE = 61,
643 PERF_SP_LM_CH0_REQUESTS = 62,
644 PERF_SP_LM_CH1_REQUESTS = 63,
645 PERF_SP_LM_BANK_CONFLICTS = 64,
646 };
647
648 enum a5xx_rb_perfcounter_select {
649 PERF_RB_BUSY_CYCLES = 0,
650 PERF_RB_STALL_CYCLES_CCU = 1,
651 PERF_RB_STALL_CYCLES_HLSQ = 2,
652 PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
653 PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
654 PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
655 PERF_RB_STARVE_CYCLES_SP = 6,
656 PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
657 PERF_RB_STARVE_CYCLES_CCU = 8,
658 PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
659 PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
660 PERF_RB_Z_WORKLOAD = 11,
661 PERF_RB_HLSQ_ACTIVE = 12,
662 PERF_RB_Z_READ = 13,
663 PERF_RB_Z_WRITE = 14,
664 PERF_RB_C_READ = 15,
665 PERF_RB_C_WRITE = 16,
666 PERF_RB_TOTAL_PASS = 17,
667 PERF_RB_Z_PASS = 18,
668 PERF_RB_Z_FAIL = 19,
669 PERF_RB_S_FAIL = 20,
670 PERF_RB_BLENDED_FXP_COMPONENTS = 21,
671 PERF_RB_BLENDED_FP16_COMPONENTS = 22,
672 RB_RESERVED = 23,
673 PERF_RB_2D_ALIVE_CYCLES = 24,
674 PERF_RB_2D_STALL_CYCLES_A2D = 25,
675 PERF_RB_2D_STARVE_CYCLES_SRC = 26,
676 PERF_RB_2D_STARVE_CYCLES_SP = 27,
677 PERF_RB_2D_STARVE_CYCLES_DST = 28,
678 PERF_RB_2D_VALID_PIXELS = 29,
679 };
680
681 enum a5xx_rb_samples_perfcounter_select {
682 TOTAL_SAMPLES = 0,
683 ZPASS_SAMPLES = 1,
684 ZFAIL_SAMPLES = 2,
685 SFAIL_SAMPLES = 3,
686 };
687
688 enum a5xx_vsc_perfcounter_select {
689 PERF_VSC_BUSY_CYCLES = 0,
690 PERF_VSC_WORKING_CYCLES = 1,
691 PERF_VSC_STALL_CYCLES_UCHE = 2,
692 PERF_VSC_EOT_NUM = 3,
693 };
694
695 enum a5xx_ccu_perfcounter_select {
696 PERF_CCU_BUSY_CYCLES = 0,
697 PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
698 PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
699 PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
700 PERF_CCU_DEPTH_BLOCKS = 4,
701 PERF_CCU_COLOR_BLOCKS = 5,
702 PERF_CCU_DEPTH_BLOCK_HIT = 6,
703 PERF_CCU_COLOR_BLOCK_HIT = 7,
704 PERF_CCU_PARTIAL_BLOCK_READ = 8,
705 PERF_CCU_GMEM_READ = 9,
706 PERF_CCU_GMEM_WRITE = 10,
707 PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
708 PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
709 PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
710 PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
711 PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
712 PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
713 PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
714 PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
715 PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
716 PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
717 PERF_CCU_2D_BUSY_CYCLES = 21,
718 PERF_CCU_2D_RD_REQ = 22,
719 PERF_CCU_2D_WR_REQ = 23,
720 PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
721 PERF_CCU_2D_PIXELS = 25,
722 };
723
724 enum a5xx_cmp_perfcounter_select {
725 PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
726 PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
727 PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
728 PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
729 PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
730 PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
731 PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
732 PERF_CMPDECMP_VBIF_READ_DATA = 7,
733 PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
734 PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
735 PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
736 PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
737 PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
738 PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
739 PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
740 PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
741 PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
742 PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
743 PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
744 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
745 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
746 PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
747 PERF_CMPDECMP_2D_RD_DATA = 22,
748 PERF_CMPDECMP_2D_WR_DATA = 23,
749 };
750
751 enum a5xx_vbif_perfcounter_select {
752 AXI_READ_REQUESTS_ID_0 = 0,
753 AXI_READ_REQUESTS_ID_1 = 1,
754 AXI_READ_REQUESTS_ID_2 = 2,
755 AXI_READ_REQUESTS_ID_3 = 3,
756 AXI_READ_REQUESTS_ID_4 = 4,
757 AXI_READ_REQUESTS_ID_5 = 5,
758 AXI_READ_REQUESTS_ID_6 = 6,
759 AXI_READ_REQUESTS_ID_7 = 7,
760 AXI_READ_REQUESTS_ID_8 = 8,
761 AXI_READ_REQUESTS_ID_9 = 9,
762 AXI_READ_REQUESTS_ID_10 = 10,
763 AXI_READ_REQUESTS_ID_11 = 11,
764 AXI_READ_REQUESTS_ID_12 = 12,
765 AXI_READ_REQUESTS_ID_13 = 13,
766 AXI_READ_REQUESTS_ID_14 = 14,
767 AXI_READ_REQUESTS_ID_15 = 15,
768 AXI0_READ_REQUESTS_TOTAL = 16,
769 AXI1_READ_REQUESTS_TOTAL = 17,
770 AXI2_READ_REQUESTS_TOTAL = 18,
771 AXI3_READ_REQUESTS_TOTAL = 19,
772 AXI_READ_REQUESTS_TOTAL = 20,
773 AXI_WRITE_REQUESTS_ID_0 = 21,
774 AXI_WRITE_REQUESTS_ID_1 = 22,
775 AXI_WRITE_REQUESTS_ID_2 = 23,
776 AXI_WRITE_REQUESTS_ID_3 = 24,
777 AXI_WRITE_REQUESTS_ID_4 = 25,
778 AXI_WRITE_REQUESTS_ID_5 = 26,
779 AXI_WRITE_REQUESTS_ID_6 = 27,
780 AXI_WRITE_REQUESTS_ID_7 = 28,
781 AXI_WRITE_REQUESTS_ID_8 = 29,
782 AXI_WRITE_REQUESTS_ID_9 = 30,
783 AXI_WRITE_REQUESTS_ID_10 = 31,
784 AXI_WRITE_REQUESTS_ID_11 = 32,
785 AXI_WRITE_REQUESTS_ID_12 = 33,
786 AXI_WRITE_REQUESTS_ID_13 = 34,
787 AXI_WRITE_REQUESTS_ID_14 = 35,
788 AXI_WRITE_REQUESTS_ID_15 = 36,
789 AXI0_WRITE_REQUESTS_TOTAL = 37,
790 AXI1_WRITE_REQUESTS_TOTAL = 38,
791 AXI2_WRITE_REQUESTS_TOTAL = 39,
792 AXI3_WRITE_REQUESTS_TOTAL = 40,
793 AXI_WRITE_REQUESTS_TOTAL = 41,
794 AXI_TOTAL_REQUESTS = 42,
795 AXI_READ_DATA_BEATS_ID_0 = 43,
796 AXI_READ_DATA_BEATS_ID_1 = 44,
797 AXI_READ_DATA_BEATS_ID_2 = 45,
798 AXI_READ_DATA_BEATS_ID_3 = 46,
799 AXI_READ_DATA_BEATS_ID_4 = 47,
800 AXI_READ_DATA_BEATS_ID_5 = 48,
801 AXI_READ_DATA_BEATS_ID_6 = 49,
802 AXI_READ_DATA_BEATS_ID_7 = 50,
803 AXI_READ_DATA_BEATS_ID_8 = 51,
804 AXI_READ_DATA_BEATS_ID_9 = 52,
805 AXI_READ_DATA_BEATS_ID_10 = 53,
806 AXI_READ_DATA_BEATS_ID_11 = 54,
807 AXI_READ_DATA_BEATS_ID_12 = 55,
808 AXI_READ_DATA_BEATS_ID_13 = 56,
809 AXI_READ_DATA_BEATS_ID_14 = 57,
810 AXI_READ_DATA_BEATS_ID_15 = 58,
811 AXI0_READ_DATA_BEATS_TOTAL = 59,
812 AXI1_READ_DATA_BEATS_TOTAL = 60,
813 AXI2_READ_DATA_BEATS_TOTAL = 61,
814 AXI3_READ_DATA_BEATS_TOTAL = 62,
815 AXI_READ_DATA_BEATS_TOTAL = 63,
816 AXI_WRITE_DATA_BEATS_ID_0 = 64,
817 AXI_WRITE_DATA_BEATS_ID_1 = 65,
818 AXI_WRITE_DATA_BEATS_ID_2 = 66,
819 AXI_WRITE_DATA_BEATS_ID_3 = 67,
820 AXI_WRITE_DATA_BEATS_ID_4 = 68,
821 AXI_WRITE_DATA_BEATS_ID_5 = 69,
822 AXI_WRITE_DATA_BEATS_ID_6 = 70,
823 AXI_WRITE_DATA_BEATS_ID_7 = 71,
824 AXI_WRITE_DATA_BEATS_ID_8 = 72,
825 AXI_WRITE_DATA_BEATS_ID_9 = 73,
826 AXI_WRITE_DATA_BEATS_ID_10 = 74,
827 AXI_WRITE_DATA_BEATS_ID_11 = 75,
828 AXI_WRITE_DATA_BEATS_ID_12 = 76,
829 AXI_WRITE_DATA_BEATS_ID_13 = 77,
830 AXI_WRITE_DATA_BEATS_ID_14 = 78,
831 AXI_WRITE_DATA_BEATS_ID_15 = 79,
832 AXI0_WRITE_DATA_BEATS_TOTAL = 80,
833 AXI1_WRITE_DATA_BEATS_TOTAL = 81,
834 AXI2_WRITE_DATA_BEATS_TOTAL = 82,
835 AXI3_WRITE_DATA_BEATS_TOTAL = 83,
836 AXI_WRITE_DATA_BEATS_TOTAL = 84,
837 AXI_DATA_BEATS_TOTAL = 85,
838 };
839
840 enum a5xx_tex_filter {
841 A5XX_TEX_NEAREST = 0,
842 A5XX_TEX_LINEAR = 1,
843 A5XX_TEX_ANISO = 2,
844 };
845
846 enum a5xx_tex_clamp {
847 A5XX_TEX_REPEAT = 0,
848 A5XX_TEX_CLAMP_TO_EDGE = 1,
849 A5XX_TEX_MIRROR_REPEAT = 2,
850 A5XX_TEX_CLAMP_TO_BORDER = 3,
851 A5XX_TEX_MIRROR_CLAMP = 4,
852 };
853
854 enum a5xx_tex_aniso {
855 A5XX_TEX_ANISO_1 = 0,
856 A5XX_TEX_ANISO_2 = 1,
857 A5XX_TEX_ANISO_4 = 2,
858 A5XX_TEX_ANISO_8 = 3,
859 A5XX_TEX_ANISO_16 = 4,
860 };
861
862 enum a5xx_tex_swiz {
863 A5XX_TEX_X = 0,
864 A5XX_TEX_Y = 1,
865 A5XX_TEX_Z = 2,
866 A5XX_TEX_W = 3,
867 A5XX_TEX_ZERO = 4,
868 A5XX_TEX_ONE = 5,
869 };
870
871 enum a5xx_tex_type {
872 A5XX_TEX_1D = 0,
873 A5XX_TEX_2D = 1,
874 A5XX_TEX_CUBE = 2,
875 A5XX_TEX_3D = 3,
876 };
877
878 #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
879 #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
880 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
881 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
882 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
883 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
884 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
885 #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
886 #define A5XX_INT0_CP_SW 0x00000100
887 #define A5XX_INT0_CP_HW_ERROR 0x00000200
888 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
889 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
890 #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
891 #define A5XX_INT0_CP_IB2 0x00002000
892 #define A5XX_INT0_CP_IB1 0x00004000
893 #define A5XX_INT0_CP_RB 0x00008000
894 #define A5XX_INT0_CP_UNUSED_1 0x00010000
895 #define A5XX_INT0_CP_RB_DONE_TS 0x00020000
896 #define A5XX_INT0_CP_WT_DONE_TS 0x00040000
897 #define A5XX_INT0_UNKNOWN_1 0x00080000
898 #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
899 #define A5XX_INT0_UNUSED_2 0x00200000
900 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
901 #define A5XX_INT0_MISC_HANG_DETECT 0x00800000
902 #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
903 #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
904 #define A5XX_INT0_DEBBUS_INTR_0 0x04000000
905 #define A5XX_INT0_DEBBUS_INTR_1 0x08000000
906 #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
907 #define A5XX_INT0_GPMU_FIRMWARE 0x20000000
908 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
909 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
910 #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
911 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
912 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
913 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
914 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
915 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
916 #define REG_A5XX_CP_RB_BASE 0x00000800
917
918 #define REG_A5XX_CP_RB_BASE_HI 0x00000801
919
920 #define REG_A5XX_CP_RB_CNTL 0x00000802
921
922 #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
923
924 #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
925
926 #define REG_A5XX_CP_RB_RPTR 0x00000806
927
928 #define REG_A5XX_CP_RB_WPTR 0x00000807
929
930 #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
931
932 #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
933
934 #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
935
936 #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
937
938 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
939
940 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
941
942 #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
943
944 #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
945
946 #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
947
948 #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
949
950 #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
951
952 #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
953
954 #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
955
956 #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
957
958 #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
959
960 #define REG_A5XX_CP_MERCIU_SIZE 0x00000826
961
962 #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
963
964 #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
965
966 #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
967
968 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
969
970 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
971
972 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
973
974 #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
975
976 #define REG_A5XX_CP_CNTL 0x00000831
977
978 #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
979
980 #define REG_A5XX_CP_CHICKEN_DBG 0x00000833
981
982 #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
983
984 #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
985
986 #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
987
988 #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
989
990 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
991
992 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
993
994 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
995
996 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
997
998 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
999
1000 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
1001
1002 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
1003
1004 #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
1005
1006 #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
1007
1008 #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
1009
1010 #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
1011
1012 #define REG_A5XX_CP_HW_FAULT 0x00000b1a
1013
1014 #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
1015
1016 #define REG_A5XX_CP_IB1_BASE 0x00000b1f
1017
1018 #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
1019
1020 #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
1021
1022 #define REG_A5XX_CP_IB2_BASE 0x00000b22
1023
1024 #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
1025
1026 #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
1027
1028 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1029
1030 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1031
1032 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1033
1034 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1035 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
1036 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
1037 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1038 {
1039 return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1040 }
1041 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
1042 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
1043 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1044 {
1045 return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
1046 }
1047 #define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
1048 #define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
1049
1050 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
1051
1052 #define REG_A5XX_CP_AHB_FAULT 0x00000b1b
1053
1054 #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
1055
1056 #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
1057
1058 #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
1059
1060 #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
1061
1062 #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
1063
1064 #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
1065
1066 #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
1067
1068 #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
1069
1070 #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
1071
1072 #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
1073
1074 #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
1075
1076 #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
1077
1078 #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
1079
1080 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
1081
1082 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
1083
1084 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
1085
1086 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
1087
1088 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
1089
1090 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
1091
1092 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
1093
1094 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
1095
1096 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
1097
1098 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
1099
1100 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
1101
1102 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
1103
1104 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
1105
1106 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
1107
1108 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
1109
1110 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
1111
1112 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
1113
1114 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
1115
1116 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
1117
1118 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
1119
1120 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
1121
1122 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
1123
1124 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
1125
1126 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
1127
1128 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
1129
1130 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
1131
1132 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
1133
1134 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
1135
1136 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
1137
1138 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
1139
1140 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
1141
1142 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
1143
1144 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
1145
1146 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
1147
1148 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
1149
1150 #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
1151
1152 #define REG_A5XX_RBBM_INT_0_MASK 0x00000038
1153 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
1154 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
1155 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
1156 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
1157 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
1158 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
1159 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
1160 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
1161 #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
1162 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
1163 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
1164 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
1165 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
1166 #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
1167 #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
1168 #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
1169 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
1170 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
1171 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
1172 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
1173 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
1174 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
1175 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
1176 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
1177 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
1178 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
1179 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
1180 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
1181 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
1182
1183 #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
1184
1185 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
1186
1187 #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
1188
1189 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1190
1191 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1192
1193 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
1194
1195 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
1196
1197 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
1198
1199 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
1200
1201 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
1202
1203 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
1204
1205 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
1206
1207 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
1208
1209 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
1210
1211 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
1212
1213 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
1214
1215 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
1216
1217 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
1218
1219 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
1220
1221 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
1222
1223 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
1224
1225 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
1226
1227 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
1228
1229 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
1230
1231 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
1232
1233 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
1234
1235 #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
1236
1237 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
1238
1239 #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
1240
1241 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
1242
1243 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
1244
1245 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
1246
1247 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
1248
1249 #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
1250
1251 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
1252
1253 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
1254
1255 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
1256
1257 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
1258
1259 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
1260
1261 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
1262
1263 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
1264
1265 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
1266
1267 #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
1268
1269 #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
1270
1271 #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
1272
1273 #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
1274
1275 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
1276
1277 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
1278
1279 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
1280
1281 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
1282
1283 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
1284
1285 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
1286
1287 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
1288
1289 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
1290
1291 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
1292
1293 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
1294
1295 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
1296
1297 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
1298
1299 #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
1300
1301 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
1302
1303 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
1304
1305 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
1306
1307 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
1308
1309 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
1310
1311 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
1312
1313 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
1314
1315 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
1316
1317 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
1318
1319 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
1320
1321 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
1322
1323 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
1324
1325 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
1326
1327 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
1328
1329 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
1330
1331 #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
1332
1333 #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
1334
1335 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
1336
1337 #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
1338
1339 #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
1340
1341 #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
1342
1343 #define REG_A5XX_RBBM_AHB_CMD 0x00000096
1344
1345 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
1346
1347 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
1348
1349 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
1350
1351 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
1352
1353 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
1354
1355 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
1356
1357 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
1358
1359 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
1360
1361 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
1362
1363 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
1364
1365 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
1366
1367 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
1368
1369 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
1370
1371 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
1372
1373 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
1374
1375 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
1376
1377 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
1378
1379 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
1380
1381 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
1382
1383 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
1384
1385 #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
1386
1387 #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
1388
1389 #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
1390
1391 #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
1392
1393 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
1394
1395 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
1396
1397 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
1398
1399 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
1400
1401 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
1402
1403 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
1404
1405 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
1406
1407 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
1408
1409 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
1410
1411 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
1412
1413 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
1414
1415 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
1416
1417 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
1418
1419 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
1420
1421 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
1422
1423 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
1424
1425 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
1426
1427 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
1428
1429 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
1430
1431 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
1432
1433 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
1434
1435 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
1436
1437 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
1438
1439 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
1440
1441 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
1442
1443 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
1444
1445 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
1446
1447 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
1448
1449 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
1450
1451 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
1452
1453 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
1454
1455 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
1456
1457 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
1458
1459 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
1460
1461 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
1462
1463 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
1464
1465 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
1466
1467 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
1468
1469 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
1470
1471 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
1472
1473 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
1474
1475 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
1476
1477 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
1478
1479 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
1480
1481 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
1482
1483 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
1484
1485 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
1486
1487 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
1488
1489 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
1490
1491 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
1492
1493 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
1494
1495 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
1496
1497 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
1498
1499 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
1500
1501 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
1502
1503 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
1504
1505 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
1506
1507 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
1508
1509 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
1510
1511 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
1512
1513 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
1514
1515 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
1516
1517 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
1518
1519 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
1520
1521 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
1522
1523 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
1524
1525 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
1526
1527 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
1528
1529 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
1530
1531 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
1532
1533 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
1534
1535 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
1536
1537 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
1538
1539 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
1540
1541 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
1542
1543 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
1544
1545 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
1546
1547 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
1548
1549 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
1550
1551 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
1552
1553 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
1554
1555 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
1556
1557 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
1558
1559 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
1560
1561 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
1562
1563 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
1564
1565 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
1566
1567 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
1568
1569 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
1570
1571 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
1572
1573 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
1574
1575 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
1576
1577 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
1578
1579 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
1580
1581 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
1582
1583 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
1584
1585 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
1586
1587 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
1588
1589 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
1590
1591 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
1592
1593 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
1594
1595 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
1596
1597 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
1598
1599 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
1600
1601 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
1602
1603 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
1604
1605 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
1606
1607 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
1608
1609 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
1610
1611 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
1612
1613 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
1614
1615 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
1616
1617 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
1618
1619 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
1620
1621 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
1622
1623 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
1624
1625 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
1626
1627 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
1628
1629 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
1630
1631 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
1632
1633 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
1634
1635 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
1636
1637 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
1638
1639 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
1640
1641 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
1642
1643 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
1644
1645 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
1646
1647 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
1648
1649 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
1650
1651 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
1652
1653 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
1654
1655 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
1656
1657 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
1658
1659 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
1660
1661 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
1662
1663 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
1664
1665 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
1666
1667 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
1668
1669 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
1670
1671 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
1672
1673 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
1674
1675 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
1676
1677 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
1678
1679 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
1680
1681 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
1682
1683 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
1684
1685 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
1686
1687 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
1688
1689 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
1690
1691 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
1692
1693 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
1694
1695 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
1696
1697 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
1698
1699 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
1700
1701 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
1702
1703 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
1704
1705 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
1706
1707 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
1708
1709 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
1710
1711 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
1712
1713 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
1714
1715 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
1716
1717 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
1718
1719 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
1720
1721 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
1722
1723 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
1724
1725 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
1726
1727 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
1728
1729 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
1730
1731 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
1732
1733 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
1734
1735 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
1736
1737 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
1738
1739 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
1740
1741 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
1742
1743 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
1744
1745 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
1746
1747 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
1748
1749 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
1750
1751 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
1752
1753 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
1754
1755 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
1756
1757 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
1758
1759 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
1760
1761 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
1762
1763 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
1764
1765 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
1766
1767 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
1768
1769 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
1770
1771 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
1772
1773 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
1774
1775 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
1776
1777 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
1778
1779 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
1780
1781 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
1782
1783 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
1784
1785 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
1786
1787 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
1788
1789 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
1790
1791 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
1792
1793 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
1794
1795 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
1796
1797 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
1798
1799 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
1800
1801 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
1802
1803 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
1804
1805 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
1806
1807 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1808
1809 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1810
1811 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1812
1813 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1814
1815 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
1816
1817 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
1818
1819 #define REG_A5XX_RBBM_STATUS 0x000004f5
1820 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
1821 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
1822 #define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1823 #define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
1824 #define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
1825 #define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
1826 #define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
1827 #define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
1828 #define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
1829 #define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
1830 #define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
1831 #define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1832 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1833 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
1834 #define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
1835 #define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
1836 #define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
1837 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
1838 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
1839 #define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
1840 #define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
1841 #define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
1842 #define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
1843 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
1844 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
1845 #define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
1846 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
1847 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
1848 #define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
1849 #define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1850 #define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1851 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
1852
1853 #define REG_A5XX_RBBM_STATUS3 0x00000530
1854
1855 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
1856
1857 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
1858
1859 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
1860
1861 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
1862
1863 #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
1864
1865 #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
1866
1867 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
1868
1869 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
1870
1871 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
1872
1873 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
1874
1875 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
1876
1877 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
1878
1879 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1880
1881 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1882
1883 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1884
1885 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1886
1887 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
1888
1889 #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
1890
1891 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
1892
1893 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
1894
1895 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
1896
1897 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
1898
1899 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
1900
1901 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
1902
1903 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
1904
1905 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
1906
1907 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
1908
1909 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
1910
1911 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
1912
1913 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
1914
1915 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
1916
1917 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
1918
1919 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
1920
1921 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
1922
1923 #define REG_A5XX_RBBM_ISDB_CNT 0x00000533
1924
1925 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
1926
1927 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1928
1929 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1930
1931 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1932
1933 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1934
1935 #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1936
1937 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
1938
1939 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
1940
1941 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
1942
1943 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
1944
1945 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1946
1947 #define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
1948 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
1949 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1950 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1951 {
1952 assert(!(val & 0x1f));
1953 return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
1954 }
1955 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
1956 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
1957 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1958 {
1959 assert(!(val & 0x1f));
1960 return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
1961 }
1962
1963 #define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
1964
1965 #define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
1966
1967 #define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
1968
1969 #define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
1970
1971 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
1972
1973 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
1974 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1975 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1976 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1977 {
1978 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
1979 }
1980 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1981 #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1982 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1983 {
1984 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1985 }
1986 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1987 #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1988 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1989 {
1990 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
1991 }
1992 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1993 #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
1994 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
1995 {
1996 return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
1997 }
1998
1999 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2000
2001 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2002
2003 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
2004
2005 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2006
2007 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2008
2009 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
2010
2011 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
2012
2013 #define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
2014 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
2015 #define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
2016 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
2017 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
2018 {
2019 return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
2020 }
2021 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
2022 #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
2023 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
2024 {
2025 return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
2026 }
2027
2028 #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
2029
2030 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
2031
2032 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
2033
2034 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
2035
2036 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
2037
2038 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
2039
2040 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
2041
2042 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
2043
2044 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
2045
2046 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
2047
2048 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
2049
2050 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
2051
2052 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
2053
2054 #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
2055
2056 #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
2057
2058 #define REG_A5XX_RB_MODE_CNTL 0x00000cc6
2059
2060 #define REG_A5XX_RB_CCU_CNTL 0x00000cc7
2061
2062 #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
2063
2064 #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
2065
2066 #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
2067
2068 #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
2069
2070 #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
2071
2072 #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
2073
2074 #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
2075
2076 #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
2077
2078 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
2079
2080 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
2081
2082 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
2083
2084 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
2085
2086 #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
2087
2088 #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
2089
2090 #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
2091
2092 #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
2093
2094 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
2095
2096 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
2097
2098 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
2099
2100 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
2101
2102 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
2103
2104 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
2105
2106 #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
2107 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
2108
2109 #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
2110
2111 #define REG_A5XX_PC_MODE_CNTL 0x00000d02
2112
2113 #define REG_A5XX_UNKNOWN_0D08 0x00000d08
2114
2115 #define REG_A5XX_UNKNOWN_0D09 0x00000d09
2116
2117 #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2118
2119 #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
2120
2121 #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
2122
2123 #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
2124
2125 #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
2126
2127 #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
2128
2129 #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
2130
2131 #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2132
2133 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
2134
2135 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
2136
2137 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
2138
2139 #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
2140
2141 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
2142
2143 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
2144
2145 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
2146
2147 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
2148
2149 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
2150
2151 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
2152
2153 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
2154
2155 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
2156
2157 #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
2158
2159 #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
2160
2161 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
2162
2163 #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
2164
2165 #define REG_A5XX_VFD_MODE_CNTL 0x00000e42
2166
2167 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
2168
2169 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
2170
2171 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
2172
2173 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
2174
2175 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
2176
2177 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
2178
2179 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
2180
2181 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
2182
2183 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
2184
2185 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
2186
2187 #define REG_A5XX_VPC_MODE_CNTL 0x00000e62
2188 #define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
2189
2190 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
2191
2192 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
2193
2194 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
2195
2196 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
2197
2198 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
2199
2200 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
2201
2202 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
2203
2204 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
2205
2206 #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
2207
2208 #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
2209
2210 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
2211
2212 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
2213
2214 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
2215
2216 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
2217
2218 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
2219
2220 #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
2221
2222 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
2223
2224 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
2225
2226 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
2227
2228 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
2229
2230 #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
2231
2232 #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
2233
2234 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
2235
2236 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
2237
2238 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
2239
2240 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
2241
2242 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
2243
2244 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
2245
2246 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
2247
2248 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
2249
2250 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
2251
2252 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
2253
2254 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
2255
2256 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
2257
2258 #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
2259
2260 #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
2261
2262 #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
2263
2264 #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
2265
2266 #define REG_A5XX_SP_MODE_CNTL 0x00000ec2
2267
2268 #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
2269
2270 #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
2271
2272 #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
2273
2274 #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
2275
2276 #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
2277
2278 #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
2279
2280 #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
2281
2282 #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
2283
2284 #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
2285
2286 #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
2287
2288 #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
2289
2290 #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
2291
2292 #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
2293
2294 #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
2295
2296 #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
2297
2298 #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
2299
2300 #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
2301
2302 #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
2303
2304 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
2305
2306 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
2307
2308 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
2309
2310 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
2311
2312 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
2313
2314 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
2315
2316 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
2317
2318 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
2319
2320 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
2321
2322 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
2323
2324 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
2325
2326 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
2327
2328 #define REG_A5XX_VBIF_VERSION 0x00003000
2329
2330 #define REG_A5XX_VBIF_CLKON 0x00003001
2331
2332 #define REG_A5XX_VBIF_ABIT_SORT 0x00003028
2333
2334 #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
2335
2336 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2337
2338 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2339
2340 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2341
2342 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2343
2344 #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
2345
2346 #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
2347
2348 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
2349
2350 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
2351
2352 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
2353
2354 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
2355
2356 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
2357
2358 #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
2359
2360 #define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0
2361
2362 #define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1
2363
2364 #define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2
2365
2366 #define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3
2367
2368 #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
2369
2370 #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
2371
2372 #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
2373
2374 #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
2375
2376 #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
2377
2378 #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
2379
2380 #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
2381
2382 #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
2383
2384 #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
2385
2386 #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
2387
2388 #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
2389
2390 #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
2391
2392 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
2393
2394 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
2395
2396 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
2397
2398 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
2399
2400 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
2401
2402 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
2403
2404 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
2405
2406 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
2407
2408 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2409
2410 #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
2411
2412 #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
2413
2414 #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
2415
2416 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
2417
2418 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
2419
2420 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
2421 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
2422
2423 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
2424 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
2425
2426 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
2427
2428 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
2429
2430 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
2431
2432 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
2433
2434 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
2435
2436 #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
2437
2438 #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
2439
2440 #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
2441
2442 #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
2443
2444 #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
2445
2446 #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
2447
2448 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
2449
2450 #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
2451
2452 #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
2453
2454 #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
2455
2456 #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
2457
2458 #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
2459
2460 #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
2461
2462 #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
2463
2464 #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
2465
2466 #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
2467
2468 #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
2469
2470 #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
2471
2472 #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
2473
2474 #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
2475
2476 #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
2477
2478 #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
2479
2480 #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
2481
2482 #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
2483
2484 #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
2485
2486 #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
2487
2488 #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
2489
2490 #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
2491
2492 #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
2493
2494 #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
2495
2496 #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
2497
2498 #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
2499
2500 #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
2501
2502 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
2503
2504 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
2505
2506 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
2507
2508 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
2509
2510 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
2511
2512 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
2513
2514 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
2515
2516 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
2517
2518 #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
2519
2520 #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
2521
2522 #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
2523
2524 #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
2525
2526 #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
2527
2528 #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
2529
2530 #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
2531
2532 #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
2533
2534 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
2535
2536 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
2537
2538 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
2539
2540 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
2541
2542 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
2543
2544 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
2545
2546 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
2547
2548 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
2549
2550 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
2551
2552 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
2553
2554 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
2555
2556 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
2557
2558 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
2559
2560 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
2561
2562 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
2563
2564 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
2565
2566 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
2567
2568 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
2569
2570 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
2571
2572 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
2573
2574 #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
2575
2576 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
2577
2578 #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
2579
2580 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
2581
2582 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
2583
2584 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
2585
2586 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
2587
2588 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
2589
2590 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
2591
2592 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
2593
2594 #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
2595
2596 #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
2597
2598 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
2599
2600 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
2601
2602 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
2603
2604 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
2605
2606 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
2607
2608 #define REG_A5XX_GDPM_CONFIG1 0x0000b80c
2609
2610 #define REG_A5XX_GDPM_CONFIG2 0x0000b80d
2611
2612 #define REG_A5XX_GDPM_INT_EN 0x0000b80f
2613
2614 #define REG_A5XX_GDPM_INT_MASK 0x0000b811
2615
2616 #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
2617
2618 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
2619
2620 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
2621
2622 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
2623
2624 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
2625
2626 #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
2627
2628 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
2629
2630 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000
2631 #define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2632
2633 #define REG_A5XX_UNKNOWN_E001 0x0000e001
2634
2635 #define REG_A5XX_UNKNOWN_E004 0x0000e004
2636
2637 #define REG_A5XX_GRAS_CNTL 0x0000e005
2638 #define A5XX_GRAS_CNTL_VARYING 0x00000001
2639 #define A5XX_GRAS_CNTL_UNK3 0x00000008
2640 #define A5XX_GRAS_CNTL_XCOORD 0x00000040
2641 #define A5XX_GRAS_CNTL_YCOORD 0x00000080
2642 #define A5XX_GRAS_CNTL_ZCOORD 0x00000100
2643 #define A5XX_GRAS_CNTL_WCOORD 0x00000200
2644
2645 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
2646 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
2647 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
2648 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2649 {
2650 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2651 }
2652 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
2653 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
2654 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2655 {
2656 return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2657 }
2658
2659 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
2660 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2661 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2662 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2663 {
2664 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2665 }
2666
2667 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
2668 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2669 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2670 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
2671 {
2672 return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2673 }
2674
2675 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
2676 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2677 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2678 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2679 {
2680 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2681 }
2682
2683 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
2684 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2685 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2686 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
2687 {
2688 return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2689 }
2690
2691 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
2692 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2693 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2694 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2695 {
2696 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2697 }
2698
2699 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
2700 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2701 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2702 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2703 {
2704 return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2705 }
2706
2707 #define REG_A5XX_GRAS_SU_CNTL 0x0000e090
2708 #define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2709 #define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2710 #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2711 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2712 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
2713 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2714 {
2715 return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2716 }
2717 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2718 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2719
2720 #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
2721 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2722 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2723 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2724 {
2725 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2726 }
2727 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2728 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2729 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2730 {
2731 return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2732 }
2733
2734 #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
2735 #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2736 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
2737 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
2738 {
2739 return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
2740 }
2741
2742 #define REG_A5XX_UNKNOWN_E093 0x0000e093
2743
2744 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
2745 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2746 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002
2747
2748 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
2749 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2750 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2751 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2752 {
2753 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2754 }
2755
2756 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
2757 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2758 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2759 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2760 {
2761 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2762 }
2763
2764 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
2765 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2766 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2767 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2768 {
2769 return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2770 }
2771
2772 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
2773 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2774 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2775 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2776 {
2777 return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2778 }
2779
2780 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
2781
2782 #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
2783 #define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
2784 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
2785
2786 #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
2787
2788 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
2789 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2790 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2791 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2792 {
2793 return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
2794 }
2795
2796 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
2797 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2798 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2799 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2800 {
2801 return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
2802 }
2803 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2804
2805 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
2806
2807 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
2808 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2809 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2810 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2811 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2812 {
2813 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2814 }
2815 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2816 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2817 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2818 {
2819 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2820 }
2821
2822 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
2823 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2824 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
2825 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
2826 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2827 {
2828 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2829 }
2830 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
2831 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
2832 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2833 {
2834 return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2835 }
2836
2837 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
2838 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2839 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
2840 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
2841 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2842 {
2843 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2844 }
2845 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
2846 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
2847 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2848 {
2849 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2850 }
2851
2852 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
2853 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2854 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
2855 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
2856 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2857 {
2858 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2859 }
2860 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
2861 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
2862 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2863 {
2864 return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2865 }
2866
2867 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
2868 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2869 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2870 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2871 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2872 {
2873 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2874 }
2875 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2876 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2877 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2878 {
2879 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2880 }
2881
2882 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
2883 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2884 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2885 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2886 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2887 {
2888 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2889 }
2890 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2891 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2892 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2893 {
2894 return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2895 }
2896
2897 #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
2898 #define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2899 #define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2900 #define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2901
2902 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
2903
2904 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
2905
2906 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
2907 #define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff
2908 #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0
2909 static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
2910 {
2911 assert(!(val & 0x1f));
2912 return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
2913 }
2914
2915 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
2916
2917 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
2918
2919 #define REG_A5XX_RB_CNTL 0x0000e140
2920 #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
2921 #define A5XX_RB_CNTL_WIDTH__SHIFT 0
2922 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
2923 {
2924 assert(!(val & 0x1f));
2925 return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
2926 }
2927 #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
2928 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9
2929 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
2930 {
2931 assert(!(val & 0x1f));
2932 return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
2933 }
2934 #define A5XX_RB_CNTL_BYPASS 0x00020000
2935
2936 #define REG_A5XX_RB_RENDER_CNTL 0x0000e141
2937 #define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
2938 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
2939 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
2940 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
2941 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
2942 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
2943 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
2944 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
2945 {
2946 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
2947 }
2948 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
2949 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
2950 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
2951 {
2952 return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
2953 }
2954
2955 #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
2956 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2957 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2958 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2959 {
2960 return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
2961 }
2962
2963 #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
2964 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2965 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2966 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2967 {
2968 return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
2969 }
2970 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2971
2972 #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
2973 #define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
2974 #define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008
2975 #define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
2976 #define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
2977 #define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
2978 #define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
2979
2980 #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
2981 #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
2982
2983 #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
2984 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
2985 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
2986 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
2987 {
2988 return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
2989 }
2990 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
2991
2992 #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
2993 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
2994 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
2995 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
2996 {
2997 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
2998 }
2999 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
3000 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
3001 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3002 {
3003 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
3004 }
3005 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3006 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
3007 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3008 {
3009 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
3010 }
3011 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3012 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
3013 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3014 {
3015 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
3016 }
3017 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3018 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
3019 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3020 {
3021 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
3022 }
3023 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3024 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
3025 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3026 {
3027 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
3028 }
3029 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3030 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
3031 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3032 {
3033 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
3034 }
3035 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3036 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
3037 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3038 {
3039 return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
3040 }
3041
3042 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3043
3044 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3045 #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
3046 #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
3047 #define A5XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
3048 #define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
3049 #define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
3050 static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3051 {
3052 return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3053 }
3054 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3055 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
3056 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3057 {
3058 return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3059 }
3060
3061 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
3062 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3063 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
3064 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3065 {
3066 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3067 }
3068 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3069 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
3070 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3071 {
3072 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3073 }
3074 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3075 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
3076 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3077 {
3078 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3079 }
3080 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3081 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
3082 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3083 {
3084 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3085 }
3086 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3087 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
3088 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3089 {
3090 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3091 }
3092 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3093 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
3094 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3095 {
3096 return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3097 }
3098
3099 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
3100 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3101 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
3102 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3103 {
3104 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3105 }
3106 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3107 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
3108 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
3109 {
3110 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3111 }
3112 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3113 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
3114 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3115 {
3116 return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3117 }
3118 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
3119
3120 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
3121 #define A5XX_RB_MRT_PITCH__MASK 0xffffffff
3122 #define A5XX_RB_MRT_PITCH__SHIFT 0
3123 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
3124 {
3125 assert(!(val & 0x3f));
3126 return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
3127 }
3128
3129 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
3130 #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
3131 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
3132 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3133 {
3134 assert(!(val & 0x3f));
3135 return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
3136 }
3137
3138 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
3139
3140 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
3141
3142 #define REG_A5XX_RB_BLEND_RED 0x0000e1a0
3143 #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
3144 #define A5XX_RB_BLEND_RED_UINT__SHIFT 0
3145 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
3146 {
3147 return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
3148 }
3149 #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
3150 #define A5XX_RB_BLEND_RED_SINT__SHIFT 8
3151 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
3152 {
3153 return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
3154 }
3155 #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
3156 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
3157 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3158 {
3159 return ((util_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3160 }
3161
3162 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
3163 #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
3164 #define A5XX_RB_BLEND_RED_F32__SHIFT 0
3165 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
3166 {
3167 return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
3168 }
3169
3170 #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
3171 #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
3172 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
3173 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
3174 {
3175 return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
3176 }
3177 #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
3178 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
3179 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
3180 {
3181 return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
3182 }
3183 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
3184 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
3185 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3186 {
3187 return ((util_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3188 }
3189
3190 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
3191 #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3192 #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
3193 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
3194 {
3195 return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
3196 }
3197
3198 #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
3199 #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
3200 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
3201 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
3202 {
3203 return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
3204 }
3205 #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
3206 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
3207 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
3208 {
3209 return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
3210 }
3211 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
3212 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
3213 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3214 {
3215 return ((util_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3216 }
3217
3218 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
3219 #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3220 #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
3221 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
3222 {
3223 return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
3224 }
3225
3226 #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
3227 #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
3228 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
3229 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
3230 {
3231 return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
3232 }
3233 #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
3234 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
3235 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
3236 {
3237 return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
3238 }
3239 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
3240 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
3241 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3242 {
3243 return ((util_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3244 }
3245
3246 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
3247 #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3248 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
3249 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
3250 {
3251 return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
3252 }
3253
3254 #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
3255 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3256 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
3257 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3258 {
3259 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3260 }
3261 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3262 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3263 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
3264 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3265 {
3266 return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3267 }
3268
3269 #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
3270 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3271 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
3272 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3273 {
3274 return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3275 }
3276 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3277 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3278 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
3279 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3280 {
3281 return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3282 }
3283
3284 #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
3285 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
3286 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
3287
3288 #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
3289 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
3290 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3291 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3292 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
3293 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3294 {
3295 return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3296 }
3297 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
3298
3299 #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
3300 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
3301 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
3302 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
3303 {
3304 return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3305 }
3306
3307 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
3308
3309 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
3310
3311 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
3312 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
3313 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
3314 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3315 {
3316 assert(!(val & 0x3f));
3317 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
3318 }
3319
3320 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
3321 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3322 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
3323 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3324 {
3325 assert(!(val & 0x3f));
3326 return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3327 }
3328
3329 #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
3330 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
3331 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
3332 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
3333 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
3334 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
3335 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3336 {
3337 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
3338 }
3339 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
3340 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
3341 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3342 {
3343 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
3344 }
3345 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
3346 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
3347 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3348 {
3349 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3350 }
3351 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
3352 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
3353 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3354 {
3355 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3356 }
3357 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3358 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
3359 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3360 {
3361 return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3362 }
3363 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3364 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
3365 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3366 {
3367 return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3368 }
3369 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3370 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
3371 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3372 {
3373 return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3374 }
3375 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3376 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
3377 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3378 {
3379 return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3380 }
3381
3382 #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
3383 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3384
3385 #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
3386
3387 #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
3388
3389 #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
3390 #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
3391 #define A5XX_RB_STENCIL_PITCH__SHIFT 0
3392 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
3393 {
3394 assert(!(val & 0x3f));
3395 return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
3396 }
3397
3398 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
3399 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
3400 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
3401 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
3402 {
3403 assert(!(val & 0x3f));
3404 return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
3405 }
3406
3407 #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
3408 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
3409 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
3410 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
3411 {
3412 return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
3413 }
3414 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
3415 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
3416 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
3417 {
3418 return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
3419 }
3420 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
3421 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
3422 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
3423 {
3424 return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
3425 }
3426
3427 #define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7
3428 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
3429 #define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
3430 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
3431 {
3432 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
3433 }
3434 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
3435 #define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
3436 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
3437 {
3438 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
3439 }
3440 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
3441 #define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
3442 static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
3443 {
3444 return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
3445 }
3446
3447 #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
3448 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
3449 #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
3450 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
3451 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
3452 {
3453 return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
3454 }
3455 #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
3456 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
3457 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3458 {
3459 return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
3460 }
3461
3462 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1
3463 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3464
3465 #define REG_A5XX_RB_BLIT_CNTL 0x0000e210
3466 #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
3467 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
3468 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
3469 {
3470 return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
3471 }
3472
3473 #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
3474 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
3475 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
3476 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
3477 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
3478 {
3479 return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
3480 }
3481 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
3482 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
3483 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
3484 {
3485 return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
3486 }
3487
3488 #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
3489 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
3490 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
3491 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
3492 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
3493 {
3494 return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
3495 }
3496 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
3497 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
3498 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
3499 {
3500 return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
3501 }
3502
3503 #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
3504
3505 #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
3506
3507 #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
3508
3509 #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
3510 #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
3511 #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
3512 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
3513 {
3514 assert(!(val & 0x3f));
3515 return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
3516 }
3517
3518 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
3519 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
3520 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
3521 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3522 {
3523 assert(!(val & 0x3f));
3524 return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3525 }
3526
3527 #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
3528
3529 #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
3530
3531 #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
3532
3533 #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
3534
3535 #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
3536 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
3537 #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
3538 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
3539 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
3540 {
3541 return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
3542 }
3543
3544 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
3545
3546 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
3547
3548 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
3549
3550 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3551
3552 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3553
3554 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
3555
3556 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
3557 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
3558 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
3559 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
3560 {
3561 assert(!(val & 0x3f));
3562 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
3563 }
3564
3565 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
3566 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3567 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
3568 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
3569 {
3570 assert(!(val & 0x3f));
3571 return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
3572 }
3573
3574 #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
3575
3576 #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
3577
3578 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
3579 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
3580 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
3581 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
3582 {
3583 assert(!(val & 0x3f));
3584 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
3585 }
3586
3587 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
3588 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
3589 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
3590 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
3591 {
3592 assert(!(val & 0x3f));
3593 return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
3594 }
3595
3596 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
3597
3598 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268
3599
3600 #define REG_A5XX_VPC_CNTL_0 0x0000e280
3601 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
3602 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
3603 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
3604 {
3605 return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
3606 }
3607 #define A5XX_VPC_CNTL_0_VARYING 0x00000800
3608
3609 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3610
3611 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3612
3613 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3614
3615 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3616
3617 #define REG_A5XX_UNKNOWN_E292 0x0000e292
3618
3619 #define REG_A5XX_UNKNOWN_E293 0x0000e293
3620
3621 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3622
3623 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3624
3625 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
3626
3627 #define REG_A5XX_UNKNOWN_E29A 0x0000e29a
3628
3629 #define REG_A5XX_VPC_PACK 0x0000e29d
3630 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
3631 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
3632 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3633 {
3634 return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
3635 }
3636 #define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00
3637 #define A5XX_VPC_PACK_PSIZELOC__SHIFT 8
3638 static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
3639 {
3640 return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
3641 }
3642
3643 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
3644
3645 #define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
3646 #define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
3647 #define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
3648 #define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
3649 #define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
3650 #define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
3651
3652 #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
3653 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
3654
3655 #define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
3656 #define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
3657
3658 #define REG_A5XX_VPC_SO_PROG 0x0000e2a4
3659 #define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
3660 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
3661 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
3662 {
3663 return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
3664 }
3665 #define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
3666 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
3667 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
3668 {
3669 assert(!(val & 0x3));
3670 return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
3671 }
3672 #define A5XX_VPC_SO_PROG_A_EN 0x00000800
3673 #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
3674 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
3675 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
3676 {
3677 return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
3678 }
3679 #define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
3680 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
3681 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
3682 {
3683 assert(!(val & 0x3));
3684 return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
3685 }
3686 #define A5XX_VPC_SO_PROG_B_EN 0x00800000
3687
3688 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3689
3690 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3691
3692 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
3693
3694 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
3695
3696 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
3697
3698 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
3699
3700 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
3701
3702 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
3703
3704 #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
3705 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
3706 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
3707 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
3708 {
3709 return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
3710 }
3711 #define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100
3712 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
3713
3714 #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
3715 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
3716
3717 #define REG_A5XX_PC_RASTER_CNTL 0x0000e388
3718 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3719 #define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 0
3720 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3721 {
3722 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK;
3723 }
3724 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038
3725 #define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3
3726 static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3727 {
3728 return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
3729 }
3730 #define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
3731
3732 #define REG_A5XX_UNKNOWN_E389 0x0000e389
3733
3734 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
3735
3736 #define REG_A5XX_UNKNOWN_E38D 0x0000e38d
3737
3738 #define REG_A5XX_PC_GS_PARAM 0x0000e38e
3739
3740 #define REG_A5XX_PC_HS_PARAM 0x0000e38f
3741
3742 #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
3743
3744 #define REG_A5XX_VFD_CONTROL_0 0x0000e400
3745 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
3746 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
3747 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
3748 {
3749 return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
3750 }
3751
3752 #define REG_A5XX_VFD_CONTROL_1 0x0000e401
3753 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
3754 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
3755 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
3756 {
3757 return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
3758 }
3759 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
3760 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
3761 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
3762 {
3763 return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
3764 }
3765
3766 #define REG_A5XX_VFD_CONTROL_2 0x0000e402
3767
3768 #define REG_A5XX_VFD_CONTROL_3 0x0000e403
3769
3770 #define REG_A5XX_VFD_CONTROL_4 0x0000e404
3771
3772 #define REG_A5XX_VFD_CONTROL_5 0x0000e405
3773
3774 #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
3775
3776 #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
3777
3778 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
3779
3780 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
3781
3782 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
3783
3784 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
3785
3786 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
3787
3788 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
3789
3790 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
3791 #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
3792 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
3793 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
3794 {
3795 return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
3796 }
3797 #define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
3798 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
3799 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
3800 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
3801 {
3802 return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
3803 }
3804 #define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
3805 #define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
3806 static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3807 {
3808 return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
3809 }
3810 #define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
3811 #define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
3812
3813 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
3814
3815 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
3816
3817 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
3818 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
3819 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
3820 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
3821 {
3822 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
3823 }
3824 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
3825 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
3826 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
3827 {
3828 return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
3829 }
3830
3831 #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
3832
3833 #define REG_A5XX_SP_SP_CNTL 0x0000e580
3834
3835 #define REG_A5XX_SP_VS_CONFIG 0x0000e584
3836 #define A5XX_SP_VS_CONFIG_ENABLED 0x00000001
3837 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3838 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3839 static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3840 {
3841 return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
3842 }
3843 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3844 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3845 static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3846 {
3847 return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
3848 }
3849
3850 #define REG_A5XX_SP_FS_CONFIG 0x0000e585
3851 #define A5XX_SP_FS_CONFIG_ENABLED 0x00000001
3852 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3853 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3854 static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3855 {
3856 return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
3857 }
3858 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3859 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3860 static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3861 {
3862 return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
3863 }
3864
3865 #define REG_A5XX_SP_HS_CONFIG 0x0000e586
3866 #define A5XX_SP_HS_CONFIG_ENABLED 0x00000001
3867 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3868 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3869 static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3870 {
3871 return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
3872 }
3873 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3874 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3875 static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3876 {
3877 return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
3878 }
3879
3880 #define REG_A5XX_SP_DS_CONFIG 0x0000e587
3881 #define A5XX_SP_DS_CONFIG_ENABLED 0x00000001
3882 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3883 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3884 static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3885 {
3886 return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
3887 }
3888 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3889 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3890 static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3891 {
3892 return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
3893 }
3894
3895 #define REG_A5XX_SP_GS_CONFIG 0x0000e588
3896 #define A5XX_SP_GS_CONFIG_ENABLED 0x00000001
3897 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3898 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3899 static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3900 {
3901 return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
3902 }
3903 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3904 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3905 static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3906 {
3907 return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
3908 }
3909
3910 #define REG_A5XX_SP_CS_CONFIG 0x0000e589
3911 #define A5XX_SP_CS_CONFIG_ENABLED 0x00000001
3912 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3913 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3914 static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3915 {
3916 return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
3917 }
3918 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3919 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3920 static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
3921 {
3922 return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
3923 }
3924
3925 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
3926
3927 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
3928
3929 #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
3930 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008
3931 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3
3932 static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
3933 {
3934 return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
3935 }
3936 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3937 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3938 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
3939 {
3940 return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
3941 }
3942 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3943 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3944 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
3945 {
3946 return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
3947 }
3948 #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
3949 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
3950 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
3951 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
3952 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
3953 {
3954 return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
3955 }
3956
3957 #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
3958 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
3959 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
3960 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
3961 {
3962 return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
3963 }
3964
3965 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
3966
3967 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
3968 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
3969 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
3970 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
3971 {
3972 return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
3973 }
3974 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
3975 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
3976 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
3977 {
3978 return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
3979 }
3980 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
3981 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
3982 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
3983 {
3984 return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
3985 }
3986 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
3987 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
3988 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
3989 {
3990 return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
3991 }
3992
3993 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
3994
3995 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
3996 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
3997 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
3998 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
3999 {
4000 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
4001 }
4002 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
4003 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
4004 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
4005 {
4006 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
4007 }
4008 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
4009 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
4010 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
4011 {
4012 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
4013 }
4014 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
4015 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
4016 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
4017 {
4018 return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
4019 }
4020
4021 #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
4022
4023 #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
4024
4025 #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
4026
4027 #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
4028 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4029 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3
4030 static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4031 {
4032 return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
4033 }
4034 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4035 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4036 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4037 {
4038 return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4039 }
4040 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4041 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4042 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4043 {
4044 return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4045 }
4046 #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
4047 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
4048 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4049 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4050 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4051 {
4052 return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4053 }
4054
4055 #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
4056
4057 #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
4058
4059 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
4060
4061 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
4062 #define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
4063 #define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
4064
4065 #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
4066 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
4067 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
4068 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
4069 {
4070 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
4071 }
4072 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
4073 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
4074 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
4075 {
4076 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
4077 }
4078 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
4079 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
4080 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
4081 {
4082 return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
4083 }
4084
4085 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4086
4087 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4088 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
4089 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
4090 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4091 {
4092 return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
4093 }
4094 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
4095
4096 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4097
4098 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4099 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
4100 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
4101 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
4102 {
4103 return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4104 }
4105 #define A5XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
4106 #define A5XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
4107 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
4108
4109 #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
4110
4111 #define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
4112
4113 #define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
4114
4115 #define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
4116
4117 #define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
4118 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4119 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
4120 static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4121 {
4122 return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4123 }
4124 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4125 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4126 static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4127 {
4128 return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4129 }
4130 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4131 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4132 static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4133 {
4134 return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4135 }
4136 #define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000
4137 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000
4138 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4139 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4140 static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4141 {
4142 return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4143 }
4144
4145 #define REG_A5XX_UNKNOWN_E600 0x0000e600
4146
4147 #define REG_A5XX_UNKNOWN_E602 0x0000e602
4148
4149 #define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603
4150
4151 #define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
4152
4153 #define REG_A5XX_UNKNOWN_E62B 0x0000e62b
4154
4155 #define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
4156
4157 #define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
4158
4159 #define REG_A5XX_UNKNOWN_E640 0x0000e640
4160
4161 #define REG_A5XX_UNKNOWN_E65B 0x0000e65b
4162
4163 #define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c
4164
4165 #define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
4166
4167 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
4168 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
4169 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
4170 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4171 {
4172 return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4173 }
4174
4175 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
4176 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
4177 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
4178 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4179 {
4180 return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4181 }
4182 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
4183
4184 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
4185
4186 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
4187
4188 #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
4189
4190 #define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701
4191
4192 #define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702
4193
4194 #define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703
4195
4196 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
4197
4198 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
4199
4200 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724
4201
4202 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725
4203
4204 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726
4205
4206 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727
4207
4208 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728
4209
4210 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729
4211
4212 #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
4213
4214 #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
4215
4216 #define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c
4217
4218 #define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d
4219
4220 #define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e
4221
4222 #define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f
4223
4224 #define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730
4225
4226 #define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731
4227
4228 #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
4229
4230 #define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751
4231
4232 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
4233
4234 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
4235
4236 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
4237
4238 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d
4239
4240 #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
4241
4242 #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
4243
4244 #define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
4245
4246 #define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761
4247
4248 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
4249
4250 #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
4251 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001
4252 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0
4253 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
4254 {
4255 return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
4256 }
4257 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004
4258 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2
4259 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
4260 {
4261 return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
4262 }
4263
4264 #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
4265 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
4266 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
4267 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
4268 {
4269 return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
4270 }
4271
4272 #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
4273 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
4274 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
4275 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4276 {
4277 return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4278 }
4279
4280 #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
4281 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
4282 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
4283 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
4284 {
4285 return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
4286 }
4287
4288 #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
4289 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
4290 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
4291 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4292 {
4293 return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4294 }
4295 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
4296 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
4297 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4298 {
4299 return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4300 }
4301
4302 #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
4303
4304 #define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b
4305 #define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001
4306 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4307 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4308 static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4309 {
4310 return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4311 }
4312 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4313 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4314 static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4315 {
4316 return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
4317 }
4318
4319 #define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c
4320 #define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001
4321 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4322 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4323 static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4324 {
4325 return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4326 }
4327 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4328 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4329 static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4330 {
4331 return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
4332 }
4333
4334 #define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d
4335 #define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001
4336 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4337 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4338 static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4339 {
4340 return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4341 }
4342 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4343 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4344 static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4345 {
4346 return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
4347 }
4348
4349 #define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e
4350 #define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001
4351 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4352 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4353 static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4354 {
4355 return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4356 }
4357 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4358 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4359 static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4360 {
4361 return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
4362 }
4363
4364 #define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f
4365 #define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001
4366 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4367 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4368 static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4369 {
4370 return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4371 }
4372 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4373 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4374 static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4375 {
4376 return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
4377 }
4378
4379 #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
4380 #define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001
4381 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4382 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4383 static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4384 {
4385 return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4386 }
4387 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4388 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4389 static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4390 {
4391 return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
4392 }
4393
4394 #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
4395 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001
4396 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
4397 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
4398 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
4399 {
4400 return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
4401 }
4402
4403 #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
4404 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001
4405 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
4406 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
4407 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
4408 {
4409 return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
4410 }
4411
4412 #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
4413 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001
4414 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
4415 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
4416 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
4417 {
4418 return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
4419 }
4420
4421 #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
4422 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001
4423 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
4424 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
4425 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
4426 {
4427 return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
4428 }
4429
4430 #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
4431 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001
4432 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
4433 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
4434 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
4435 {
4436 return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
4437 }
4438
4439 #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
4440 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001
4441 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
4442 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
4443 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
4444 {
4445 return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
4446 }
4447
4448 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
4449
4450 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
4451
4452 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
4453
4454 #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
4455 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
4456 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
4457 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4458 {
4459 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4460 }
4461 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
4462 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
4463 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4464 {
4465 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4466 }
4467 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
4468 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
4469 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4470 {
4471 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4472 }
4473 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
4474 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
4475 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4476 {
4477 return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4478 }
4479
4480 #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
4481 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK 0xffffffff
4482 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT 0
4483 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(uint32_t val)
4484 {
4485 return ((val) << A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK;
4486 }
4487
4488 #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
4489
4490 #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
4491 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK 0xffffffff
4492 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT 0
4493 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(uint32_t val)
4494 {
4495 return ((val) << A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK;
4496 }
4497
4498 #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
4499
4500 #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
4501 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK 0xffffffff
4502 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT 0
4503 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(uint32_t val)
4504 {
4505 return ((val) << A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK;
4506 }
4507
4508 #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
4509
4510 #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
4511 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
4512 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
4513 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
4514 {
4515 return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
4516 }
4517 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
4518 #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
4519 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
4520 {
4521 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
4522 }
4523 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
4524 #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
4525 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
4526 {
4527 return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
4528 }
4529 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
4530 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
4531 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
4532 {
4533 return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
4534 }
4535
4536 #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
4537
4538 #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
4539
4540 #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
4541
4542 #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
4543
4544 #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
4545
4546 #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
4547
4548 #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
4549
4550 #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
4551
4552 #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
4553
4554 #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
4555
4556 #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
4557
4558 #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
4559
4560 #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
4561
4562 #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
4563
4564 #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
4565
4566 #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
4567
4568 #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
4569
4570 #define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc
4571
4572 #define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
4573
4574 #define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
4575
4576 #define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
4577
4578 #define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
4579
4580 #define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
4581
4582 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107
4583 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
4584 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
4585 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4586 {
4587 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
4588 }
4589 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
4590 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
4591 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4592 {
4593 return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
4594 }
4595
4596 #define REG_A5XX_RB_2D_SRC_LO 0x00002108
4597
4598 #define REG_A5XX_RB_2D_SRC_HI 0x00002109
4599
4600 #define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
4601 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
4602 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
4603 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
4604 {
4605 assert(!(val & 0x3f));
4606 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
4607 }
4608 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
4609 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
4610 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
4611 {
4612 assert(!(val & 0x3f));
4613 return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
4614 }
4615
4616 #define REG_A5XX_RB_2D_DST_INFO 0x00002110
4617 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
4618 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
4619 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4620 {
4621 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
4622 }
4623 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
4624 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
4625 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4626 {
4627 return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
4628 }
4629
4630 #define REG_A5XX_RB_2D_DST_LO 0x00002111
4631
4632 #define REG_A5XX_RB_2D_DST_HI 0x00002112
4633
4634 #define REG_A5XX_RB_2D_DST_SIZE 0x00002113
4635 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
4636 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
4637 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
4638 {
4639 assert(!(val & 0x3f));
4640 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
4641 }
4642 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
4643 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
4644 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
4645 {
4646 assert(!(val & 0x3f));
4647 return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
4648 }
4649
4650 #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
4651
4652 #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
4653
4654 #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
4655
4656 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
4657
4658 #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
4659 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
4660 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
4661 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4662 {
4663 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
4664 }
4665 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
4666 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
4667 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4668 {
4669 return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
4670 }
4671
4672 #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
4673 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
4674 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
4675 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
4676 {
4677 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
4678 }
4679 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
4680 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
4681 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
4682 {
4683 return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
4684 }
4685
4686 #define REG_A5XX_UNKNOWN_2100 0x00002100
4687
4688 #define REG_A5XX_UNKNOWN_2180 0x00002180
4689
4690 #define REG_A5XX_UNKNOWN_2184 0x00002184
4691
4692 #define REG_A5XX_TEX_SAMP_0 0x00000000
4693 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
4694 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
4695 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
4696 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
4697 {
4698 return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
4699 }
4700 #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
4701 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
4702 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
4703 {
4704 return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
4705 }
4706 #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
4707 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
4708 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
4709 {
4710 return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
4711 }
4712 #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
4713 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
4714 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
4715 {
4716 return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
4717 }
4718 #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
4719 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
4720 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
4721 {
4722 return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
4723 }
4724 #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
4725 #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
4726 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
4727 {
4728 return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
4729 }
4730 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
4731 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
4732 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
4733 {
4734 return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
4735 }
4736
4737 #define REG_A5XX_TEX_SAMP_1 0x00000001
4738 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
4739 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
4740 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
4741 {
4742 return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
4743 }
4744 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
4745 #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
4746 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
4747 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
4748 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
4749 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
4750 {
4751 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
4752 }
4753 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
4754 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
4755 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
4756 {
4757 return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
4758 }
4759
4760 #define REG_A5XX_TEX_SAMP_2 0x00000002
4761 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
4762 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
4763 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
4764 {
4765 return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
4766 }
4767
4768 #define REG_A5XX_TEX_SAMP_3 0x00000003
4769
4770 #define REG_A5XX_TEX_CONST_0 0x00000000
4771 #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
4772 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
4773 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
4774 {
4775 return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
4776 }
4777 #define A5XX_TEX_CONST_0_SRGB 0x00000004
4778 #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
4779 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
4780 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
4781 {
4782 return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
4783 }
4784 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
4785 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
4786 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
4787 {
4788 return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
4789 }
4790 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
4791 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
4792 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
4793 {
4794 return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
4795 }
4796 #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
4797 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
4798 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
4799 {
4800 return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
4801 }
4802 #define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
4803 #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16
4804 static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
4805 {
4806 return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
4807 }
4808 #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
4809 #define A5XX_TEX_CONST_0_FMT__SHIFT 22
4810 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
4811 {
4812 return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
4813 }
4814 #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
4815 #define A5XX_TEX_CONST_0_SWAP__SHIFT 30
4816 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
4817 {
4818 return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
4819 }
4820
4821 #define REG_A5XX_TEX_CONST_1 0x00000001
4822 #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
4823 #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
4824 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
4825 {
4826 return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
4827 }
4828 #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
4829 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
4830 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
4831 {
4832 return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
4833 }
4834
4835 #define REG_A5XX_TEX_CONST_2 0x00000002
4836 #define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
4837 #define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
4838 static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val)
4839 {
4840 return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK;
4841 }
4842 #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
4843 #define A5XX_TEX_CONST_2_PITCH__SHIFT 7
4844 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
4845 {
4846 return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
4847 }
4848 #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
4849 #define A5XX_TEX_CONST_2_TYPE__SHIFT 29
4850 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
4851 {
4852 return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
4853 }
4854
4855 #define REG_A5XX_TEX_CONST_3 0x00000003
4856 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
4857 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
4858 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
4859 {
4860 assert(!(val & 0xfff));
4861 return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
4862 }
4863 #define A5XX_TEX_CONST_3_FLAG 0x10000000
4864
4865 #define REG_A5XX_TEX_CONST_4 0x00000004
4866 #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
4867 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
4868 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
4869 {
4870 assert(!(val & 0x1f));
4871 return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
4872 }
4873
4874 #define REG_A5XX_TEX_CONST_5 0x00000005
4875 #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
4876 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
4877 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
4878 {
4879 return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
4880 }
4881 #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
4882 #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
4883 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
4884 {
4885 return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
4886 }
4887
4888 #define REG_A5XX_TEX_CONST_6 0x00000006
4889
4890 #define REG_A5XX_TEX_CONST_7 0x00000007
4891
4892 #define REG_A5XX_TEX_CONST_8 0x00000008
4893
4894 #define REG_A5XX_TEX_CONST_9 0x00000009
4895
4896 #define REG_A5XX_TEX_CONST_10 0x0000000a
4897
4898 #define REG_A5XX_TEX_CONST_11 0x0000000b
4899
4900 #define REG_A5XX_SSBO_0_0 0x00000000
4901 #define A5XX_SSBO_0_0_BASE_LO__MASK 0xffffffe0
4902 #define A5XX_SSBO_0_0_BASE_LO__SHIFT 5
4903 static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
4904 {
4905 assert(!(val & 0x1f));
4906 return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
4907 }
4908
4909 #define REG_A5XX_SSBO_0_1 0x00000001
4910 #define A5XX_SSBO_0_1_PITCH__MASK 0x003fffff
4911 #define A5XX_SSBO_0_1_PITCH__SHIFT 0
4912 static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val)
4913 {
4914 return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK;
4915 }
4916
4917 #define REG_A5XX_SSBO_0_2 0x00000002
4918 #define A5XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
4919 #define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
4920 static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
4921 {
4922 assert(!(val & 0xfff));
4923 return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
4924 }
4925
4926 #define REG_A5XX_SSBO_0_3 0x00000003
4927 #define A5XX_SSBO_0_3_CPP__MASK 0x0000003f
4928 #define A5XX_SSBO_0_3_CPP__SHIFT 0
4929 static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val)
4930 {
4931 return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK;
4932 }
4933
4934 #define REG_A5XX_SSBO_1_0 0x00000000
4935 #define A5XX_SSBO_1_0_FMT__MASK 0x0000ff00
4936 #define A5XX_SSBO_1_0_FMT__SHIFT 8
4937 static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)
4938 {
4939 return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK;
4940 }
4941 #define A5XX_SSBO_1_0_WIDTH__MASK 0xffff0000
4942 #define A5XX_SSBO_1_0_WIDTH__SHIFT 16
4943 static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val)
4944 {
4945 return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK;
4946 }
4947
4948 #define REG_A5XX_SSBO_1_1 0x00000001
4949 #define A5XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
4950 #define A5XX_SSBO_1_1_HEIGHT__SHIFT 0
4951 static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val)
4952 {
4953 return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK;
4954 }
4955 #define A5XX_SSBO_1_1_DEPTH__MASK 0xffff0000
4956 #define A5XX_SSBO_1_1_DEPTH__SHIFT 16
4957 static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val)
4958 {
4959 return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK;
4960 }
4961
4962 #define REG_A5XX_SSBO_2_0 0x00000000
4963 #define A5XX_SSBO_2_0_BASE_LO__MASK 0xffffffff
4964 #define A5XX_SSBO_2_0_BASE_LO__SHIFT 0
4965 static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val)
4966 {
4967 return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK;
4968 }
4969
4970 #define REG_A5XX_SSBO_2_1 0x00000001
4971 #define A5XX_SSBO_2_1_BASE_HI__MASK 0xffffffff
4972 #define A5XX_SSBO_2_1_BASE_HI__SHIFT 0
4973 static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
4974 {
4975 return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
4976 }
4977
4978
4979 #endif /* A5XX_XML */