4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31541 bytes, from 2017-05-17 13:21:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110757 bytes, from 2017-05-17 13:21:27)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 105446 bytes, from 2017-05-17 20:33:08)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
21 Copyright (C) 2013-2017 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
53 RB5_R4G4B4A4_UNORM
= 8,
54 RB5_R5G5B5A1_UNORM
= 10,
55 RB5_R5G6B5_UNORM
= 14,
65 RB5_R8G8B8A8_UNORM
= 48,
66 RB5_R8G8B8_UNORM
= 49,
67 RB5_R8G8B8A8_SNORM
= 50,
68 RB5_R8G8B8A8_UINT
= 51,
69 RB5_R8G8B8A8_SINT
= 52,
70 RB5_R10G10B10A2_UNORM
= 55,
71 RB5_R10G10B10A2_UINT
= 58,
72 RB5_R11G11B10_FLOAT
= 66,
73 RB5_R16G16_UNORM
= 67,
74 RB5_R16G16_SNORM
= 68,
75 RB5_R16G16_FLOAT
= 69,
81 RB5_R16G16B16A16_UNORM
= 96,
82 RB5_R16G16B16A16_SNORM
= 97,
83 RB5_R16G16B16A16_FLOAT
= 98,
84 RB5_R16G16B16A16_UINT
= 99,
85 RB5_R16G16B16A16_SINT
= 100,
86 RB5_R32G32_FLOAT
= 103,
87 RB5_R32G32_UINT
= 104,
88 RB5_R32G32_SINT
= 105,
89 RB5_R32G32B32A32_FLOAT
= 130,
90 RB5_R32G32B32A32_UINT
= 131,
91 RB5_R32G32B32A32_SINT
= 132,
105 VFMT5_8_8_UNORM
= 15,
106 VFMT5_8_8_SNORM
= 16,
114 VFMT5_8_8_8_UNORM
= 33,
115 VFMT5_8_8_8_SNORM
= 34,
116 VFMT5_8_8_8_UINT
= 35,
117 VFMT5_8_8_8_SINT
= 36,
118 VFMT5_8_8_8_8_UNORM
= 48,
119 VFMT5_8_8_8_8_SNORM
= 50,
120 VFMT5_8_8_8_8_UINT
= 51,
121 VFMT5_8_8_8_8_SINT
= 52,
122 VFMT5_16_16_UNORM
= 67,
123 VFMT5_16_16_SNORM
= 68,
124 VFMT5_16_16_FLOAT
= 69,
125 VFMT5_16_16_UINT
= 70,
126 VFMT5_16_16_SINT
= 71,
133 VFMT5_16_16_16_UNORM
= 88,
134 VFMT5_16_16_16_SNORM
= 89,
135 VFMT5_16_16_16_FLOAT
= 90,
136 VFMT5_16_16_16_UINT
= 91,
137 VFMT5_16_16_16_SINT
= 92,
138 VFMT5_16_16_16_16_UNORM
= 96,
139 VFMT5_16_16_16_16_SNORM
= 97,
140 VFMT5_16_16_16_16_FLOAT
= 98,
141 VFMT5_16_16_16_16_UINT
= 99,
142 VFMT5_16_16_16_16_SINT
= 100,
143 VFMT5_32_32_UNORM
= 101,
144 VFMT5_32_32_SNORM
= 102,
145 VFMT5_32_32_FLOAT
= 103,
146 VFMT5_32_32_UINT
= 104,
147 VFMT5_32_32_SINT
= 105,
148 VFMT5_32_32_FIXED
= 106,
149 VFMT5_32_32_32_UNORM
= 112,
150 VFMT5_32_32_32_SNORM
= 113,
151 VFMT5_32_32_32_UINT
= 114,
152 VFMT5_32_32_32_SINT
= 115,
153 VFMT5_32_32_32_FLOAT
= 116,
154 VFMT5_32_32_32_FIXED
= 117,
155 VFMT5_32_32_32_32_UNORM
= 128,
156 VFMT5_32_32_32_32_SNORM
= 129,
157 VFMT5_32_32_32_32_FLOAT
= 130,
158 VFMT5_32_32_32_32_UINT
= 131,
159 VFMT5_32_32_32_32_SINT
= 132,
160 VFMT5_32_32_32_32_FIXED
= 133,
169 TFMT5_4_4_4_4_UNORM
= 8,
170 TFMT5_5_5_5_1_UNORM
= 10,
171 TFMT5_5_6_5_UNORM
= 14,
172 TFMT5_8_8_UNORM
= 15,
173 TFMT5_8_8_SNORM
= 16,
176 TFMT5_L8_A8_UNORM
= 19,
182 TFMT5_8_8_8_8_UNORM
= 48,
183 TFMT5_8_8_8_UNORM
= 49,
184 TFMT5_8_8_8_8_SNORM
= 50,
185 TFMT5_8_8_8_8_UINT
= 51,
186 TFMT5_8_8_8_8_SINT
= 52,
187 TFMT5_9_9_9_E5_FLOAT
= 53,
188 TFMT5_10_10_10_2_UNORM
= 54,
189 TFMT5_10_10_10_2_UINT
= 58,
190 TFMT5_11_11_10_FLOAT
= 66,
191 TFMT5_16_16_UNORM
= 67,
192 TFMT5_16_16_SNORM
= 68,
193 TFMT5_16_16_FLOAT
= 69,
194 TFMT5_16_16_UINT
= 70,
195 TFMT5_16_16_SINT
= 71,
199 TFMT5_16_16_16_16_UNORM
= 96,
200 TFMT5_16_16_16_16_SNORM
= 97,
201 TFMT5_16_16_16_16_FLOAT
= 98,
202 TFMT5_16_16_16_16_UINT
= 99,
203 TFMT5_16_16_16_16_SINT
= 100,
204 TFMT5_32_32_FLOAT
= 103,
205 TFMT5_32_32_UINT
= 104,
206 TFMT5_32_32_SINT
= 105,
207 TFMT5_32_32_32_32_FLOAT
= 130,
208 TFMT5_32_32_32_32_UINT
= 131,
209 TFMT5_32_32_32_32_SINT
= 132,
210 TFMT5_X8Z24_UNORM
= 160,
211 TFMT5_RGTC1_UNORM
= 183,
212 TFMT5_RGTC1_SNORM
= 184,
213 TFMT5_RGTC2_UNORM
= 187,
214 TFMT5_RGTC2_SNORM
= 188,
217 enum a5xx_tex_fetchsize
{
225 enum a5xx_depth_format
{
245 enum a5xx_tex_filter
{
246 A5XX_TEX_NEAREST
= 0,
251 enum a5xx_tex_clamp
{
253 A5XX_TEX_CLAMP_TO_EDGE
= 1,
254 A5XX_TEX_MIRROR_REPEAT
= 2,
255 A5XX_TEX_CLAMP_TO_BORDER
= 3,
256 A5XX_TEX_MIRROR_CLAMP
= 4,
259 enum a5xx_tex_aniso
{
260 A5XX_TEX_ANISO_1
= 0,
261 A5XX_TEX_ANISO_2
= 1,
262 A5XX_TEX_ANISO_4
= 2,
263 A5XX_TEX_ANISO_8
= 3,
264 A5XX_TEX_ANISO_16
= 4,
283 #define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
284 #define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
285 #define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
286 #define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
287 #define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
288 #define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
289 #define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
290 #define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
291 #define A5XX_INT0_CP_SW 0x00000100
292 #define A5XX_INT0_CP_HW_ERROR 0x00000200
293 #define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
294 #define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
295 #define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
296 #define A5XX_INT0_CP_IB2 0x00002000
297 #define A5XX_INT0_CP_IB1 0x00004000
298 #define A5XX_INT0_CP_RB 0x00008000
299 #define A5XX_INT0_CP_UNUSED_1 0x00010000
300 #define A5XX_INT0_CP_RB_DONE_TS 0x00020000
301 #define A5XX_INT0_CP_WT_DONE_TS 0x00040000
302 #define A5XX_INT0_UNKNOWN_1 0x00080000
303 #define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
304 #define A5XX_INT0_UNUSED_2 0x00200000
305 #define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
306 #define A5XX_INT0_MISC_HANG_DETECT 0x00800000
307 #define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
308 #define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
309 #define A5XX_INT0_DEBBUS_INTR_0 0x04000000
310 #define A5XX_INT0_DEBBUS_INTR_1 0x08000000
311 #define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
312 #define A5XX_INT0_GPMU_FIRMWARE 0x20000000
313 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
314 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
315 #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
316 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
317 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
318 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
319 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
320 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
321 #define REG_A5XX_CP_RB_BASE 0x00000800
323 #define REG_A5XX_CP_RB_BASE_HI 0x00000801
325 #define REG_A5XX_CP_RB_CNTL 0x00000802
327 #define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
329 #define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
331 #define REG_A5XX_CP_RB_RPTR 0x00000806
333 #define REG_A5XX_CP_RB_WPTR 0x00000807
335 #define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
337 #define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
339 #define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
341 #define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
343 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
345 #define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
347 #define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
349 #define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
351 #define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
353 #define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
355 #define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
357 #define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
359 #define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
361 #define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
363 #define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
365 #define REG_A5XX_CP_MERCIU_SIZE 0x00000826
367 #define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
369 #define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
371 #define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
373 #define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
375 #define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
377 #define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
379 #define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
381 #define REG_A5XX_CP_CNTL 0x00000831
383 #define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
385 #define REG_A5XX_CP_CHICKEN_DBG 0x00000833
387 #define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
389 #define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
391 #define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
393 #define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
395 #define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
397 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
399 #define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
401 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
403 #define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
405 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
407 #define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
409 #define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
411 #define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
413 #define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
415 #define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
417 #define REG_A5XX_CP_HW_FAULT 0x00000b1a
419 #define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
421 #define REG_A5XX_CP_IB1_BASE 0x00000b1f
423 #define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
425 #define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
427 #define REG_A5XX_CP_IB2_BASE 0x00000b22
429 #define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
431 #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
433 static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0
) { return 0x00000b78 + 0x1*i0
; }
435 static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0
) { return 0x00000b78 + 0x1*i0
; }
437 static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0
) { return 0x00000880 + 0x1*i0
; }
439 static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0
) { return 0x00000880 + 0x1*i0
; }
440 #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
441 #define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
442 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val
)
444 return ((val
) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT
) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK
;
446 #define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
447 #define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
448 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val
)
450 return ((val
) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT
) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK
;
452 #define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
453 #define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
455 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
457 #define REG_A5XX_CP_AHB_FAULT 0x00000b1b
459 #define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
461 #define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
463 #define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
465 #define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
467 #define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
469 #define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
471 #define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
473 #define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
475 #define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
477 #define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
479 #define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
481 #define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
483 #define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
485 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
487 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
489 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
491 #define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
493 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
495 #define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
497 #define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
499 #define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
501 #define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
503 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
505 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
507 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
509 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
511 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
513 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
515 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
517 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
519 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
521 #define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
523 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
525 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
527 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
529 #define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
531 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
533 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
535 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
537 #define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
539 #define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
541 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
543 #define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
545 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
547 #define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
549 #define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
551 #define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
553 #define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
555 #define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
557 #define REG_A5XX_RBBM_INT_0_MASK 0x00000038
558 #define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
559 #define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
560 #define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
561 #define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
562 #define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
563 #define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
564 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
565 #define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
566 #define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
567 #define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
568 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
569 #define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
570 #define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
571 #define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
572 #define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
573 #define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
574 #define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
575 #define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
576 #define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
577 #define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
578 #define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
579 #define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
580 #define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
581 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
582 #define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
583 #define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
584 #define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
585 #define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
586 #define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
588 #define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
590 #define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
592 #define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
594 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
596 #define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
598 #define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
600 #define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
602 #define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
604 #define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
606 #define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
608 #define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
610 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
612 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
614 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
616 #define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
618 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
620 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
622 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
624 #define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
626 #define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
628 #define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
630 #define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
632 #define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
634 #define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
636 #define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
638 #define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
640 #define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
642 #define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
644 #define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
646 #define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
648 #define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
650 #define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
652 #define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
654 #define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
656 #define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
658 #define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
660 #define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
662 #define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
664 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
666 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
668 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
670 #define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
672 #define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
674 #define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
676 #define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
678 #define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
680 #define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
682 #define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
684 #define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
686 #define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
688 #define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
690 #define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
692 #define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
694 #define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
696 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
698 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
700 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
702 #define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
704 #define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
706 #define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
708 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
710 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
712 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
714 #define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
716 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
718 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
720 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
722 #define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
724 #define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
726 #define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
728 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
730 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
732 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
734 #define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
736 #define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
738 #define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
740 #define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
742 #define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
744 #define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
746 #define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
748 #define REG_A5XX_RBBM_AHB_CMD 0x00000096
750 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
752 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
754 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
756 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
758 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
760 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
762 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
764 #define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
766 #define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
768 #define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
770 #define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
772 #define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
774 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
776 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
778 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
780 #define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
782 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
784 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
786 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
788 #define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
790 #define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
792 #define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
794 #define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
796 #define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
798 #define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
800 #define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
802 #define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
804 #define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
806 #define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
808 #define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
810 #define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
812 #define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
814 #define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
816 #define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
818 #define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
820 #define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
822 #define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
824 #define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
826 #define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
828 #define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
830 #define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
832 #define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
834 #define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
836 #define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
838 #define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
840 #define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
842 #define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
844 #define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
846 #define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
848 #define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
850 #define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
852 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
854 #define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
856 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
858 #define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
860 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
862 #define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
864 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
866 #define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
868 #define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
870 #define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
872 #define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
874 #define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
876 #define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
878 #define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
880 #define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
882 #define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
884 #define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
886 #define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
888 #define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
890 #define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
892 #define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
894 #define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
896 #define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
898 #define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
900 #define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
902 #define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
904 #define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
906 #define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
908 #define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
910 #define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
912 #define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
914 #define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
916 #define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
918 #define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
920 #define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
922 #define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
924 #define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
926 #define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
928 #define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
930 #define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
932 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
934 #define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
936 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
938 #define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
940 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
942 #define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
944 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
946 #define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
948 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
950 #define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
952 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
954 #define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
956 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
958 #define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
960 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
962 #define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
964 #define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
966 #define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
968 #define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
970 #define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
972 #define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
974 #define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
976 #define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
978 #define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
980 #define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
982 #define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
984 #define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
986 #define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
988 #define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
990 #define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
992 #define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
994 #define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
996 #define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
998 #define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
1000 #define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
1002 #define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
1004 #define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
1006 #define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
1008 #define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
1010 #define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
1012 #define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
1014 #define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
1016 #define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
1018 #define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
1020 #define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
1022 #define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
1024 #define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
1026 #define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
1028 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
1030 #define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
1032 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
1034 #define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
1036 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
1038 #define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
1040 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
1042 #define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
1044 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
1046 #define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
1048 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
1050 #define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
1052 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
1054 #define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
1056 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
1058 #define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
1060 #define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
1062 #define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
1064 #define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
1066 #define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
1068 #define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
1070 #define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
1072 #define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
1074 #define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
1076 #define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
1078 #define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
1080 #define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
1082 #define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
1084 #define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
1086 #define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
1088 #define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
1090 #define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
1092 #define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
1094 #define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
1096 #define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
1098 #define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
1100 #define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
1102 #define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
1104 #define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
1106 #define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
1108 #define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
1110 #define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
1112 #define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
1114 #define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
1116 #define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
1118 #define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
1120 #define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
1122 #define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
1124 #define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
1126 #define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
1128 #define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
1130 #define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
1132 #define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
1134 #define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
1136 #define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
1138 #define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
1140 #define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
1142 #define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
1144 #define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
1146 #define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
1148 #define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
1150 #define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
1152 #define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
1154 #define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
1156 #define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
1158 #define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
1160 #define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
1162 #define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
1164 #define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
1166 #define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
1168 #define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
1170 #define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
1172 #define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
1174 #define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
1176 #define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
1178 #define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
1180 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
1182 #define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
1184 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
1186 #define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
1188 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
1190 #define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
1192 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
1194 #define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
1196 #define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
1198 #define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
1200 #define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
1202 #define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
1204 #define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
1206 #define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
1208 #define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
1210 #define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
1212 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1214 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1216 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1218 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1220 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
1222 #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
1224 #define REG_A5XX_RBBM_STATUS 0x000004f5
1225 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
1226 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
1227 #define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1228 #define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
1229 #define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
1230 #define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
1231 #define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
1232 #define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
1233 #define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
1234 #define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
1235 #define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
1236 #define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1237 #define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1238 #define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
1239 #define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
1240 #define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
1241 #define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
1242 #define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
1243 #define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
1244 #define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
1245 #define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
1246 #define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
1247 #define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
1248 #define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
1249 #define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
1250 #define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
1251 #define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
1252 #define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
1253 #define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
1254 #define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1255 #define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1256 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
1258 #define REG_A5XX_RBBM_STATUS3 0x00000530
1260 #define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
1262 #define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
1264 #define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
1266 #define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
1268 #define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
1270 #define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
1272 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
1274 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
1276 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
1278 #define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
1280 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
1282 #define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
1284 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1286 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1288 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1290 #define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1292 #define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
1294 #define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
1296 #define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
1298 #define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
1300 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
1302 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
1304 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
1306 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
1308 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
1310 #define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
1312 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
1314 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
1316 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
1318 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
1320 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
1322 #define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
1324 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
1326 #define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
1328 #define REG_A5XX_RBBM_ISDB_CNT 0x00000533
1330 #define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
1332 #define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1334 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1336 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1338 #define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1340 #define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1342 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
1344 #define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
1346 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
1348 #define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
1350 #define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1352 #define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
1353 #define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
1354 #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1355 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val
)
1357 assert(!(val
& 0x1f));
1358 return ((val
>> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT
) & A5XX_VSC_BIN_SIZE_WIDTH__MASK
;
1360 #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
1361 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
1362 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val
)
1364 assert(!(val
& 0x1f));
1365 return ((val
>> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT
) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK
;
1368 #define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
1370 #define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
1372 #define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
1374 #define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
1376 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0
) { return 0x00000bd0 + 0x1*i0
; }
1378 static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0
) { return 0x00000bd0 + 0x1*i0
; }
1379 #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1380 #define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1381 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val
)
1383 return ((val
) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT
) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK
;
1385 #define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1386 #define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1387 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val
)
1389 return ((val
) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT
) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK
;
1391 #define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1392 #define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1393 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val
)
1395 return ((val
) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT
) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK
;
1397 #define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1398 #define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
1399 static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val
)
1401 return ((val
) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT
) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK
;
1404 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0
) { return 0x00000be0 + 0x2*i0
; }
1406 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0
) { return 0x00000be0 + 0x2*i0
; }
1408 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0
) { return 0x00000be1 + 0x2*i0
; }
1410 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0
) { return 0x00000c00 + 0x1*i0
; }
1412 static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0
) { return 0x00000c00 + 0x1*i0
; }
1414 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
1416 #define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
1418 #define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
1419 #define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
1420 #define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
1421 #define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
1422 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val
)
1424 return ((val
) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT
) & A5XX_VSC_RESOLVE_CNTL_X__MASK
;
1426 #define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
1427 #define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
1428 static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val
)
1430 return ((val
) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT
) & A5XX_VSC_RESOLVE_CNTL_Y__MASK
;
1433 #define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
1435 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
1437 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
1439 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
1441 #define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
1443 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
1445 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
1447 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
1449 #define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
1451 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
1453 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
1455 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
1457 #define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
1459 #define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
1461 #define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
1463 #define REG_A5XX_RB_MODE_CNTL 0x00000cc6
1465 #define REG_A5XX_RB_CCU_CNTL 0x00000cc7
1467 #define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
1469 #define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
1471 #define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
1473 #define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
1475 #define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
1477 #define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
1479 #define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
1481 #define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
1483 #define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
1485 #define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
1487 #define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
1489 #define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
1491 #define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
1493 #define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
1495 #define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
1497 #define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
1499 #define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
1501 #define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
1503 #define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
1505 #define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
1507 #define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
1509 #define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
1511 #define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
1512 #define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
1514 #define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
1516 #define REG_A5XX_PC_MODE_CNTL 0x00000d02
1518 #define REG_A5XX_UNKNOWN_0D08 0x00000d08
1520 #define REG_A5XX_UNKNOWN_0D09 0x00000d09
1522 #define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
1524 #define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
1526 #define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
1528 #define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
1530 #define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
1532 #define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
1534 #define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
1536 #define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
1538 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
1540 #define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
1542 #define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
1544 #define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
1546 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
1548 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
1550 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
1552 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
1554 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
1556 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
1558 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
1560 #define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
1562 #define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
1564 #define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
1566 #define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
1568 #define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
1570 #define REG_A5XX_VFD_MODE_CNTL 0x00000e42
1572 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
1574 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
1576 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
1578 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
1580 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
1582 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
1584 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
1586 #define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
1588 #define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
1590 #define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
1592 #define REG_A5XX_VPC_MODE_CNTL 0x00000e62
1593 #define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
1595 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
1597 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
1599 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
1601 #define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
1603 #define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
1605 #define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
1607 #define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
1609 #define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
1611 #define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
1613 #define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
1615 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
1617 #define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
1619 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
1621 #define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
1623 #define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
1625 #define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
1627 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
1629 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
1631 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
1633 #define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
1635 #define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
1637 #define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
1639 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
1641 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
1643 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
1645 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
1647 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
1649 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
1651 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
1653 #define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
1655 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
1657 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
1659 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
1661 #define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
1663 #define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
1665 #define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
1667 #define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
1669 #define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
1671 #define REG_A5XX_SP_MODE_CNTL 0x00000ec2
1673 #define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
1675 #define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
1677 #define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
1679 #define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
1681 #define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
1683 #define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
1685 #define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
1687 #define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
1689 #define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
1691 #define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
1693 #define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
1695 #define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
1697 #define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
1699 #define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
1701 #define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
1703 #define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
1705 #define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
1707 #define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
1709 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
1711 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
1713 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
1715 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
1717 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
1719 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
1721 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
1723 #define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
1725 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
1727 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
1729 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
1731 #define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
1733 #define REG_A5XX_VBIF_VERSION 0x00003000
1735 #define REG_A5XX_VBIF_CLKON 0x00003001
1737 #define REG_A5XX_VBIF_ABIT_SORT 0x00003028
1739 #define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
1741 #define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
1743 #define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
1745 #define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
1747 #define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
1749 #define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
1751 #define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
1753 #define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
1755 #define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
1757 #define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
1759 #define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
1761 #define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
1763 #define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
1765 #define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
1767 #define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
1769 #define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
1771 #define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
1773 #define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
1775 #define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
1777 #define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
1779 #define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
1781 #define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
1783 #define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
1785 #define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
1787 #define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
1789 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
1791 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
1793 #define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
1795 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
1797 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
1799 #define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
1801 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
1803 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
1805 #define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
1807 #define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
1809 #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
1811 #define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
1813 #define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
1815 #define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
1817 #define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
1818 #define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
1820 #define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
1821 #define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
1823 #define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
1825 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
1827 #define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
1829 #define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
1831 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
1833 #define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
1835 #define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
1837 #define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
1839 #define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
1841 #define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
1843 #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
1845 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
1847 #define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
1849 #define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
1851 #define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
1853 #define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
1855 #define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
1857 #define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
1859 #define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
1861 #define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
1863 #define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
1865 #define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
1867 #define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
1869 #define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
1871 #define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
1873 #define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
1875 #define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
1877 #define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
1879 #define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
1881 #define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
1883 #define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
1885 #define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
1887 #define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
1889 #define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
1891 #define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
1893 #define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
1895 #define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
1897 #define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
1899 #define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
1901 #define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
1903 #define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
1905 #define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
1907 #define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
1909 #define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
1911 #define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
1913 #define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
1915 #define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
1917 #define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
1919 #define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
1921 #define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
1923 #define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
1925 #define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
1927 #define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
1929 #define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
1931 #define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
1933 #define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
1935 #define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
1937 #define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
1939 #define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
1941 #define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
1943 #define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
1945 #define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
1947 #define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
1949 #define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
1951 #define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
1953 #define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
1955 #define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
1957 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
1959 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
1961 #define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
1963 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
1965 #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
1967 #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
1969 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
1971 #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
1973 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
1975 #define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
1977 #define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
1979 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
1981 #define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
1983 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
1985 #define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
1987 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
1989 #define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
1991 #define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
1993 #define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
1995 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
1997 #define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
1999 #define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
2001 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
2003 #define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
2005 #define REG_A5XX_GDPM_CONFIG1 0x0000b80c
2007 #define REG_A5XX_GDPM_CONFIG2 0x0000b80d
2009 #define REG_A5XX_GDPM_INT_EN 0x0000b80f
2011 #define REG_A5XX_GDPM_INT_MASK 0x0000b811
2013 #define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
2015 #define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
2017 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
2019 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
2021 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
2023 #define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
2025 #define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
2027 #define REG_A5XX_GRAS_CL_CNTL 0x0000e000
2029 #define REG_A5XX_UNKNOWN_E001 0x0000e001
2031 #define REG_A5XX_UNKNOWN_E004 0x0000e004
2033 #define REG_A5XX_GRAS_CNTL 0x0000e005
2034 #define A5XX_GRAS_CNTL_VARYING 0x00000001
2035 #define A5XX_GRAS_CNTL_UNK3 0x00000008
2036 #define A5XX_GRAS_CNTL_XCOORD 0x00000040
2037 #define A5XX_GRAS_CNTL_YCOORD 0x00000080
2038 #define A5XX_GRAS_CNTL_ZCOORD 0x00000100
2039 #define A5XX_GRAS_CNTL_WCOORD 0x00000200
2041 #define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
2042 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
2043 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
2044 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val
)
2046 return ((val
) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT
) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK
;
2048 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
2049 #define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
2050 static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val
)
2052 return ((val
) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT
) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK
;
2055 #define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
2056 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2057 #define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2058 static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val
)
2060 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT
) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK
;
2063 #define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
2064 #define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2065 #define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2066 static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val
)
2068 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT
) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK
;
2071 #define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
2072 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2073 #define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2074 static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val
)
2076 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT
) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK
;
2079 #define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
2080 #define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2081 #define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2082 static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val
)
2084 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT
) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK
;
2087 #define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
2088 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2089 #define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2090 static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val
)
2092 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT
) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK
;
2095 #define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
2096 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2097 #define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2098 static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val
)
2100 return ((fui(val
)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT
) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK
;
2103 #define REG_A5XX_GRAS_SU_CNTL 0x0000e090
2104 #define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2105 #define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2106 #define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2107 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2108 #define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
2109 static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val
)
2111 return ((((int32_t)(val
* 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT
) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2113 #define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2114 #define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
2116 #define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
2117 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2118 #define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2119 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val
)
2121 return ((((uint32_t)(val
* 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT
) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK
;
2123 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2124 #define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2125 static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val
)
2127 return ((((uint32_t)(val
* 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT
) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK
;
2130 #define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
2131 #define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2132 #define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
2133 static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val
)
2135 return ((((int32_t)(val
* 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT
) & A5XX_GRAS_SU_POINT_SIZE__MASK
;
2138 #define REG_A5XX_UNKNOWN_E093 0x0000e093
2140 #define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
2141 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2142 #define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002
2144 #define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
2145 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2146 #define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2147 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val
)
2149 return ((fui(val
)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT
) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK
;
2152 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
2153 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2154 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2155 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val
)
2157 return ((fui(val
)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
;
2160 #define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
2161 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2162 #define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2163 static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val
)
2165 return ((fui(val
)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT
) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK
;
2168 #define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
2169 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2170 #define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2171 static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val
)
2173 return ((val
) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT
) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
;
2176 #define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
2178 #define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
2179 #define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
2180 #define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
2182 #define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
2184 #define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
2185 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2186 #define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2187 static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
2189 return ((val
) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK
;
2192 #define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
2193 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2194 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2195 static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
2197 return ((val
) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK
;
2199 #define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2201 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
2203 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
2204 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2205 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2206 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2207 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val
)
2209 return ((val
) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT
) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK
;
2211 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2212 #define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2213 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val
)
2215 return ((val
) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT
) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK
;
2218 #define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
2219 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2220 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
2221 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
2222 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val
)
2224 return ((val
) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT
) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK
;
2226 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
2227 #define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
2228 static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val
)
2230 return ((val
) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT
) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK
;
2233 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
2234 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2235 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
2236 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
2237 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val
)
2239 return ((val
) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT
) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK
;
2241 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
2242 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
2243 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val
)
2245 return ((val
) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT
) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK
;
2248 #define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
2249 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2250 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
2251 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
2252 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val
)
2254 return ((val
) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT
) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK
;
2256 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
2257 #define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
2258 static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val
)
2260 return ((val
) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT
) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK
;
2263 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
2264 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2265 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2266 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2267 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val
)
2269 return ((val
) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT
) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
;
2271 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2272 #define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2273 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val
)
2275 return ((val
) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT
) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
;
2278 #define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
2279 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2280 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2281 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2282 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val
)
2284 return ((val
) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT
) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
;
2286 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2287 #define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2288 static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val
)
2290 return ((val
) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT
) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
;
2293 #define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
2295 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
2297 #define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
2299 #define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
2301 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
2303 #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
2305 #define REG_A5XX_RB_CNTL 0x0000e140
2306 #define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
2307 #define A5XX_RB_CNTL_WIDTH__SHIFT 0
2308 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val
)
2310 assert(!(val
& 0x1f));
2311 return ((val
>> 5) << A5XX_RB_CNTL_WIDTH__SHIFT
) & A5XX_RB_CNTL_WIDTH__MASK
;
2313 #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
2314 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9
2315 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val
)
2317 assert(!(val
& 0x1f));
2318 return ((val
>> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT
) & A5XX_RB_CNTL_HEIGHT__MASK
;
2320 #define A5XX_RB_CNTL_BYPASS 0x00020000
2322 #define REG_A5XX_RB_RENDER_CNTL 0x0000e141
2323 #define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
2324 #define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
2325 #define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
2326 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
2327 #define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
2328 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
2329 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
2330 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val
)
2332 return ((val
) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT
) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK
;
2334 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
2335 #define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
2336 static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val
)
2338 return ((val
) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT
) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK
;
2341 #define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
2342 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2343 #define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2344 static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
2346 return ((val
) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK
;
2349 #define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
2350 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2351 #define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2352 static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
2354 return ((val
) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK
;
2356 #define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2358 #define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
2359 #define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
2360 #define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008
2361 #define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
2362 #define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
2363 #define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
2364 #define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
2366 #define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
2367 #define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
2369 #define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
2370 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
2371 #define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
2372 static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val
)
2374 return ((val
) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT
) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK
;
2376 #define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
2378 #define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
2379 #define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
2380 #define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
2381 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val
)
2383 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK
;
2385 #define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
2386 #define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
2387 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val
)
2389 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK
;
2391 #define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
2392 #define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
2393 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val
)
2395 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK
;
2397 #define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
2398 #define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
2399 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val
)
2401 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK
;
2403 #define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
2404 #define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
2405 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val
)
2407 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK
;
2409 #define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
2410 #define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
2411 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val
)
2413 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK
;
2415 #define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
2416 #define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
2417 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val
)
2419 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK
;
2421 #define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
2422 #define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
2423 static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val
)
2425 return ((val
) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT
) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK
;
2428 static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0
) { return 0x0000e150 + 0x7*i0
; }
2430 static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0
) { return 0x0000e150 + 0x7*i0
; }
2431 #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
2432 #define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
2433 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
2434 #define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
2435 static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val
)
2437 return ((val
) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT
) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
2440 static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0
) { return 0x0000e151 + 0x7*i0
; }
2441 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
2442 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
2443 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val
)
2445 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
;
2447 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
2448 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
2449 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val
)
2451 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
;
2453 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
2454 #define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
2455 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val
)
2457 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
;
2459 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
2460 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
2461 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val
)
2463 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
;
2465 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
2466 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
2467 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val
)
2469 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
;
2471 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
2472 #define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
2473 static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val
)
2475 return ((val
) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT
) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
;
2478 static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0
) { return 0x0000e152 + 0x7*i0
; }
2479 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
2480 #define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
2481 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
2483 return ((val
) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT
) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
;
2485 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
2486 #define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
2487 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val
)
2489 return ((val
) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT
) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
;
2491 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
2492 #define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
2493 static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
2495 return ((val
) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT
) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
;
2497 #define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
2499 static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0
) { return 0x0000e153 + 0x7*i0
; }
2500 #define A5XX_RB_MRT_PITCH__MASK 0xffffffff
2501 #define A5XX_RB_MRT_PITCH__SHIFT 0
2502 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val
)
2504 assert(!(val
& 0x3f));
2505 return ((val
>> 6) << A5XX_RB_MRT_PITCH__SHIFT
) & A5XX_RB_MRT_PITCH__MASK
;
2508 static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0
) { return 0x0000e154 + 0x7*i0
; }
2509 #define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
2510 #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
2511 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val
)
2513 assert(!(val
& 0x3f));
2514 return ((val
>> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT
) & A5XX_RB_MRT_ARRAY_PITCH__MASK
;
2517 static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0
) { return 0x0000e155 + 0x7*i0
; }
2519 static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0
) { return 0x0000e156 + 0x7*i0
; }
2521 #define REG_A5XX_RB_BLEND_RED 0x0000e1a0
2522 #define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
2523 #define A5XX_RB_BLEND_RED_UINT__SHIFT 0
2524 static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val
)
2526 return ((val
) << A5XX_RB_BLEND_RED_UINT__SHIFT
) & A5XX_RB_BLEND_RED_UINT__MASK
;
2528 #define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
2529 #define A5XX_RB_BLEND_RED_SINT__SHIFT 8
2530 static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val
)
2532 return ((val
) << A5XX_RB_BLEND_RED_SINT__SHIFT
) & A5XX_RB_BLEND_RED_SINT__MASK
;
2534 #define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
2535 #define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
2536 static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val
)
2538 return ((util_float_to_half(val
)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT
) & A5XX_RB_BLEND_RED_FLOAT__MASK
;
2541 #define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
2542 #define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
2543 #define A5XX_RB_BLEND_RED_F32__SHIFT 0
2544 static inline uint32_t A5XX_RB_BLEND_RED_F32(float val
)
2546 return ((fui(val
)) << A5XX_RB_BLEND_RED_F32__SHIFT
) & A5XX_RB_BLEND_RED_F32__MASK
;
2549 #define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
2550 #define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
2551 #define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
2552 static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val
)
2554 return ((val
) << A5XX_RB_BLEND_GREEN_UINT__SHIFT
) & A5XX_RB_BLEND_GREEN_UINT__MASK
;
2556 #define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
2557 #define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
2558 static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val
)
2560 return ((val
) << A5XX_RB_BLEND_GREEN_SINT__SHIFT
) & A5XX_RB_BLEND_GREEN_SINT__MASK
;
2562 #define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
2563 #define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
2564 static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val
)
2566 return ((util_float_to_half(val
)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT
) & A5XX_RB_BLEND_GREEN_FLOAT__MASK
;
2569 #define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
2570 #define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
2571 #define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
2572 static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val
)
2574 return ((fui(val
)) << A5XX_RB_BLEND_GREEN_F32__SHIFT
) & A5XX_RB_BLEND_GREEN_F32__MASK
;
2577 #define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
2578 #define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
2579 #define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
2580 static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val
)
2582 return ((val
) << A5XX_RB_BLEND_BLUE_UINT__SHIFT
) & A5XX_RB_BLEND_BLUE_UINT__MASK
;
2584 #define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
2585 #define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
2586 static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val
)
2588 return ((val
) << A5XX_RB_BLEND_BLUE_SINT__SHIFT
) & A5XX_RB_BLEND_BLUE_SINT__MASK
;
2590 #define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
2591 #define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
2592 static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val
)
2594 return ((util_float_to_half(val
)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT
) & A5XX_RB_BLEND_BLUE_FLOAT__MASK
;
2597 #define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
2598 #define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
2599 #define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
2600 static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val
)
2602 return ((fui(val
)) << A5XX_RB_BLEND_BLUE_F32__SHIFT
) & A5XX_RB_BLEND_BLUE_F32__MASK
;
2605 #define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
2606 #define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
2607 #define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
2608 static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val
)
2610 return ((val
) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT
) & A5XX_RB_BLEND_ALPHA_UINT__MASK
;
2612 #define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
2613 #define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
2614 static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val
)
2616 return ((val
) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT
) & A5XX_RB_BLEND_ALPHA_SINT__MASK
;
2618 #define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
2619 #define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
2620 static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val
)
2622 return ((util_float_to_half(val
)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT
) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK
;
2625 #define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
2626 #define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
2627 #define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
2628 static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val
)
2630 return ((fui(val
)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT
) & A5XX_RB_BLEND_ALPHA_F32__MASK
;
2633 #define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
2634 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
2635 #define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
2636 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val
)
2638 return ((val
) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT
) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK
;
2640 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
2641 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
2642 #define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
2643 static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val
)
2645 return ((val
) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT
) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK
;
2648 #define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
2649 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
2650 #define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
2651 static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val
)
2653 return ((val
) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT
) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK
;
2655 #define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
2656 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
2657 #define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
2658 static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val
)
2660 return ((val
) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT
) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK
;
2663 #define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
2664 #define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2665 #define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
2667 #define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
2668 #define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
2669 #define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
2670 #define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
2671 #define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
2672 static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val
)
2674 return ((val
) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT
) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK
;
2676 #define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
2678 #define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
2679 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2680 #define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2681 static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val
)
2683 return ((val
) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT
) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
;
2686 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
2688 #define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
2690 #define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
2691 #define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
2692 #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
2693 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val
)
2695 assert(!(val
& 0x3f));
2696 return ((val
>> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT
) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK
;
2699 #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
2700 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
2701 #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
2702 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val
)
2704 assert(!(val
& 0x3f));
2705 return ((val
>> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT
) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK
;
2708 #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
2709 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
2710 #define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
2711 #define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
2712 #define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
2713 #define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
2714 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val
)
2716 return ((val
) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT
) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK
;
2718 #define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
2719 #define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
2720 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val
)
2722 return ((val
) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT
) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK
;
2724 #define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
2725 #define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
2726 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val
)
2728 return ((val
) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT
) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK
;
2730 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
2731 #define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
2732 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val
)
2734 return ((val
) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT
) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK
;
2736 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
2737 #define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
2738 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val
)
2740 return ((val
) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT
) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
;
2742 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
2743 #define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
2744 static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val
)
2746 return ((val
) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT
) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
;
2748 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
2749 #define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
2750 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val
)
2752 return ((val
) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT
) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
;
2754 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
2755 #define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
2756 static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val
)
2758 return ((val
) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT
) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
;
2761 #define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
2762 #define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
2764 #define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
2766 #define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
2768 #define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
2769 #define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
2770 #define A5XX_RB_STENCIL_PITCH__SHIFT 0
2771 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val
)
2773 assert(!(val
& 0x3f));
2774 return ((val
>> 6) << A5XX_RB_STENCIL_PITCH__SHIFT
) & A5XX_RB_STENCIL_PITCH__MASK
;
2777 #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
2778 #define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
2779 #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
2780 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val
)
2782 assert(!(val
& 0x3f));
2783 return ((val
>> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT
) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK
;
2786 #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
2787 #define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
2788 #define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
2789 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val
)
2791 return ((val
) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT
) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK
;
2793 #define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
2794 #define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
2795 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val
)
2797 return ((val
) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT
) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK
;
2799 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
2800 #define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
2801 static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val
)
2803 return ((val
) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT
) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK
;
2806 #define REG_A5XX_UNKNOWN_E1C7 0x0000e1c7
2808 #define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
2809 #define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
2810 #define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
2811 #define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
2812 static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val
)
2814 return ((val
) << A5XX_RB_WINDOW_OFFSET_X__SHIFT
) & A5XX_RB_WINDOW_OFFSET_X__MASK
;
2816 #define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
2817 #define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
2818 static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val
)
2820 return ((val
) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT
) & A5XX_RB_WINDOW_OFFSET_Y__MASK
;
2823 #define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1
2824 #define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
2826 #define REG_A5XX_RB_BLIT_CNTL 0x0000e210
2827 #define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
2828 #define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
2829 static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val
)
2831 return ((val
) << A5XX_RB_BLIT_CNTL_BUF__SHIFT
) & A5XX_RB_BLIT_CNTL_BUF__MASK
;
2834 #define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
2835 #define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
2836 #define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
2837 #define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
2838 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val
)
2840 return ((val
) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT
) & A5XX_RB_RESOLVE_CNTL_1_X__MASK
;
2842 #define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
2843 #define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
2844 static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val
)
2846 return ((val
) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT
) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK
;
2849 #define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
2850 #define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
2851 #define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
2852 #define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
2853 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val
)
2855 return ((val
) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT
) & A5XX_RB_RESOLVE_CNTL_2_X__MASK
;
2857 #define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
2858 #define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
2859 static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val
)
2861 return ((val
) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT
) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK
;
2864 #define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
2866 #define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
2868 #define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
2870 #define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
2871 #define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
2872 #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
2873 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val
)
2875 assert(!(val
& 0x3f));
2876 return ((val
>> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT
) & A5XX_RB_BLIT_DST_PITCH__MASK
;
2879 #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
2880 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
2881 #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
2882 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val
)
2884 assert(!(val
& 0x3f));
2885 return ((val
>> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT
) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK
;
2888 #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
2890 #define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
2892 #define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
2894 #define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
2896 #define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
2897 #define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
2898 #define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
2899 #define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
2900 static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val
)
2902 return ((val
) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT
) & A5XX_RB_CLEAR_CNTL_MASK__MASK
;
2905 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
2907 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
2909 #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
2911 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0
) { return 0x0000e243 + 0x4*i0
; }
2913 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0
) { return 0x0000e243 + 0x4*i0
; }
2915 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0
) { return 0x0000e244 + 0x4*i0
; }
2917 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0
) { return 0x0000e245 + 0x4*i0
; }
2918 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
2919 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
2920 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val
)
2922 assert(!(val
& 0x3f));
2923 return ((val
>> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT
) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK
;
2926 static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0
) { return 0x0000e246 + 0x4*i0
; }
2927 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
2928 #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
2929 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val
)
2931 assert(!(val
& 0x3f));
2932 return ((val
>> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT
) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK
;
2935 #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
2937 #define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
2939 #define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
2940 #define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
2941 #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
2942 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val
)
2944 assert(!(val
& 0x3f));
2945 return ((val
>> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT
) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK
;
2948 #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
2949 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
2950 #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
2951 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val
)
2953 assert(!(val
& 0x3f));
2954 return ((val
>> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT
) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK
;
2957 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
2959 #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268
2961 #define REG_A5XX_VPC_CNTL_0 0x0000e280
2962 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
2963 #define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
2964 static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val
)
2966 return ((val
) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT
) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK
;
2968 #define A5XX_VPC_CNTL_0_VARYING 0x00000800
2970 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0
) { return 0x0000e282 + 0x1*i0
; }
2972 static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0
) { return 0x0000e282 + 0x1*i0
; }
2974 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0
) { return 0x0000e28a + 0x1*i0
; }
2976 static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0
) { return 0x0000e28a + 0x1*i0
; }
2978 #define REG_A5XX_UNKNOWN_E292 0x0000e292
2980 #define REG_A5XX_UNKNOWN_E293 0x0000e293
2982 static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0
) { return 0x0000e294 + 0x1*i0
; }
2984 static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0
) { return 0x0000e294 + 0x1*i0
; }
2986 #define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
2988 #define REG_A5XX_UNKNOWN_E29A 0x0000e29a
2990 #define REG_A5XX_VPC_PACK 0x0000e29d
2991 #define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
2992 #define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
2993 static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val
)
2995 return ((val
) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT
) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK
;
2997 #define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00
2998 #define A5XX_VPC_PACK_PSIZELOC__SHIFT 8
2999 static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val
)
3001 return ((val
) << A5XX_VPC_PACK_PSIZELOC__SHIFT
) & A5XX_VPC_PACK_PSIZELOC__MASK
;
3004 #define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
3006 #define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
3007 #define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
3008 #define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
3009 #define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
3010 #define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
3011 #define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
3013 #define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
3014 #define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
3016 #define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
3017 #define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
3019 #define REG_A5XX_VPC_SO_PROG 0x0000e2a4
3020 #define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
3021 #define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
3022 static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val
)
3024 return ((val
) << A5XX_VPC_SO_PROG_A_BUF__SHIFT
) & A5XX_VPC_SO_PROG_A_BUF__MASK
;
3026 #define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
3027 #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
3028 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val
)
3030 assert(!(val
& 0x3));
3031 return ((val
>> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT
) & A5XX_VPC_SO_PROG_A_OFF__MASK
;
3033 #define A5XX_VPC_SO_PROG_A_EN 0x00000800
3034 #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
3035 #define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
3036 static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val
)
3038 return ((val
) << A5XX_VPC_SO_PROG_B_BUF__SHIFT
) & A5XX_VPC_SO_PROG_B_BUF__MASK
;
3040 #define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
3041 #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
3042 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val
)
3044 assert(!(val
& 0x3));
3045 return ((val
>> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT
) & A5XX_VPC_SO_PROG_B_OFF__MASK
;
3047 #define A5XX_VPC_SO_PROG_B_EN 0x00800000
3049 static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0
) { return 0x0000e2a7 + 0x7*i0
; }
3051 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0
) { return 0x0000e2a7 + 0x7*i0
; }
3053 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0
) { return 0x0000e2a8 + 0x7*i0
; }
3055 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0
) { return 0x0000e2a9 + 0x7*i0
; }
3057 static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0
) { return 0x0000e2aa + 0x7*i0
; }
3059 static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0
) { return 0x0000e2ab + 0x7*i0
; }
3061 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0
) { return 0x0000e2ac + 0x7*i0
; }
3063 static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0
) { return 0x0000e2ad + 0x7*i0
; }
3065 #define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
3066 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
3067 #define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
3068 static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val
)
3070 return ((val
) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT
) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK
;
3072 #define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
3074 #define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
3075 #define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
3077 #define REG_A5XX_PC_RASTER_CNTL 0x0000e388
3079 #define REG_A5XX_UNKNOWN_E389 0x0000e389
3081 #define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
3083 #define REG_A5XX_UNKNOWN_E38D 0x0000e38d
3085 #define REG_A5XX_PC_GS_PARAM 0x0000e38e
3087 #define REG_A5XX_PC_HS_PARAM 0x0000e38f
3089 #define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
3091 #define REG_A5XX_VFD_CONTROL_0 0x0000e400
3092 #define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
3093 #define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
3094 static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val
)
3096 return ((val
) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT
) & A5XX_VFD_CONTROL_0_VTXCNT__MASK
;
3099 #define REG_A5XX_VFD_CONTROL_1 0x0000e401
3100 #define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
3101 #define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
3102 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val
)
3104 return ((val
) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT
) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK
;
3106 #define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
3107 #define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
3108 static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val
)
3110 return ((val
) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT
) & A5XX_VFD_CONTROL_1_REGID4INST__MASK
;
3113 #define REG_A5XX_VFD_CONTROL_2 0x0000e402
3115 #define REG_A5XX_VFD_CONTROL_3 0x0000e403
3117 #define REG_A5XX_VFD_CONTROL_4 0x0000e404
3119 #define REG_A5XX_VFD_CONTROL_5 0x0000e405
3121 #define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
3123 #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
3125 static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0
) { return 0x0000e40a + 0x4*i0
; }
3127 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0
) { return 0x0000e40a + 0x4*i0
; }
3129 static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0
) { return 0x0000e40b + 0x4*i0
; }
3131 static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0
) { return 0x0000e40c + 0x4*i0
; }
3133 static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0
) { return 0x0000e40d + 0x4*i0
; }
3135 static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0
) { return 0x0000e48a + 0x2*i0
; }
3137 static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0
) { return 0x0000e48a + 0x2*i0
; }
3138 #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
3139 #define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
3140 static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val
)
3142 return ((val
) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT
) & A5XX_VFD_DECODE_INSTR_IDX__MASK
;
3144 #define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
3145 #define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000
3146 #define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
3147 static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val
)
3149 return ((val
) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT
) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK
;
3151 #define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
3152 #define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
3154 static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0
) { return 0x0000e48b + 0x2*i0
; }
3156 static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0
) { return 0x0000e4ca + 0x1*i0
; }
3158 static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0
) { return 0x0000e4ca + 0x1*i0
; }
3159 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
3160 #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
3161 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val
)
3163 return ((val
) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT
) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK
;
3165 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
3166 #define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
3167 static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val
)
3169 return ((val
) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT
) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK
;
3172 #define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
3174 #define REG_A5XX_SP_SP_CNTL 0x0000e580
3176 #define REG_A5XX_SP_VS_CONFIG 0x0000e584
3177 #define A5XX_SP_VS_CONFIG_ENABLED 0x00000001
3178 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3179 #define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3180 static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3182 return ((val
) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3184 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3185 #define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3186 static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3188 return ((val
) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK
;
3191 #define REG_A5XX_SP_FS_CONFIG 0x0000e585
3192 #define A5XX_SP_FS_CONFIG_ENABLED 0x00000001
3193 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3194 #define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3195 static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3197 return ((val
) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3199 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3200 #define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3201 static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3203 return ((val
) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK
;
3206 #define REG_A5XX_SP_HS_CONFIG 0x0000e586
3207 #define A5XX_SP_HS_CONFIG_ENABLED 0x00000001
3208 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3209 #define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3210 static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3212 return ((val
) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3214 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3215 #define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3216 static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3218 return ((val
) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK
;
3221 #define REG_A5XX_SP_DS_CONFIG 0x0000e587
3222 #define A5XX_SP_DS_CONFIG_ENABLED 0x00000001
3223 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3224 #define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3225 static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3227 return ((val
) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3229 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3230 #define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3231 static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3233 return ((val
) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK
;
3236 #define REG_A5XX_SP_GS_CONFIG 0x0000e588
3237 #define A5XX_SP_GS_CONFIG_ENABLED 0x00000001
3238 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3239 #define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3240 static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3242 return ((val
) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3244 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3245 #define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3246 static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3248 return ((val
) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK
;
3251 #define REG_A5XX_SP_CS_CONFIG 0x0000e589
3252 #define A5XX_SP_CS_CONFIG_ENABLED 0x00000001
3253 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3254 #define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3255 static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3257 return ((val
) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3259 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3260 #define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3261 static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3263 return ((val
) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK
;
3266 #define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
3268 #define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
3270 #define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
3271 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008
3272 #define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3
3273 static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
3275 return ((val
) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT
) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK
;
3277 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3278 #define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3279 static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
3281 return ((val
) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
3283 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3284 #define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3285 static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
3287 return ((val
) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
3289 #define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
3290 #define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
3291 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
3292 #define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
3293 static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val
)
3295 return ((val
) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT
) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK
;
3298 #define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
3299 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
3300 #define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
3301 static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val
)
3303 return ((val
) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT
) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK
;
3306 static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0
) { return 0x0000e593 + 0x1*i0
; }
3308 static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0
) { return 0x0000e593 + 0x1*i0
; }
3309 #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
3310 #define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
3311 static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val
)
3313 return ((val
) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT
) & A5XX_SP_VS_OUT_REG_A_REGID__MASK
;
3315 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
3316 #define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
3317 static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val
)
3319 return ((val
) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT
) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK
;
3321 #define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
3322 #define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
3323 static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val
)
3325 return ((val
) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT
) & A5XX_SP_VS_OUT_REG_B_REGID__MASK
;
3327 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
3328 #define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
3329 static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val
)
3331 return ((val
) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT
) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK
;
3334 static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0
) { return 0x0000e5a3 + 0x1*i0
; }
3336 static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0
) { return 0x0000e5a3 + 0x1*i0
; }
3337 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
3338 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
3339 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val
)
3341 return ((val
) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT
) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
;
3343 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
3344 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
3345 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val
)
3347 return ((val
) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT
) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
;
3349 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
3350 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
3351 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val
)
3353 return ((val
) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT
) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
;
3355 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
3356 #define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
3357 static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val
)
3359 return ((val
) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT
) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
;
3362 #define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
3364 #define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
3366 #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
3368 #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
3369 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
3370 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3
3371 static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
3373 return ((val
) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT
) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
;
3375 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3376 #define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3377 static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
3379 return ((val
) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
3381 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3382 #define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3383 static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
3385 return ((val
) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
3387 #define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
3388 #define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
3389 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
3390 #define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
3391 static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val
)
3393 return ((val
) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT
) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK
;
3396 #define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
3398 #define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
3400 #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
3402 #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
3404 #define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
3405 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
3406 #define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
3407 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val
)
3409 return ((val
) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT
) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK
;
3411 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
3412 #define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
3413 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val
)
3415 return ((val
) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT
) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK
;
3417 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
3418 #define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
3419 static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val
)
3421 return ((val
) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT
) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK
;
3424 static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0
) { return 0x0000e5cb + 0x1*i0
; }
3426 static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0
) { return 0x0000e5cb + 0x1*i0
; }
3427 #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
3428 #define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
3429 static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val
)
3431 return ((val
) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT
) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK
;
3433 #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
3435 static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0
) { return 0x0000e5d3 + 0x1*i0
; }
3437 static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0
) { return 0x0000e5d3 + 0x1*i0
; }
3438 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
3439 #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
3440 static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val
)
3442 return ((val
) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT
) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK
;
3444 #define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
3446 #define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
3448 #define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
3450 #define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
3452 #define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
3454 #define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
3455 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
3456 #define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
3457 static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val
)
3459 return ((val
) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT
) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK
;
3461 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
3462 #define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
3463 static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val
)
3465 return ((val
) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT
) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK
;
3467 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
3468 #define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
3469 static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val
)
3471 return ((val
) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT
) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK
;
3473 #define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000
3474 #define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000
3475 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
3476 #define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25
3477 static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val
)
3479 return ((val
) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT
) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK
;
3482 #define REG_A5XX_UNKNOWN_E600 0x0000e600
3484 #define REG_A5XX_UNKNOWN_E602 0x0000e602
3486 #define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603
3488 #define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
3490 #define REG_A5XX_UNKNOWN_E62B 0x0000e62b
3492 #define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
3494 #define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
3496 #define REG_A5XX_UNKNOWN_E640 0x0000e640
3498 #define REG_A5XX_UNKNOWN_E65B 0x0000e65b
3500 #define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c
3502 #define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
3504 #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
3505 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3506 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
3507 static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
3509 return ((val
) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK
;
3512 #define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
3513 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3514 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
3515 static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
)
3517 return ((val
) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT
) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK
;
3519 #define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3521 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
3523 #define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
3525 #define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
3527 #define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701
3529 #define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702
3531 #define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703
3533 #define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
3535 #define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
3537 #define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724
3539 #define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725
3541 #define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726
3543 #define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727
3545 #define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728
3547 #define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729
3549 #define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
3551 #define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
3553 #define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c
3555 #define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d
3557 #define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e
3559 #define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f
3561 #define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730
3563 #define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731
3565 #define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
3567 #define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751
3569 #define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
3571 #define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
3573 #define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
3575 #define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d
3577 #define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
3579 #define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
3581 #define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
3583 #define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761
3585 #define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
3587 #define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
3588 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001
3589 #define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0
3590 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val
)
3592 return ((val
) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT
) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK
;
3594 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004
3595 #define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2
3596 static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val
)
3598 return ((val
) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT
) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK
;
3601 #define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
3602 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
3603 #define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
3604 static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val
)
3606 return ((val
) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT
) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK
;
3609 #define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
3610 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
3611 #define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
3612 static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val
)
3614 return ((val
) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT
) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK
;
3617 #define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
3618 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
3619 #define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
3620 static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val
)
3622 return ((val
) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT
) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK
;
3625 #define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
3626 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
3627 #define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
3628 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val
)
3630 return ((val
) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT
) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK
;
3632 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
3633 #define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
3634 static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val
)
3636 return ((val
) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT
) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK
;
3639 #define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
3641 #define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b
3642 #define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001
3643 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3644 #define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3645 static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3647 return ((val
) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3649 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3650 #define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3651 static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3653 return ((val
) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK
;
3656 #define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c
3657 #define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001
3658 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3659 #define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3660 static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3662 return ((val
) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3664 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3665 #define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3666 static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3668 return ((val
) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK
;
3671 #define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d
3672 #define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001
3673 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3674 #define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3675 static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3677 return ((val
) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3679 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3680 #define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3681 static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3683 return ((val
) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK
;
3686 #define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e
3687 #define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001
3688 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3689 #define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3690 static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3692 return ((val
) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3694 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3695 #define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3696 static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3698 return ((val
) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK
;
3701 #define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f
3702 #define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001
3703 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3704 #define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3705 static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3707 return ((val
) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3709 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3710 #define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3711 static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3713 return ((val
) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK
;
3716 #define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
3717 #define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001
3718 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3719 #define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3720 static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val
)
3722 return ((val
) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT
) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK
;
3724 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3725 #define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3726 static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val
)
3728 return ((val
) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT
) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK
;
3731 #define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
3732 #define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001
3733 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
3734 #define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
3735 static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val
)
3737 return ((val
) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK
;
3740 #define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
3741 #define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001
3742 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
3743 #define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
3744 static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val
)
3746 return ((val
) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK
;
3749 #define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
3750 #define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001
3751 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
3752 #define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
3753 static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val
)
3755 return ((val
) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK
;
3758 #define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
3759 #define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001
3760 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
3761 #define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
3762 static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val
)
3764 return ((val
) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK
;
3767 #define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
3768 #define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001
3769 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
3770 #define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
3771 static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val
)
3773 return ((val
) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK
;
3776 #define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
3777 #define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001
3778 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
3779 #define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
3780 static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val
)
3782 return ((val
) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT
) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK
;
3785 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
3787 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
3789 #define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
3791 #define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
3792 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
3793 #define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
3794 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val
)
3796 return ((val
) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT
) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK
;
3798 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
3799 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
3800 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val
)
3802 return ((val
) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT
) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK
;
3804 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
3805 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
3806 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val
)
3808 return ((val
) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT
) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK
;
3810 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
3811 #define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
3812 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val
)
3814 return ((val
) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT
) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK
;
3817 #define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
3818 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK 0xffffffff
3819 #define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT 0
3820 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(uint32_t val
)
3822 return ((val
) << A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT
) & A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK
;
3825 #define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
3827 #define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
3828 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK 0xffffffff
3829 #define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT 0
3830 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(uint32_t val
)
3832 return ((val
) << A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT
) & A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK
;
3835 #define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
3837 #define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
3838 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK 0xffffffff
3839 #define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT 0
3840 static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(uint32_t val
)
3842 return ((val
) << A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT
) & A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK
;
3845 #define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
3847 #define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
3848 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
3849 #define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
3850 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val
)
3852 return ((val
) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT
) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK
;
3854 #define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
3855 #define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
3856 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val
)
3858 return ((val
) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT
) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK
;
3860 #define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
3861 #define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
3862 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val
)
3864 return ((val
) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT
) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK
;
3866 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
3867 #define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
3868 static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val
)
3870 return ((val
) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT
) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK
;
3873 #define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
3875 #define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
3877 #define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
3879 #define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
3881 #define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
3883 #define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
3885 #define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
3887 #define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
3889 #define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
3891 #define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
3893 #define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
3895 #define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
3897 #define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
3899 #define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
3901 #define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
3903 #define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
3905 #define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
3907 #define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc
3909 #define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
3911 #define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
3913 #define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
3915 #define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
3917 #define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
3919 #define REG_A5XX_RB_2D_SRC_INFO 0x00002107
3920 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
3921 #define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
3922 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
3924 return ((val
) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT
) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK
;
3926 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
3927 #define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
3928 static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
3930 return ((val
) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT
) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK
;
3933 #define REG_A5XX_RB_2D_SRC_LO 0x00002108
3935 #define REG_A5XX_RB_2D_SRC_HI 0x00002109
3937 #define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
3938 #define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
3939 #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
3940 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val
)
3942 assert(!(val
& 0x3f));
3943 return ((val
>> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT
) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK
;
3945 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
3946 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
3947 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val
)
3949 assert(!(val
& 0x3f));
3950 return ((val
>> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT
) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK
;
3953 #define REG_A5XX_RB_2D_DST_INFO 0x00002110
3954 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
3955 #define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
3956 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
3958 return ((val
) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT
) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK
;
3960 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
3961 #define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
3962 static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
3964 return ((val
) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT
) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK
;
3967 #define REG_A5XX_RB_2D_DST_LO 0x00002111
3969 #define REG_A5XX_RB_2D_DST_HI 0x00002112
3971 #define REG_A5XX_RB_2D_DST_SIZE 0x00002113
3972 #define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
3973 #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
3974 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val
)
3976 assert(!(val
& 0x3f));
3977 return ((val
>> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT
) & A5XX_RB_2D_DST_SIZE_PITCH__MASK
;
3979 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
3980 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
3981 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val
)
3983 assert(!(val
& 0x3f));
3984 return ((val
>> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT
) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK
;
3987 #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
3989 #define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
3991 #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
3993 #define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
3995 #define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
3996 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
3997 #define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
3998 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
4000 return ((val
) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT
) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK
;
4002 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
4003 #define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
4004 static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
4006 return ((val
) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT
) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK
;
4009 #define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
4010 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
4011 #define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
4012 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val
)
4014 return ((val
) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT
) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK
;
4016 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
4017 #define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
4018 static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val
)
4020 return ((val
) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT
) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK
;
4023 #define REG_A5XX_UNKNOWN_2100 0x00002100
4025 #define REG_A5XX_UNKNOWN_2180 0x00002180
4027 #define REG_A5XX_UNKNOWN_2184 0x00002184
4029 #define REG_A5XX_TEX_SAMP_0 0x00000000
4030 #define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
4031 #define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
4032 #define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
4033 static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val
)
4035 return ((val
) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT
) & A5XX_TEX_SAMP_0_XY_MAG__MASK
;
4037 #define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
4038 #define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
4039 static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val
)
4041 return ((val
) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT
) & A5XX_TEX_SAMP_0_XY_MIN__MASK
;
4043 #define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
4044 #define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
4045 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val
)
4047 return ((val
) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT
) & A5XX_TEX_SAMP_0_WRAP_S__MASK
;
4049 #define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
4050 #define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
4051 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val
)
4053 return ((val
) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT
) & A5XX_TEX_SAMP_0_WRAP_T__MASK
;
4055 #define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
4056 #define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
4057 static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val
)
4059 return ((val
) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT
) & A5XX_TEX_SAMP_0_WRAP_R__MASK
;
4061 #define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
4062 #define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
4063 static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val
)
4065 return ((val
) << A5XX_TEX_SAMP_0_ANISO__SHIFT
) & A5XX_TEX_SAMP_0_ANISO__MASK
;
4067 #define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
4068 #define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
4069 static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val
)
4071 return ((((int32_t)(val
* 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT
) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK
;
4074 #define REG_A5XX_TEX_SAMP_1 0x00000001
4075 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
4076 #define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
4077 static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val
)
4079 return ((val
) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT
) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK
;
4081 #define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
4082 #define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
4083 #define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
4084 #define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
4085 #define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
4086 static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val
)
4088 return ((((uint32_t)(val
* 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT
) & A5XX_TEX_SAMP_1_MAX_LOD__MASK
;
4090 #define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
4091 #define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
4092 static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val
)
4094 return ((((uint32_t)(val
* 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT
) & A5XX_TEX_SAMP_1_MIN_LOD__MASK
;
4097 #define REG_A5XX_TEX_SAMP_2 0x00000002
4098 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
4099 #define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
4100 static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val
)
4102 return ((val
) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT
) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK
;
4105 #define REG_A5XX_TEX_SAMP_3 0x00000003
4107 #define REG_A5XX_TEX_CONST_0 0x00000000
4108 #define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
4109 #define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
4110 static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val
)
4112 return ((val
) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT
) & A5XX_TEX_CONST_0_TILE_MODE__MASK
;
4114 #define A5XX_TEX_CONST_0_SRGB 0x00000004
4115 #define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
4116 #define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
4117 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val
)
4119 return ((val
) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT
) & A5XX_TEX_CONST_0_SWIZ_X__MASK
;
4121 #define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
4122 #define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
4123 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val
)
4125 return ((val
) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT
) & A5XX_TEX_CONST_0_SWIZ_Y__MASK
;
4127 #define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
4128 #define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
4129 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val
)
4131 return ((val
) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT
) & A5XX_TEX_CONST_0_SWIZ_Z__MASK
;
4133 #define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
4134 #define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
4135 static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val
)
4137 return ((val
) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT
) & A5XX_TEX_CONST_0_SWIZ_W__MASK
;
4139 #define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
4140 #define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16
4141 static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val
)
4143 return ((val
) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT
) & A5XX_TEX_CONST_0_MIPLVLS__MASK
;
4145 #define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
4146 #define A5XX_TEX_CONST_0_FMT__SHIFT 22
4147 static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val
)
4149 return ((val
) << A5XX_TEX_CONST_0_FMT__SHIFT
) & A5XX_TEX_CONST_0_FMT__MASK
;
4151 #define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
4152 #define A5XX_TEX_CONST_0_SWAP__SHIFT 30
4153 static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val
)
4155 return ((val
) << A5XX_TEX_CONST_0_SWAP__SHIFT
) & A5XX_TEX_CONST_0_SWAP__MASK
;
4158 #define REG_A5XX_TEX_CONST_1 0x00000001
4159 #define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
4160 #define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
4161 static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val
)
4163 return ((val
) << A5XX_TEX_CONST_1_WIDTH__SHIFT
) & A5XX_TEX_CONST_1_WIDTH__MASK
;
4165 #define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
4166 #define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
4167 static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val
)
4169 return ((val
) << A5XX_TEX_CONST_1_HEIGHT__SHIFT
) & A5XX_TEX_CONST_1_HEIGHT__MASK
;
4172 #define REG_A5XX_TEX_CONST_2 0x00000002
4173 #define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
4174 #define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
4175 static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val
)
4177 return ((val
) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT
) & A5XX_TEX_CONST_2_FETCHSIZE__MASK
;
4179 #define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
4180 #define A5XX_TEX_CONST_2_PITCH__SHIFT 7
4181 static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val
)
4183 return ((val
) << A5XX_TEX_CONST_2_PITCH__SHIFT
) & A5XX_TEX_CONST_2_PITCH__MASK
;
4185 #define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
4186 #define A5XX_TEX_CONST_2_TYPE__SHIFT 29
4187 static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val
)
4189 return ((val
) << A5XX_TEX_CONST_2_TYPE__SHIFT
) & A5XX_TEX_CONST_2_TYPE__MASK
;
4192 #define REG_A5XX_TEX_CONST_3 0x00000003
4193 #define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
4194 #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
4195 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val
)
4197 assert(!(val
& 0xfff));
4198 return ((val
>> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT
) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK
;
4200 #define A5XX_TEX_CONST_3_FLAG 0x10000000
4202 #define REG_A5XX_TEX_CONST_4 0x00000004
4203 #define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
4204 #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
4205 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val
)
4207 assert(!(val
& 0x1f));
4208 return ((val
>> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT
) & A5XX_TEX_CONST_4_BASE_LO__MASK
;
4211 #define REG_A5XX_TEX_CONST_5 0x00000005
4212 #define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
4213 #define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
4214 static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val
)
4216 return ((val
) << A5XX_TEX_CONST_5_BASE_HI__SHIFT
) & A5XX_TEX_CONST_5_BASE_HI__MASK
;
4218 #define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
4219 #define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
4220 static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val
)
4222 return ((val
) << A5XX_TEX_CONST_5_DEPTH__SHIFT
) & A5XX_TEX_CONST_5_DEPTH__MASK
;
4225 #define REG_A5XX_TEX_CONST_6 0x00000006
4227 #define REG_A5XX_TEX_CONST_7 0x00000007
4229 #define REG_A5XX_TEX_CONST_8 0x00000008
4231 #define REG_A5XX_TEX_CONST_9 0x00000009
4233 #define REG_A5XX_TEX_CONST_10 0x0000000a
4235 #define REG_A5XX_TEX_CONST_11 0x0000000b
4238 #endif /* A5XX_XML */