src/gallium/drivers/freedreno/a5xx/fd5_blitter.c

   1 /*
   2  * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "freedreno_blitter.h"
  28 #include "freedreno_resource.h"
  29
  30 #include "fd5_blitter.h"
  31 #include "fd5_format.h"
  32 #include "fd5_emit.h"
  33
  34 /* Make sure none of the requested dimensions extend beyond the size of the
  35  * resource.  Not entirely sure why this happens, but sometimes it does, and
  36  * w/ 2d blt doesn't have wrap modes like a sampler, so force those cases
  37  * back to u_blitter
  38  */
  39 static bool
  40 ok_dims(const struct pipe_resource *r, const struct pipe_box *b, int lvl)
  41 {
  42         return (b->x >= 0) && (b->x + b->width <= u_minify(r->width0, lvl)) &&
  43                 (b->y >= 0) && (b->y + b->height <= u_minify(r->height0, lvl)) &&
  44                 (b->z >= 0) && (b->z + b->depth <= u_minify(r->depth0, lvl));
  45 }
  46
  47 /* Not sure if format restrictions differ for src and dst, or if
  48  * they only matter when src fmt != dst fmt..  but there appear to
  49  * be *some* limitations so let's just start blacklisting stuff that
  50  * piglit complains about
  51  */
  52 static bool
  53 ok_format(enum pipe_format fmt)
  54 {
  55         switch (fmt) {
  56         case PIPE_FORMAT_R10G10B10A2_SSCALED:
  57         case PIPE_FORMAT_R10G10B10A2_SNORM:
  58         case PIPE_FORMAT_B10G10R10A2_USCALED:
  59         case PIPE_FORMAT_B10G10R10A2_SSCALED:
  60         case PIPE_FORMAT_B10G10R10A2_SNORM:
  61         case PIPE_FORMAT_R10G10B10A2_UNORM:
  62         case PIPE_FORMAT_R10G10B10A2_USCALED:
  63         case PIPE_FORMAT_B10G10R10A2_UNORM:
  64         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
  65         case PIPE_FORMAT_B10G10R10A2_UINT:
  66         case PIPE_FORMAT_R10G10B10A2_UINT:
  67                 return false;
  68         default:
  69                 return true;
  70         }
  71 }
  72
  73 static bool
  74 can_do_blit(const struct pipe_blit_info *info)
  75 {
  76         /* I think we can do scaling, but not in z dimension since that would
  77          * require blending..
  78          */
  79         if (info->dst.box.depth != info->src.box.depth)
  80                 return false;
  81
  82         if (!ok_format(info->dst.format))
  83                 return false;
  84
  85         if (!ok_format(info->src.format))
  86                 return false;
  87
  88         /* until we figure out a few more registers: */
  89         if ((info->dst.box.width != info->src.box.width) ||
  90                         (info->dst.box.height != info->src.box.height))
  91                 return false;
  92
  93         /* src box can be inverted, which we don't support.. dst box cannot: */
  94         if ((info->src.box.width < 0) || (info->src.box.height < 0))
  95                 return false;
  96
  97         if (!ok_dims(info->src.resource, &info->src.box, info->src.level))
  98                 return false;
  99
 100         if (!ok_dims(info->dst.resource, &info->dst.box, info->dst.level))
 101                 return false;
 102
 103         debug_assert(info->dst.box.width >= 0);
 104         debug_assert(info->dst.box.height >= 0);
 105         debug_assert(info->dst.box.depth >= 0);
 106
 107         if (info->dst.resource->nr_samples + info->src.resource->nr_samples)
 108                 return false;
 109
 110         if (info->scissor_enable)
 111                 return false;
 112
 113         if (info->window_rectangle_include)
 114                 return false;
 115
 116         if (info->render_condition_enable)
 117                 return false;
 118
 119         if (info->alpha_blend)
 120                 return false;
 121
 122         if (info->filter != PIPE_TEX_FILTER_NEAREST)
 123                 return false;
 124
 125         if (info->mask != util_format_get_mask(info->src.format))
 126                 return false;
 127
 128         if (info->mask != util_format_get_mask(info->dst.format))
 129                 return false;
 130
 131         if (util_format_is_compressed(info->dst.format))
 132                 return false;
 133
 134         if (util_format_is_compressed(info->src.format))
 135                 return false;
 136
 137         return true;
 138 }
 139
 140 static void
 141 emit_setup(struct fd_ringbuffer *ring)
 142 {
 143         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 144         OUT_RING(ring, LRZ_FLUSH);
 145
 146         OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 147         OUT_RING(ring, 0x0);
 148
 149         OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
 150         OUT_RING(ring, 0x00000003);   /* PC_POWER_CNTL */
 151
 152         OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
 153         OUT_RING(ring, 0x00000003);   /* VFD_POWER_CNTL */
 154
 155         /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
 156         OUT_WFI5(ring);
 157         OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
 158         OUT_RING(ring, 0x10000000);   /* RB_CCU_CNTL */
 159
 160         OUT_PKT4(ring, REG_A5XX_RB_RENDER_CNTL, 1);
 161         OUT_RING(ring, 0x00000008);
 162
 163         OUT_PKT4(ring, REG_A5XX_UNKNOWN_2100, 1);
 164         OUT_RING(ring, 0x86000000);   /* UNKNOWN_2100 */
 165
 166         OUT_PKT4(ring, REG_A5XX_UNKNOWN_2180, 1);
 167         OUT_RING(ring, 0x86000000);   /* UNKNOWN_2180 */
 168
 169         OUT_PKT4(ring, REG_A5XX_UNKNOWN_2184, 1);
 170         OUT_RING(ring, 0x00000009);   /* UNKNOWN_2184 */
 171
 172         OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
 173         OUT_RING(ring, A5XX_RB_CNTL_BYPASS);
 174
 175         OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
 176         OUT_RING(ring, 0x00000004);   /* RB_MODE_CNTL */
 177
 178         OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
 179         OUT_RING(ring, 0x0000000c);   /* SP_MODE_CNTL */
 180
 181         OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
 182         OUT_RING(ring, 0x00000344);   /* TPL1_MODE_CNTL */
 183
 184         OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
 185         OUT_RING(ring, 0x00000002);   /* HLSQ_MODE_CNTL */
 186
 187         OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
 188         OUT_RING(ring, 0x00000181);   /* GRAS_CL_CNTL */
 189 }
 190
 191 /* buffers need to be handled specially since x/width can exceed the bounds
 192  * supported by hw.. if necessary decompose into (potentially) two 2D blits
 193  */
 194 static void
 195 emit_blit_buffer(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
 196 {
 197         const struct pipe_box *sbox = &info->src.box;
 198         const struct pipe_box *dbox = &info->dst.box;
 199         struct fd_resource *src, *dst;
 200         unsigned sshift, dshift;
 201
 202         src = fd_resource(info->src.resource);
 203         dst = fd_resource(info->dst.resource);
 204
 205         debug_assert(src->cpp == 1);
 206         debug_assert(dst->cpp == 1);
 207         debug_assert(info->src.resource->format == info->dst.resource->format);
 208         debug_assert((sbox->y == 0) && (sbox->height == 1));
 209         debug_assert((dbox->y == 0) && (dbox->height == 1));
 210         debug_assert((sbox->z == 0) && (sbox->depth == 1));
 211         debug_assert((dbox->z == 0) && (dbox->depth == 1));
 212         debug_assert(sbox->width == dbox->width);
 213         debug_assert(info->src.level == 0);
 214         debug_assert(info->dst.level == 0);
 215
 216         /*
 217          * Buffers can have dimensions bigger than max width, remap into
 218          * multiple 1d blits to fit within max dimension
 219          *
 220          * Note that blob uses .ARRAY_PITCH=128 for blitting buffers, which
 221          * seems to prevent overfetch related faults.  Not quite sure what
 222          * the deal is there.
 223          *
 224          * Low 6 bits of SRC/DST addresses need to be zero (ie. address
 225          * aligned to 64) so we need to shift src/dst x1/x2 to make up the
 226          * difference.  On top of already splitting up the blit so width
 227          * isn't > 16k.
 228          *
 229          * We perhaps could do a bit better, if src and dst are aligned but
 230          * in the worst case this means we have to split the copy up into
 231          * 16k (0x4000) minus 64 (0x40).
 232          */
 233
 234         sshift = sbox->x & 0x3f;
 235         dshift = dbox->x & 0x3f;
 236
 237         for (unsigned off = 0; off < sbox->width; off += (0x4000 - 0x40)) {
 238                 unsigned soff, doff, w, p;
 239
 240                 soff = (sbox->x + off) & ~0x3f;
 241                 doff = (dbox->x + off) & ~0x3f;
 242
 243                 w = MIN2(sbox->width - off, (0x4000 - 0x40));
 244                 p = align(w, 64);
 245
 246                 debug_assert((soff + w) <= fd_bo_size(src->bo));
 247                 debug_assert((doff + w) <= fd_bo_size(dst->bo));
 248
 249                 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
 250                 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(BLIT2D));
 251
 252                 /*
 253                  * Emit source:
 254                  */
 255                 OUT_PKT4(ring, REG_A5XX_RB_2D_SRC_INFO, 9);
 256                 OUT_RING(ring, A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
 257                                 A5XX_RB_2D_SRC_INFO_COLOR_SWAP(WZYX));
 258                 OUT_RELOC(ring, src->bo, soff, 0, 0);    /* RB_2D_SRC_LO/HI */
 259                 OUT_RING(ring, A5XX_RB_2D_SRC_SIZE_PITCH(p) |
 260                                 A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(128));
 261                 OUT_RING(ring, 0x00000000);
 262                 OUT_RING(ring, 0x00000000);
 263                 OUT_RING(ring, 0x00000000);
 264                 OUT_RING(ring, 0x00000000);
 265                 OUT_RING(ring, 0x00000000);
 266
 267                 OUT_PKT4(ring, REG_A5XX_GRAS_2D_SRC_INFO, 1);
 268                 OUT_RING(ring, A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
 269                                 A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(WZYX));
 270
 271                 /*
 272                  * Emit destination:
 273                  */
 274                 OUT_PKT4(ring, REG_A5XX_RB_2D_DST_INFO, 9);
 275                 OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
 276                                 A5XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
 277                 OUT_RELOCW(ring, dst->bo, doff, 0, 0);   /* RB_2D_DST_LO/HI */
 278                 OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(p) |
 279                                 A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(128));
 280                 OUT_RING(ring, 0x00000000);
 281                 OUT_RING(ring, 0x00000000);
 282                 OUT_RING(ring, 0x00000000);
 283                 OUT_RING(ring, 0x00000000);
 284                 OUT_RING(ring, 0x00000000);
 285
 286                 OUT_PKT4(ring, REG_A5XX_GRAS_2D_DST_INFO, 1);
 287                 OUT_RING(ring, A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(RB5_R8_UNORM) |
 288                                 A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(WZYX));
 289
 290                 /*
 291                  * Blit command:
 292                  */
 293                 OUT_PKT7(ring, CP_BLIT, 5);
 294                 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_COPY));
 295                 OUT_RING(ring, CP_BLIT_1_SRC_X1(sshift) | CP_BLIT_1_SRC_Y1(0));
 296                 OUT_RING(ring, CP_BLIT_2_SRC_X2(sshift+w-1) | CP_BLIT_2_SRC_Y2(0));
 297                 OUT_RING(ring, CP_BLIT_3_DST_X1(dshift) | CP_BLIT_3_DST_Y1(0));
 298                 OUT_RING(ring, CP_BLIT_4_DST_X2(dshift+w-1) | CP_BLIT_4_DST_Y2(0));
 299
 300                 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
 301                 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(END2D));
 302
 303                 OUT_WFI5(ring);
 304         }
 305 }
 306
 307 static void
 308 emit_blit(struct fd_ringbuffer *ring, const struct pipe_blit_info *info)
 309 {
 310         const struct pipe_box *sbox = &info->src.box;
 311         const struct pipe_box *dbox = &info->dst.box;
 312         struct fd_resource *src, *dst;
 313         struct fd_resource_slice *sslice, *dslice;
 314         enum a5xx_color_fmt sfmt, dfmt;
 315         enum a3xx_color_swap sswap, dswap;
 316         unsigned ssize, dsize, spitch, dpitch;
 317         unsigned sx1, sy1, sx2, sy2;
 318         unsigned dx1, dy1, dx2, dy2;
 319
 320         src = fd_resource(info->src.resource);
 321         dst = fd_resource(info->dst.resource);
 322
 323         sslice = fd_resource_slice(src, info->src.level);
 324         dslice = fd_resource_slice(dst, info->dst.level);
 325
 326         sfmt = fd5_pipe2color(info->src.format);
 327         dfmt = fd5_pipe2color(info->dst.format);
 328
 329         sswap = fd5_pipe2swap(info->src.format);
 330         dswap = fd5_pipe2swap(info->dst.format);
 331
 332         spitch = sslice->pitch * src->cpp;
 333         dpitch = dslice->pitch * dst->cpp;
 334
 335         sx1 = sbox->x;
 336         sy1 = sbox->y;
 337         sx2 = sbox->x + sbox->width - 1;
 338         sy2 = sbox->y + sbox->height - 1;
 339
 340         dx1 = dbox->x;
 341         dy1 = dbox->y;
 342         dx2 = dbox->x + dbox->width - 1;
 343         dy2 = dbox->y + dbox->height - 1;
 344
 345         if (info->src.resource->target == PIPE_TEXTURE_3D)
 346                 ssize = sslice->size0;
 347         else
 348                 ssize = src->layer_size;
 349
 350         if (info->dst.resource->target == PIPE_TEXTURE_3D)
 351                 dsize = dslice->size0;
 352         else
 353                 dsize = dst->layer_size;
 354
 355         for (unsigned i = 0; i < info->dst.box.depth; i++) {
 356                 unsigned soff = fd_resource_offset(src, info->src.level, sbox->z + i);
 357                 unsigned doff = fd_resource_offset(dst, info->dst.level, dbox->z + i);
 358
 359                 debug_assert((soff + (sbox->height * spitch)) <= fd_bo_size(src->bo));
 360                 debug_assert((doff + (dbox->height * dpitch)) <= fd_bo_size(dst->bo));
 361
 362                 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
 363                 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(BLIT2D));
 364
 365                 /*
 366                  * Emit source:
 367                  */
 368                 OUT_PKT4(ring, REG_A5XX_RB_2D_SRC_INFO, 9);
 369                 OUT_RING(ring, A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
 370                                 A5XX_RB_2D_SRC_INFO_COLOR_SWAP(sswap));
 371                 OUT_RELOC(ring, src->bo, soff, 0, 0);    /* RB_2D_SRC_LO/HI */
 372                 OUT_RING(ring, A5XX_RB_2D_SRC_SIZE_PITCH(spitch) |
 373                                 A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(ssize));
 374                 OUT_RING(ring, 0x00000000);
 375                 OUT_RING(ring, 0x00000000);
 376                 OUT_RING(ring, 0x00000000);
 377                 OUT_RING(ring, 0x00000000);
 378                 OUT_RING(ring, 0x00000000);
 379
 380                 OUT_PKT4(ring, REG_A5XX_GRAS_2D_SRC_INFO, 1);
 381                 OUT_RING(ring, A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(sfmt) |
 382                                 A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(sswap));
 383
 384                 /*
 385                  * Emit destination:
 386                  */
 387                 OUT_PKT4(ring, REG_A5XX_RB_2D_DST_INFO, 9);
 388                 OUT_RING(ring, A5XX_RB_2D_DST_INFO_COLOR_FORMAT(dfmt) |
 389                                 A5XX_RB_2D_DST_INFO_COLOR_SWAP(dswap));
 390                 OUT_RELOCW(ring, dst->bo, doff, 0, 0);   /* RB_2D_DST_LO/HI */
 391                 OUT_RING(ring, A5XX_RB_2D_DST_SIZE_PITCH(dpitch) |
 392                                 A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(dsize));
 393                 OUT_RING(ring, 0x00000000);
 394                 OUT_RING(ring, 0x00000000);
 395                 OUT_RING(ring, 0x00000000);
 396                 OUT_RING(ring, 0x00000000);
 397                 OUT_RING(ring, 0x00000000);
 398
 399                 OUT_PKT4(ring, REG_A5XX_GRAS_2D_DST_INFO, 1);
 400                 OUT_RING(ring, A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(dfmt) |
 401                                 A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(dswap));
 402
 403                 /*
 404                  * Blit command:
 405                  */
 406                 OUT_PKT7(ring, CP_BLIT, 5);
 407                 OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_COPY));
 408                 OUT_RING(ring, CP_BLIT_1_SRC_X1(sx1) | CP_BLIT_1_SRC_Y1(sy1));
 409                 OUT_RING(ring, CP_BLIT_2_SRC_X2(sx2) | CP_BLIT_2_SRC_Y2(sy2));
 410                 OUT_RING(ring, CP_BLIT_3_DST_X1(dx1) | CP_BLIT_3_DST_Y1(dy1));
 411                 OUT_RING(ring, CP_BLIT_4_DST_X2(dx2) | CP_BLIT_4_DST_Y2(dy2));
 412
 413                 OUT_PKT7(ring, CP_SET_RENDER_MODE, 1);
 414                 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(END2D));
 415         }
 416 }
 417
 418 void
 419 fd5_blitter_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
 420 {
 421         struct fd_batch *batch;
 422
 423         if (!can_do_blit(info)) {
 424                 fd_blitter_blit(ctx, info);
 425                 return;
 426         }
 427
 428         batch = fd_batch_create(ctx, true);
 429
 430         fd5_emit_restore(batch, batch->draw);
 431         fd5_emit_lrz_flush(batch->draw);
 432
 433         emit_setup(batch->draw);
 434
 435         if ((info->src.resource->target == PIPE_BUFFER) &&
 436                         (info->dst.resource->target == PIPE_BUFFER)) {
 437                 emit_blit_buffer(batch->draw, info);
 438         } else {
 439                 /* I don't *think* we need to handle blits between buffer <-> !buffer */
 440                 debug_assert(info->src.resource->target != PIPE_BUFFER);
 441                 debug_assert(info->dst.resource->target != PIPE_BUFFER);
 442                 emit_blit(batch->draw, info);
 443         }
 444         fd_resource(info->dst.resource)->valid = true;
 445         batch->needs_flush = true;
 446
 447         fd_batch_flush(batch, false, false);
 448 }