2 * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
29 #include "freedreno_resource.h"
31 #include "fd5_compute.h"
32 #include "fd5_context.h"
35 struct fd5_compute_stateobj
{
36 struct ir3_shader
*shader
;
41 fd5_create_compute_state(struct pipe_context
*pctx
,
42 const struct pipe_compute_state
*cso
)
44 struct fd_context
*ctx
= fd_context(pctx
);
46 /* req_input_mem will only be non-zero for cl kernels (ie. clover).
47 * This isn't a perfect test because I guess it is possible (but
48 * uncommon) for none for the kernel parameters to be a global,
49 * but ctx->set_global_bindings() can't fail, so this is the next
50 * best place to fail if we need a newer version of kernel driver:
52 if ((cso
->req_input_mem
> 0) &&
53 fd_device_version(ctx
->dev
) < FD_VERSION_BO_IOVA
) {
57 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
58 struct fd5_compute_stateobj
*so
= CALLOC_STRUCT(fd5_compute_stateobj
);
59 so
->shader
= ir3_shader_create_compute(compiler
, cso
, &ctx
->debug
);
64 fd5_delete_compute_state(struct pipe_context
*pctx
, void *hwcso
)
66 struct fd5_compute_stateobj
*so
= hwcso
;
67 ir3_shader_destroy(so
->shader
);
71 /* maybe move to fd5_program? */
73 cs_program_emit(struct fd_ringbuffer
*ring
, struct ir3_shader_variant
*v
,
74 const struct pipe_grid_info
*info
)
76 const unsigned *local_size
= info
->block
;
77 const struct ir3_info
*i
= &v
->info
;
78 enum a3xx_threadsize thrsz
;
79 unsigned instrlen
= v
->instrlen
;
81 /* if shader is more than 32*16 instructions, don't preload it. Similar
82 * to the combined restriction of 64*16 for VS+FS
87 /* maybe the limit should be 1024.. basically if we can't have full
88 * occupancy, use TWO_QUAD mode to reduce divergence penalty.
90 if ((local_size
[0] * local_size
[1] * local_size
[2]) < 512) {
96 OUT_PKT4(ring
, REG_A5XX_SP_SP_CNTL
, 1);
97 OUT_RING(ring
, 0x00000000); /* SP_SP_CNTL */
99 OUT_PKT4(ring
, REG_A5XX_HLSQ_CONTROL_0_REG
, 1);
100 OUT_RING(ring
, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(TWO_QUADS
) |
101 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(thrsz
) |
102 0x00000880 /* XXX */);
104 OUT_PKT4(ring
, REG_A5XX_SP_CS_CTRL_REG0
, 1);
105 OUT_RING(ring
, A5XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz
) |
106 A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i
->max_half_reg
+ 1) |
107 A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i
->max_reg
+ 1) |
108 A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
111 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CONFIG
, 1);
112 OUT_RING(ring
, A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(0) |
113 A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(0) |
114 A5XX_HLSQ_CS_CONFIG_ENABLED
);
116 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CNTL
, 1);
117 OUT_RING(ring
, A5XX_HLSQ_CS_CNTL_INSTRLEN(instrlen
) |
118 COND(v
->has_ssbo
, A5XX_HLSQ_CS_CNTL_SSBO_ENABLE
));
120 OUT_PKT4(ring
, REG_A5XX_SP_CS_CONFIG
, 1);
121 OUT_RING(ring
, A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(0) |
122 A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(0) |
123 A5XX_SP_CS_CONFIG_ENABLED
);
125 unsigned constlen
= align(v
->constlen
, 4) / 4;
126 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CONSTLEN
, 2);
127 OUT_RING(ring
, constlen
); /* HLSQ_CS_CONSTLEN */
128 OUT_RING(ring
, instrlen
); /* HLSQ_CS_INSTRLEN */
130 OUT_PKT4(ring
, REG_A5XX_SP_CS_OBJ_START_LO
, 2);
131 OUT_RELOC(ring
, v
->bo
, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
133 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
134 OUT_RING(ring
, 0x1f00000);
136 uint32_t local_invocation_id
, work_group_id
;
137 local_invocation_id
= ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
138 work_group_id
= ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
140 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CNTL_0
, 2);
141 OUT_RING(ring
, A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
142 A5XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
143 A5XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
144 A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
145 OUT_RING(ring
, 0x1); /* HLSQ_CS_CNTL_1 */
148 fd5_emit_shader(ring
, v
);
152 emit_setup(struct fd_context
*ctx
)
154 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
156 fd5_emit_restore(ctx
->batch
, ring
);
157 fd5_emit_lrz_flush(ring
);
159 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
162 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
163 OUT_RING(ring
, UNK_19
);
165 OUT_PKT4(ring
, REG_A5XX_PC_POWER_CNTL
, 1);
166 OUT_RING(ring
, 0x00000003); /* PC_POWER_CNTL */
168 OUT_PKT4(ring
, REG_A5XX_VFD_POWER_CNTL
, 1);
169 OUT_RING(ring
, 0x00000003); /* VFD_POWER_CNTL */
171 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
172 fd_wfi(ctx
->batch
, ring
);
173 OUT_PKT4(ring
, REG_A5XX_RB_CCU_CNTL
, 1);
174 OUT_RING(ring
, 0x10000000); /* RB_CCU_CNTL */
176 OUT_PKT4(ring
, REG_A5XX_RB_CNTL
, 1);
177 OUT_RING(ring
, A5XX_RB_CNTL_BYPASS
);
181 fd5_launch_grid(struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
183 struct fd5_compute_stateobj
*so
= ctx
->compute
;
184 struct ir3_shader_key key
= {0};
185 struct ir3_shader_variant
*v
;
186 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
187 unsigned i
, nglobal
= 0;
191 v
= ir3_shader_variant(so
->shader
, key
, &ctx
->debug
);
195 if (ctx
->dirty_shader
[PIPE_SHADER_COMPUTE
] & FD_DIRTY_SHADER_PROG
)
196 cs_program_emit(ring
, v
, info
);
198 fd5_emit_cs_state(ctx
, ring
, v
);
199 ir3_emit_cs_consts(v
, ring
, ctx
, info
);
201 foreach_bit(i
, ctx
->global_bindings
.enabled_mask
)
205 /* global resources don't otherwise get an OUT_RELOC(), since
206 * the raw ptr address is emitted ir ir3_emit_cs_consts().
207 * So to make the kernel aware that these buffers are referenced
208 * by the batch, emit dummy reloc's as part of a no-op packet
211 OUT_PKT7(ring
, CP_NOP
, 2 * nglobal
);
212 foreach_bit(i
, ctx
->global_bindings
.enabled_mask
) {
213 struct pipe_resource
*prsc
= ctx
->global_bindings
.buf
[i
];
214 OUT_RELOCW(ring
, fd_resource(prsc
)->bo
, 0, 0, 0);
218 const unsigned *local_size
= info
->block
; // v->shader->nir->info->cs.local_size;
219 const unsigned *num_groups
= info
->grid
;
220 /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
221 const unsigned work_dim
= info
->work_dim
? info
->work_dim
: 3;
222 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_NDRANGE_0
, 7);
223 OUT_RING(ring
, A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim
) |
224 A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size
[0] - 1) |
225 A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size
[1] - 1) |
226 A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size
[2] - 1));
227 OUT_RING(ring
, A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size
[0] * num_groups
[0]));
228 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
229 OUT_RING(ring
, A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size
[1] * num_groups
[1]));
230 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
231 OUT_RING(ring
, A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size
[2] * num_groups
[2]));
232 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
234 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_KERNEL_GROUP_X
, 3);
235 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_X */
236 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
237 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
239 if (info
->indirect
) {
240 struct fd_resource
*rsc
= fd_resource(info
->indirect
);
242 fd5_emit_flush(ctx
, ring
);
244 OUT_PKT7(ring
, CP_EXEC_CS_INDIRECT
, 4);
245 OUT_RING(ring
, 0x00000000);
246 OUT_RELOC(ring
, rsc
->bo
, info
->indirect_offset
, 0, 0); /* ADDR_LO/HI */
247 OUT_RING(ring
, A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
248 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
249 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
251 OUT_PKT7(ring
, CP_EXEC_CS
, 4);
252 OUT_RING(ring
, 0x00000000);
253 OUT_RING(ring
, CP_EXEC_CS_1_NGROUPS_X(info
->grid
[0]));
254 OUT_RING(ring
, CP_EXEC_CS_2_NGROUPS_Y(info
->grid
[1]));
255 OUT_RING(ring
, CP_EXEC_CS_3_NGROUPS_Z(info
->grid
[2]));
260 fd5_compute_init(struct pipe_context
*pctx
)
262 struct fd_context
*ctx
= fd_context(pctx
);
263 ctx
->launch_grid
= fd5_launch_grid
;
264 pctx
->create_compute_state
= fd5_create_compute_state
;
265 pctx
->delete_compute_state
= fd5_delete_compute_state
;