src/gallium/drivers/freedreno/a5xx/fd5_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_prim.h"
  31
  32 #include "freedreno_state.h"
  33 #include "freedreno_resource.h"
  34
  35 #include "fd5_draw.h"
  36 #include "fd5_context.h"
  37 #include "fd5_emit.h"
  38 #include "fd5_program.h"
  39 #include "fd5_format.h"
  40 #include "fd5_zsa.h"
  41
  42
  43 static void
  44 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  45                 struct fd5_emit *emit)
  46 {
  47         const struct pipe_draw_info *info = emit->info;
  48         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  49
  50         fd5_emit_state(ctx, ring, emit);
  51
  52         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  53                 fd5_emit_vertex_bufs(ring, emit);
  54
  55         OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
  56         OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  57         OUT_RING(ring, info->start_instance);   /* ??? UNKNOWN_2209 */
  58
  59         OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
  60         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  61                         info->restart_index : 0xffffffff);
  62
  63         fd5_emit_render_cntl(ctx, false);
  64         fd5_draw_emit(ctx->batch, ring, primtype,
  65                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  66                         info);
  67 }
  68
  69 /* fixup dirty shader state in case some "unrelated" (from the state-
  70  * tracker's perspective) state change causes us to switch to a
  71  * different variant.
  72  */
  73 static void
  74 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  75 {
  76         struct fd5_context *fd5_ctx = fd5_context(ctx);
  77         struct ir3_shader_key *last_key = &fd5_ctx->last_key;
  78
  79         if (!ir3_shader_key_equal(last_key, key)) {
  80                 if (ir3_shader_key_changes_fs(last_key, key)) {
  81                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
  82                         ctx->dirty |= FD_DIRTY_PROG;
  83                 }
  84
  85                 if (ir3_shader_key_changes_vs(last_key, key)) {
  86                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
  87                         ctx->dirty |= FD_DIRTY_PROG;
  88                 }
  89
  90                 fd5_ctx->last_key = *key;
  91         }
  92 }
  93
  94 static bool
  95 fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
  96 {
  97         struct fd5_context *fd5_ctx = fd5_context(ctx);
  98         struct fd5_emit emit = {
  99                 .debug = &ctx->debug,
 100                 .vtx  = &ctx->vtx,
 101                 .prog = &ctx->prog,
 102                 .info = info,
 103                 .key = {
 104                         .color_two_side = ctx->rasterizer->light_twoside,
 105                         .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 106                         .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 107                         .rasterflat = ctx->rasterizer->flatshade,
 108                         .half_precision = ctx->in_blit &&
 109                                         fd_half_precision(&ctx->batch->framebuffer),
 110                         .ucp_enables = ctx->rasterizer->clip_plane_enable,
 111                         .has_per_samp = (fd5_ctx->fsaturate || fd5_ctx->vsaturate ||
 112                                         fd5_ctx->fastc_srgb || fd5_ctx->vastc_srgb),
 113                         .vsaturate_s = fd5_ctx->vsaturate_s,
 114                         .vsaturate_t = fd5_ctx->vsaturate_t,
 115                         .vsaturate_r = fd5_ctx->vsaturate_r,
 116                         .fsaturate_s = fd5_ctx->fsaturate_s,
 117                         .fsaturate_t = fd5_ctx->fsaturate_t,
 118                         .fsaturate_r = fd5_ctx->fsaturate_r,
 119                         .vastc_srgb = fd5_ctx->vastc_srgb,
 120                         .fastc_srgb = fd5_ctx->fastc_srgb,
 121                 },
 122                 .rasterflat = ctx->rasterizer->flatshade,
 123                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 124                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 125         };
 126
 127         fixup_shader_state(ctx, &emit.key);
 128
 129         unsigned dirty = ctx->dirty;
 130
 131         /* do regular pass first, since that is more likely to fail compiling: */
 132
 133         if (!(fd5_emit_get_vp(&emit) && fd5_emit_get_fp(&emit)))
 134                 return false;
 135
 136         emit.key.binning_pass = false;
 137         emit.dirty = dirty;
 138
 139         draw_impl(ctx, ctx->batch->draw, &emit);
 140
 141 //      /* and now binning pass: */
 142 //      emit.key.binning_pass = true;
 143 //      emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 144 //      emit.vp = NULL;   /* we changed key so need to refetch vp */
 145 //      emit.fp = NULL;
 146 //      draw_impl(ctx, ctx->batch->binning, &emit);
 147
 148         if (emit.streamout_mask) {
 149                 struct fd_ringbuffer *ring = ctx->batch->draw;
 150
 151                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 152                         if (emit.streamout_mask & (1 << i)) {
 153                                 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 154                                 OUT_RING(ring, FLUSH_SO_0 + i);
 155                         }
 156                 }
 157         }
 158
 159         fd_context_all_clean(ctx);
 160
 161         return true;
 162 }
 163
 164 static void
 165 fd5_clear(struct fd_context *ctx, unsigned buffers,
 166                 const union pipe_color_union *color, double depth, unsigned stencil)
 167 {
 168         struct fd_ringbuffer *ring = ctx->batch->draw;
 169         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 170         struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 171
 172         /* TODO handle scissor.. or fallback to slow-clear? */
 173
 174         ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
 175         ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
 176         ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
 177         ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
 178
 179         fd5_emit_render_cntl(ctx, true);
 180
 181         if (buffers & PIPE_CLEAR_COLOR) {
 182                 for (int i = 0; i < pfb->nr_cbufs; i++) {
 183                         union util_color uc = {0};
 184
 185                         if (!pfb->cbufs[i])
 186                                 continue;
 187
 188                         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
 189                                 continue;
 190
 191                         enum pipe_format pfmt = pfb->cbufs[i]->format;
 192
 193                         // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
 194                         union pipe_color_union swapped;
 195                         switch (fd5_pipe2swap(pfmt)) {
 196                         case WZYX:
 197                                 swapped.ui[0] = color->ui[0];
 198                                 swapped.ui[1] = color->ui[1];
 199                                 swapped.ui[2] = color->ui[2];
 200                                 swapped.ui[3] = color->ui[3];
 201                                 break;
 202                         case WXYZ:
 203                                 swapped.ui[2] = color->ui[0];
 204                                 swapped.ui[1] = color->ui[1];
 205                                 swapped.ui[0] = color->ui[2];
 206                                 swapped.ui[3] = color->ui[3];
 207                                 break;
 208                         case ZYXW:
 209                                 swapped.ui[3] = color->ui[0];
 210                                 swapped.ui[0] = color->ui[1];
 211                                 swapped.ui[1] = color->ui[2];
 212                                 swapped.ui[2] = color->ui[3];
 213                                 break;
 214                         case XYZW:
 215                                 swapped.ui[3] = color->ui[0];
 216                                 swapped.ui[2] = color->ui[1];
 217                                 swapped.ui[1] = color->ui[2];
 218                                 swapped.ui[0] = color->ui[3];
 219                                 break;
 220                         }
 221
 222                         if (util_format_is_pure_uint(pfmt)) {
 223                                 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
 224                         } else if (util_format_is_pure_sint(pfmt)) {
 225                                 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
 226                         } else {
 227                                 util_pack_color(swapped.f, pfmt, &uc);
 228                         }
 229
 230                         OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
 231                         OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i));
 232
 233                         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
 234                         OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
 235                                         A5XX_RB_CLEAR_CNTL_MASK(0xf));
 236
 237                         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4);
 238                         OUT_RING(ring, uc.ui[0]);  /* RB_CLEAR_COLOR_DW0 */
 239                         OUT_RING(ring, uc.ui[1]);  /* RB_CLEAR_COLOR_DW1 */
 240                         OUT_RING(ring, uc.ui[2]);  /* RB_CLEAR_COLOR_DW2 */
 241                         OUT_RING(ring, uc.ui[3]);  /* RB_CLEAR_COLOR_DW3 */
 242
 243                         fd5_emit_blit(ctx, ring);
 244                 }
 245         }
 246
 247         if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
 248                 uint32_t clear =
 249                         util_pack_z_stencil(pfb->zsbuf->format, depth, stencil);
 250                 uint32_t mask = 0;
 251
 252                 if (buffers & PIPE_CLEAR_DEPTH)
 253                         mask |= 0x1;
 254
 255                 if (buffers & PIPE_CLEAR_STENCIL)
 256                         mask |= 0x2;
 257
 258                 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
 259                 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS));
 260
 261                 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
 262                 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
 263                                 A5XX_RB_CLEAR_CNTL_MASK(mask));
 264
 265                 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
 266                 OUT_RING(ring, clear);    /* RB_CLEAR_COLOR_DW0 */
 267
 268                 fd5_emit_blit(ctx, ring);
 269         }
 270
 271         /* disable fast clear to not interfere w/ gmem->mem, etc.. */
 272         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
 273         OUT_RING(ring, 0x00000000);   /* RB_CLEAR_CNTL */
 274 }
 275
 276 void
 277 fd5_draw_init(struct pipe_context *pctx)
 278 {
 279         struct fd_context *ctx = fd_context(pctx);
 280         ctx->draw_vbo = fd5_draw_vbo;
 281         ctx->clear = fd5_clear;
 282 }