src/gallium/drivers/freedreno/a5xx/fd5_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "pipe/p_state.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/u_prim.h"
  31
  32 #include "freedreno_state.h"
  33 #include "freedreno_resource.h"
  34
  35 #include "fd5_draw.h"
  36 #include "fd5_context.h"
  37 #include "fd5_emit.h"
  38 #include "fd5_program.h"
  39 #include "fd5_format.h"
  40 #include "fd5_zsa.h"
  41
  42
  43 static void
  44 draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
  45                 struct fd5_emit *emit, unsigned index_offset)
  46 {
  47         const struct pipe_draw_info *info = emit->info;
  48         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
  49
  50         fd5_emit_state(ctx, ring, emit);
  51
  52         if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
  53                 fd5_emit_vertex_bufs(ring, emit);
  54
  55         OUT_PKT4(ring, REG_A5XX_VFD_INDEX_OFFSET, 2);
  56         OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
  57         OUT_RING(ring, info->start_instance);   /* ??? UNKNOWN_2209 */
  58
  59         OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
  60         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
  61                         info->restart_index : 0xffffffff);
  62
  63         fd5_emit_render_cntl(ctx, false, emit->key.binning_pass);
  64         fd5_draw_emit(ctx->batch, ring, primtype,
  65                         emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
  66                         info, index_offset);
  67 }
  68
  69 /* fixup dirty shader state in case some "unrelated" (from the state-
  70  * tracker's perspective) state change causes us to switch to a
  71  * different variant.
  72  */
  73 static void
  74 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
  75 {
  76         struct fd5_context *fd5_ctx = fd5_context(ctx);
  77         struct ir3_shader_key *last_key = &fd5_ctx->last_key;
  78
  79         if (!ir3_shader_key_equal(last_key, key)) {
  80                 if (ir3_shader_key_changes_fs(last_key, key)) {
  81                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
  82                         ctx->dirty |= FD_DIRTY_PROG;
  83                 }
  84
  85                 if (ir3_shader_key_changes_vs(last_key, key)) {
  86                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
  87                         ctx->dirty |= FD_DIRTY_PROG;
  88                 }
  89
  90                 fd5_ctx->last_key = *key;
  91         }
  92 }
  93
  94 static bool
  95 fd5_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
  96              unsigned index_offset)
  97 {
  98         struct fd5_context *fd5_ctx = fd5_context(ctx);
  99         struct fd5_emit emit = {
 100                 .debug = &ctx->debug,
 101                 .vtx  = &ctx->vtx,
 102                 .prog = &ctx->prog,
 103                 .info = info,
 104                 .key = {
 105                         .color_two_side = ctx->rasterizer->light_twoside,
 106                         .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 107                         .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 108                         .rasterflat = ctx->rasterizer->flatshade,
 109                         .half_precision = ctx->in_blit &&
 110                                         fd_half_precision(&ctx->batch->framebuffer),
 111                         .ucp_enables = ctx->rasterizer->clip_plane_enable,
 112                         .has_per_samp = (fd5_ctx->fsaturate || fd5_ctx->vsaturate ||
 113                                         fd5_ctx->fastc_srgb || fd5_ctx->vastc_srgb),
 114                         .vsaturate_s = fd5_ctx->vsaturate_s,
 115                         .vsaturate_t = fd5_ctx->vsaturate_t,
 116                         .vsaturate_r = fd5_ctx->vsaturate_r,
 117                         .fsaturate_s = fd5_ctx->fsaturate_s,
 118                         .fsaturate_t = fd5_ctx->fsaturate_t,
 119                         .fsaturate_r = fd5_ctx->fsaturate_r,
 120                         .vastc_srgb = fd5_ctx->vastc_srgb,
 121                         .fastc_srgb = fd5_ctx->fastc_srgb,
 122                 },
 123                 .rasterflat = ctx->rasterizer->flatshade,
 124                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 125                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 126         };
 127
 128         fixup_shader_state(ctx, &emit.key);
 129
 130         unsigned dirty = ctx->dirty;
 131
 132         /* do regular pass first, since that is more likely to fail compiling: */
 133
 134         if (!(fd5_emit_get_vp(&emit) && fd5_emit_get_fp(&emit)))
 135                 return false;
 136
 137         emit.key.binning_pass = false;
 138         emit.dirty = dirty;
 139
 140         draw_impl(ctx, ctx->batch->draw, &emit, index_offset);
 141
 142         /* and now binning pass: */
 143         emit.key.binning_pass = true;
 144         emit.dirty = dirty & ~(FD_DIRTY_BLEND);
 145         emit.vp = NULL;   /* we changed key so need to refetch vp */
 146         emit.fp = NULL;
 147         draw_impl(ctx, ctx->batch->binning, &emit, index_offset);
 148
 149         if (emit.streamout_mask) {
 150                 struct fd_ringbuffer *ring = ctx->batch->draw;
 151
 152                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 153                         if (emit.streamout_mask & (1 << i)) {
 154                                 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 155                                 OUT_RING(ring, FLUSH_SO_0 + i);
 156                         }
 157                 }
 158         }
 159
 160         fd_context_all_clean(ctx);
 161
 162         return true;
 163 }
 164
 165 static bool is_z32(enum pipe_format format)
 166 {
 167         switch (format) {
 168         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 169         case PIPE_FORMAT_Z32_UNORM:
 170         case PIPE_FORMAT_Z32_FLOAT:
 171                 return true;
 172         default:
 173                 return false;
 174         }
 175 }
 176
 177 static bool
 178 fd5_clear(struct fd_context *ctx, unsigned buffers,
 179                 const union pipe_color_union *color, double depth, unsigned stencil)
 180 {
 181         struct fd_ringbuffer *ring = ctx->batch->draw;
 182         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 183         struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
 184
 185         if ((buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) &&
 186                         is_z32(pfb->zsbuf->format))
 187                 return false;
 188
 189         /* TODO handle scissor.. or fallback to slow-clear? */
 190
 191         ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
 192         ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
 193         ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
 194         ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
 195
 196         fd5_emit_render_cntl(ctx, true, false);
 197
 198         if (buffers & PIPE_CLEAR_COLOR) {
 199                 for (int i = 0; i < pfb->nr_cbufs; i++) {
 200                         union util_color uc = {0};
 201
 202                         if (!pfb->cbufs[i])
 203                                 continue;
 204
 205                         if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
 206                                 continue;
 207
 208                         enum pipe_format pfmt = pfb->cbufs[i]->format;
 209
 210                         // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
 211                         union pipe_color_union swapped;
 212                         switch (fd5_pipe2swap(pfmt)) {
 213                         case WZYX:
 214                                 swapped.ui[0] = color->ui[0];
 215                                 swapped.ui[1] = color->ui[1];
 216                                 swapped.ui[2] = color->ui[2];
 217                                 swapped.ui[3] = color->ui[3];
 218                                 break;
 219                         case WXYZ:
 220                                 swapped.ui[2] = color->ui[0];
 221                                 swapped.ui[1] = color->ui[1];
 222                                 swapped.ui[0] = color->ui[2];
 223                                 swapped.ui[3] = color->ui[3];
 224                                 break;
 225                         case ZYXW:
 226                                 swapped.ui[3] = color->ui[0];
 227                                 swapped.ui[0] = color->ui[1];
 228                                 swapped.ui[1] = color->ui[2];
 229                                 swapped.ui[2] = color->ui[3];
 230                                 break;
 231                         case XYZW:
 232                                 swapped.ui[3] = color->ui[0];
 233                                 swapped.ui[2] = color->ui[1];
 234                                 swapped.ui[1] = color->ui[2];
 235                                 swapped.ui[0] = color->ui[3];
 236                                 break;
 237                         }
 238
 239                         if (util_format_is_pure_uint(pfmt)) {
 240                                 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
 241                         } else if (util_format_is_pure_sint(pfmt)) {
 242                                 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
 243                         } else {
 244                                 util_pack_color(swapped.f, pfmt, &uc);
 245                         }
 246
 247                         OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
 248                         OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i));
 249
 250                         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
 251                         OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
 252                                         A5XX_RB_CLEAR_CNTL_MASK(0xf));
 253
 254                         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 4);
 255                         OUT_RING(ring, uc.ui[0]);  /* RB_CLEAR_COLOR_DW0 */
 256                         OUT_RING(ring, uc.ui[1]);  /* RB_CLEAR_COLOR_DW1 */
 257                         OUT_RING(ring, uc.ui[2]);  /* RB_CLEAR_COLOR_DW2 */
 258                         OUT_RING(ring, uc.ui[3]);  /* RB_CLEAR_COLOR_DW3 */
 259
 260                         fd5_emit_blit(ctx, ring);
 261                 }
 262         }
 263
 264         if (pfb->zsbuf && (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))) {
 265                 uint32_t clear =
 266                         util_pack_z_stencil(pfb->zsbuf->format, depth, stencil);
 267                 uint32_t mask = 0;
 268
 269                 if (buffers & PIPE_CLEAR_DEPTH)
 270                         mask |= 0x1;
 271
 272                 if (buffers & PIPE_CLEAR_STENCIL)
 273                         mask |= 0x2;
 274
 275                 OUT_PKT4(ring, REG_A5XX_RB_BLIT_CNTL, 1);
 276                 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS));
 277
 278                 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
 279                 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
 280                                 A5XX_RB_CLEAR_CNTL_MASK(mask));
 281
 282                 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_COLOR_DW0, 1);
 283                 OUT_RING(ring, clear);    /* RB_CLEAR_COLOR_DW0 */
 284
 285                 fd5_emit_blit(ctx, ring);
 286         }
 287
 288         /* disable fast clear to not interfere w/ gmem->mem, etc.. */
 289         OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
 290         OUT_RING(ring, 0x00000000);   /* RB_CLEAR_CNTL */
 291
 292         return true;
 293 }
 294
 295 void
 296 fd5_draw_init(struct pipe_context *pctx)
 297 {
 298         struct fd_context *ctx = fd_context(pctx);
 299         ctx->draw_vbo = fd5_draw_vbo;
 300         ctx->clear = fd5_clear;
 301 }