2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_prim.h"
32 #include "freedreno_state.h"
33 #include "freedreno_resource.h"
36 #include "fd5_context.h"
38 #include "fd5_program.h"
39 #include "fd5_format.h"
44 draw_impl(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
45 struct fd5_emit
*emit
, unsigned index_offset
)
47 const struct pipe_draw_info
*info
= emit
->info
;
48 enum pc_di_primtype primtype
= ctx
->primtypes
[info
->mode
];
50 fd5_emit_state(ctx
, ring
, emit
);
52 if (emit
->dirty
& (FD_DIRTY_VTXBUF
| FD_DIRTY_VTXSTATE
))
53 fd5_emit_vertex_bufs(ring
, emit
);
55 OUT_PKT4(ring
, REG_A5XX_VFD_INDEX_OFFSET
, 2);
56 OUT_RING(ring
, info
->index_size
? info
->index_bias
: info
->start
); /* VFD_INDEX_OFFSET */
57 OUT_RING(ring
, info
->start_instance
); /* VFD_INSTANCE_START_OFFSET */
59 OUT_PKT4(ring
, REG_A5XX_PC_RESTART_INDEX
, 1);
60 OUT_RING(ring
, info
->primitive_restart
? /* PC_RESTART_INDEX */
61 info
->restart_index
: 0xffffffff);
63 fd5_emit_render_cntl(ctx
, false, emit
->binning_pass
);
64 fd5_draw_emit(ctx
->batch
, ring
, primtype
,
65 emit
->binning_pass
? IGNORE_VISIBILITY
: USE_VISIBILITY
,
69 /* fixup dirty shader state in case some "unrelated" (from the state-
70 * tracker's perspective) state change causes us to switch to a
74 fixup_shader_state(struct fd_context
*ctx
, struct ir3_shader_key
*key
)
76 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
77 struct ir3_shader_key
*last_key
= &fd5_ctx
->last_key
;
79 if (!ir3_shader_key_equal(last_key
, key
)) {
80 if (ir3_shader_key_changes_fs(last_key
, key
)) {
81 ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] |= FD_DIRTY_SHADER_PROG
;
82 ctx
->dirty
|= FD_DIRTY_PROG
;
85 if (ir3_shader_key_changes_vs(last_key
, key
)) {
86 ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] |= FD_DIRTY_SHADER_PROG
;
87 ctx
->dirty
|= FD_DIRTY_PROG
;
90 fd5_ctx
->last_key
= *key
;
95 fd5_draw_vbo(struct fd_context
*ctx
, const struct pipe_draw_info
*info
,
96 unsigned index_offset
)
98 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
99 struct fd5_emit emit
= {
100 .debug
= &ctx
->debug
,
105 .color_two_side
= ctx
->rasterizer
->light_twoside
,
106 .vclamp_color
= ctx
->rasterizer
->clamp_vertex_color
,
107 .fclamp_color
= ctx
->rasterizer
->clamp_fragment_color
,
108 .rasterflat
= ctx
->rasterizer
->flatshade
,
109 .ucp_enables
= ctx
->rasterizer
->clip_plane_enable
,
110 .has_per_samp
= (fd5_ctx
->fsaturate
|| fd5_ctx
->vsaturate
||
111 fd5_ctx
->fastc_srgb
|| fd5_ctx
->vastc_srgb
),
112 .vsaturate_s
= fd5_ctx
->vsaturate_s
,
113 .vsaturate_t
= fd5_ctx
->vsaturate_t
,
114 .vsaturate_r
= fd5_ctx
->vsaturate_r
,
115 .fsaturate_s
= fd5_ctx
->fsaturate_s
,
116 .fsaturate_t
= fd5_ctx
->fsaturate_t
,
117 .fsaturate_r
= fd5_ctx
->fsaturate_r
,
118 .vastc_srgb
= fd5_ctx
->vastc_srgb
,
119 .fastc_srgb
= fd5_ctx
->fastc_srgb
,
120 .vsamples
= ctx
->tex
[PIPE_SHADER_VERTEX
].samples
,
121 .fsamples
= ctx
->tex
[PIPE_SHADER_FRAGMENT
].samples
,
123 .rasterflat
= ctx
->rasterizer
->flatshade
,
124 .sprite_coord_enable
= ctx
->rasterizer
->sprite_coord_enable
,
125 .sprite_coord_mode
= ctx
->rasterizer
->sprite_coord_mode
,
128 fixup_shader_state(ctx
, &emit
.key
);
130 unsigned dirty
= ctx
->dirty
;
131 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(&emit
);
132 const struct ir3_shader_variant
*fp
= fd5_emit_get_fp(&emit
);
134 /* do regular pass first, since that is more likely to fail compiling: */
139 ctx
->stats
.vs_regs
+= ir3_shader_halfregs(vp
);
140 ctx
->stats
.fs_regs
+= ir3_shader_halfregs(fp
);
142 /* figure out whether we need to disable LRZ write for binning
143 * pass using draw pass's fp:
145 emit
.no_lrz_write
= fp
->writes_pos
|| fp
->no_earlyz
;
147 emit
.binning_pass
= false;
150 draw_impl(ctx
, ctx
->batch
->draw
, &emit
, index_offset
);
152 /* and now binning pass: */
153 emit
.binning_pass
= true;
154 emit
.dirty
= dirty
& ~(FD_DIRTY_BLEND
);
155 emit
.vs
= NULL
; /* we changed key so need to refetch vp */
157 draw_impl(ctx
, ctx
->batch
->binning
, &emit
, index_offset
);
159 if (emit
.streamout_mask
) {
160 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
162 for (unsigned i
= 0; i
< PIPE_MAX_SO_BUFFERS
; i
++) {
163 if (emit
.streamout_mask
& (1 << i
)) {
164 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
165 OUT_RING(ring
, FLUSH_SO_0
+ i
);
170 fd_context_all_clean(ctx
);
175 static bool is_z32(enum pipe_format format
)
178 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
179 case PIPE_FORMAT_Z32_UNORM
:
180 case PIPE_FORMAT_Z32_FLOAT
:
188 fd5_clear_lrz(struct fd_batch
*batch
, struct fd_resource
*zsbuf
, double depth
)
190 struct fd_ringbuffer
*ring
;
191 uint32_t clear
= util_pack_z(PIPE_FORMAT_Z16_UNORM
, depth
);
193 // TODO mid-frame clears (ie. app doing crazy stuff)?? Maybe worth
194 // splitting both clear and lrz clear out into their own rb's. And
195 // just throw away any draws prior to clear. (Anything not fullscreen
196 // clear, just fallback to generic path that treats it as a normal
199 if (!batch
->lrz_clear
) {
200 batch
->lrz_clear
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000, 0);
203 ring
= batch
->lrz_clear
;
207 OUT_PKT4(ring
, REG_A5XX_RB_CCU_CNTL
, 1);
208 OUT_RING(ring
, 0x10000000);
210 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
211 OUT_RING(ring
, 0x20fffff);
213 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CNTL
, 1);
214 OUT_RING(ring
, A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(0.0) |
215 COND(zsbuf
->base
.nr_samples
> 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE
));
217 OUT_PKT4(ring
, REG_A5XX_GRAS_CNTL
, 1);
218 OUT_RING(ring
, 0x00000000);
220 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_CNTL
, 1);
221 OUT_RING(ring
, 0x00000181);
223 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_CNTL
, 1);
224 OUT_RING(ring
, 0x00000000);
226 OUT_PKT4(ring
, REG_A5XX_RB_MRT_BUF_INFO(0), 5);
227 OUT_RING(ring
, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(RB5_R16_UNORM
) |
228 A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(TILE5_LINEAR
) |
229 A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(WZYX
));
230 OUT_RING(ring
, A5XX_RB_MRT_PITCH(zsbuf
->lrz_pitch
* 2));
231 OUT_RING(ring
, A5XX_RB_MRT_ARRAY_PITCH(fd_bo_size(zsbuf
->lrz
)));
232 OUT_RELOCW(ring
, zsbuf
->lrz
, 0x1000, 0, 0);
234 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_CNTL
, 1);
235 OUT_RING(ring
, 0x00000000);
237 OUT_PKT4(ring
, REG_A5XX_RB_DEST_MSAA_CNTL
, 1);
238 OUT_RING(ring
, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE
));
240 OUT_PKT4(ring
, REG_A5XX_RB_BLIT_CNTL
, 1);
241 OUT_RING(ring
, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0
));
243 OUT_PKT4(ring
, REG_A5XX_RB_CLEAR_CNTL
, 1);
244 OUT_RING(ring
, A5XX_RB_CLEAR_CNTL_FAST_CLEAR
|
245 A5XX_RB_CLEAR_CNTL_MASK(0xf));
247 OUT_PKT4(ring
, REG_A5XX_RB_CLEAR_COLOR_DW0
, 1);
248 OUT_RING(ring
, clear
); /* RB_CLEAR_COLOR_DW0 */
250 OUT_PKT4(ring
, REG_A5XX_VSC_RESOLVE_CNTL
, 2);
251 OUT_RING(ring
, A5XX_VSC_RESOLVE_CNTL_X(zsbuf
->lrz_width
) |
252 A5XX_VSC_RESOLVE_CNTL_Y(zsbuf
->lrz_height
));
253 OUT_RING(ring
, 0x00000000); // XXX UNKNOWN_0CDE
255 OUT_PKT4(ring
, REG_A5XX_RB_CNTL
, 1);
256 OUT_RING(ring
, A5XX_RB_CNTL_BYPASS
);
258 OUT_PKT4(ring
, REG_A5XX_RB_RESOLVE_CNTL_1
, 2);
259 OUT_RING(ring
, A5XX_RB_RESOLVE_CNTL_1_X(0) |
260 A5XX_RB_RESOLVE_CNTL_1_Y(0));
261 OUT_RING(ring
, A5XX_RB_RESOLVE_CNTL_2_X(zsbuf
->lrz_width
- 1) |
262 A5XX_RB_RESOLVE_CNTL_2_Y(zsbuf
->lrz_height
- 1));
264 fd5_emit_blit(batch
->ctx
, ring
);
268 fd5_clear(struct fd_context
*ctx
, unsigned buffers
,
269 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
271 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
272 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
274 if ((buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) &&
275 is_z32(pfb
->zsbuf
->format
))
278 fd5_emit_render_cntl(ctx
, true, false);
280 if (buffers
& PIPE_CLEAR_COLOR
) {
281 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
282 union util_color uc
= {0};
287 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
290 enum pipe_format pfmt
= pfb
->cbufs
[i
]->format
;
292 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
293 union pipe_color_union swapped
;
294 switch (fd5_pipe2swap(pfmt
)) {
296 swapped
.ui
[0] = color
->ui
[0];
297 swapped
.ui
[1] = color
->ui
[1];
298 swapped
.ui
[2] = color
->ui
[2];
299 swapped
.ui
[3] = color
->ui
[3];
302 swapped
.ui
[2] = color
->ui
[0];
303 swapped
.ui
[1] = color
->ui
[1];
304 swapped
.ui
[0] = color
->ui
[2];
305 swapped
.ui
[3] = color
->ui
[3];
308 swapped
.ui
[3] = color
->ui
[0];
309 swapped
.ui
[0] = color
->ui
[1];
310 swapped
.ui
[1] = color
->ui
[2];
311 swapped
.ui
[2] = color
->ui
[3];
314 swapped
.ui
[3] = color
->ui
[0];
315 swapped
.ui
[2] = color
->ui
[1];
316 swapped
.ui
[1] = color
->ui
[2];
317 swapped
.ui
[0] = color
->ui
[3];
321 util_pack_color_union(pfmt
, &uc
, &swapped
);
323 OUT_PKT4(ring
, REG_A5XX_RB_BLIT_CNTL
, 1);
324 OUT_RING(ring
, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0
+ i
));
326 OUT_PKT4(ring
, REG_A5XX_RB_CLEAR_CNTL
, 1);
327 OUT_RING(ring
, A5XX_RB_CLEAR_CNTL_FAST_CLEAR
|
328 A5XX_RB_CLEAR_CNTL_MASK(0xf));
330 OUT_PKT4(ring
, REG_A5XX_RB_CLEAR_COLOR_DW0
, 4);
331 OUT_RING(ring
, uc
.ui
[0]); /* RB_CLEAR_COLOR_DW0 */
332 OUT_RING(ring
, uc
.ui
[1]); /* RB_CLEAR_COLOR_DW1 */
333 OUT_RING(ring
, uc
.ui
[2]); /* RB_CLEAR_COLOR_DW2 */
334 OUT_RING(ring
, uc
.ui
[3]); /* RB_CLEAR_COLOR_DW3 */
336 fd5_emit_blit(ctx
, ring
);
340 if (pfb
->zsbuf
&& (buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
))) {
342 util_pack_z_stencil(pfb
->zsbuf
->format
, depth
, stencil
);
345 if (buffers
& PIPE_CLEAR_DEPTH
)
348 if (buffers
& PIPE_CLEAR_STENCIL
)
351 OUT_PKT4(ring
, REG_A5XX_RB_BLIT_CNTL
, 1);
352 OUT_RING(ring
, A5XX_RB_BLIT_CNTL_BUF(BLIT_ZS
));
354 OUT_PKT4(ring
, REG_A5XX_RB_CLEAR_CNTL
, 1);
355 OUT_RING(ring
, A5XX_RB_CLEAR_CNTL_FAST_CLEAR
|
356 A5XX_RB_CLEAR_CNTL_MASK(mask
));
358 OUT_PKT4(ring
, REG_A5XX_RB_CLEAR_COLOR_DW0
, 1);
359 OUT_RING(ring
, clear
); /* RB_CLEAR_COLOR_DW0 */
361 fd5_emit_blit(ctx
, ring
);
363 if (pfb
->zsbuf
&& (buffers
& PIPE_CLEAR_DEPTH
)) {
364 struct fd_resource
*zsbuf
= fd_resource(pfb
->zsbuf
->texture
);
366 zsbuf
->lrz_valid
= true;
367 fd5_clear_lrz(ctx
->batch
, zsbuf
, depth
);
372 /* disable fast clear to not interfere w/ gmem->mem, etc.. */
373 OUT_PKT4(ring
, REG_A5XX_RB_CLEAR_CNTL
, 1);
374 OUT_RING(ring
, 0x00000000); /* RB_CLEAR_CNTL */
380 fd5_draw_init(struct pipe_context
*pctx
)
382 struct fd_context
*ctx
= fd_context(pctx
);
383 ctx
->draw_vbo
= fd5_draw_vbo
;
384 ctx
->clear
= fd5_clear
;