2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
51 fd5_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
52 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
53 const uint32_t *dwords
, struct pipe_resource
*prsc
)
56 enum a4xx_state_src src
;
58 debug_assert((regid
% 4) == 0);
59 debug_assert((sizedwords
% 4) == 0);
69 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + sz
);
70 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
71 CP_LOAD_STATE4_0_STATE_SRC(src
) |
72 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
73 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords
/4));
75 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
76 OUT_RELOC(ring
, bo
, offset
,
77 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
), 0);
79 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
81 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
82 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
84 for (i
= 0; i
< sz
; i
++) {
85 OUT_RING(ring
, dwords
[i
]);
90 fd5_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
91 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
93 uint32_t anum
= align(num
, 2);
96 debug_assert((regid
% 4) == 0);
98 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (2 * anum
));
99 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
100 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
101 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
102 CP_LOAD_STATE4_0_NUM_UNIT(anum
/2));
103 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
104 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
105 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
107 for (i
= 0; i
< num
; i
++) {
110 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
112 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
115 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
116 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
120 for (; i
< anum
; i
++) {
121 OUT_RING(ring
, 0xffffffff);
122 OUT_RING(ring
, 0xffffffff);
126 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
127 * the same as a6xx then move this somewhere common ;-)
129 * Entry layout looks like (total size, 0x60 bytes):
131 * offset | description
132 * -------+-------------
149 * 0x28 | ?? maybe padding ??
158 * 0x38 | ?? maybe padding ??
160 * Some uncertainty, because not clear that this actually works properly
161 * with blob, so who knows..
164 struct PACKED bcolor_entry
{
175 #define FD5_BORDER_COLOR_SIZE 0x60
176 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
179 setup_border_colors(struct fd_texture_stateobj
*tex
, struct bcolor_entry
*entries
)
183 for (i
= 0; i
< tex
->num_samplers
; i
++) {
184 struct bcolor_entry
*e
= &entries
[i
];
185 struct pipe_sampler_state
*sampler
= tex
->samplers
[i
];
186 union pipe_color_union
*bc
;
191 bc
= &sampler
->border_color
;
196 * The border colors need to be swizzled in a particular
197 * format-dependent order. Even though samplers don't know about
198 * formats, we can assume that with a GL state tracker, there's a
199 * 1:1 correspondence between sampler and texture. Take advantage
202 if ((i
>= tex
->num_textures
) || !tex
->textures
[i
])
205 const struct util_format_description
*desc
=
206 util_format_description(tex
->textures
[i
]->format
);
208 for (j
= 0; j
< 4; j
++) {
209 int c
= desc
->swizzle
[j
];
214 if (desc
->channel
[c
].pure_integer
) {
218 e
->fp16
[j
] = util_float_to_half(f
);
219 e
->ui16
[j
] = bc
->ui
[c
];
220 e
->si16
[j
] = bc
->i
[c
];
221 e
->ui8
[j
] = bc
->ui
[c
];
222 e
->si8
[j
] = bc
->i
[c
];
227 e
->fp16
[j
] = util_float_to_half(f
);
228 e
->ui16
[j
] = f
* 65535.0;
229 e
->si16
[j
] = f
* 32767.5;
230 e
->ui8
[j
] = f
* 255.0;
231 e
->si8
[j
] = f
* 128.0;
236 memset(&e
->__pad0
, 0, sizeof(e
->__pad0
));
237 memset(&e
->__pad1
, 0, sizeof(e
->__pad1
));
243 emit_border_color(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
245 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
246 struct bcolor_entry
*entries
;
250 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD5_BORDER_COLOR_SIZE
);
252 u_upload_alloc(fd5_ctx
->border_color_uploader
,
253 0, FD5_BORDER_COLOR_UPLOAD_SIZE
,
254 FD5_BORDER_COLOR_UPLOAD_SIZE
, &off
,
255 &fd5_ctx
->border_color_buf
,
260 setup_border_colors(&ctx
->tex
[PIPE_SHADER_VERTEX
], &entries
[0]);
261 setup_border_colors(&ctx
->tex
[PIPE_SHADER_FRAGMENT
],
262 &entries
[ctx
->tex
[PIPE_SHADER_VERTEX
].num_samplers
]);
264 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
265 OUT_RELOC(ring
, fd_resource(fd5_ctx
->border_color_buf
)->bo
, off
, 0, 0);
267 u_upload_unmap(fd5_ctx
->border_color_uploader
);
271 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
272 enum a4xx_state_block sb
, struct fd_texture_stateobj
*tex
)
274 bool needs_border
= false;
275 unsigned bcolor_offset
= (sb
== SB4_FS_TEX
) ? ctx
->tex
[PIPE_SHADER_VERTEX
].num_samplers
: 0;
278 if (tex
->num_samplers
> 0) {
279 /* output sampler state: */
280 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (4 * tex
->num_samplers
));
281 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
282 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
283 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
284 CP_LOAD_STATE4_0_NUM_UNIT(tex
->num_samplers
));
285 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
) |
286 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
287 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
288 for (i
= 0; i
< tex
->num_samplers
; i
++) {
289 static const struct fd5_sampler_stateobj dummy_sampler
= {};
290 const struct fd5_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
291 fd5_sampler_stateobj(tex
->samplers
[i
]) :
293 OUT_RING(ring
, sampler
->texsamp0
);
294 OUT_RING(ring
, sampler
->texsamp1
);
295 OUT_RING(ring
, sampler
->texsamp2
|
296 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset
));
297 OUT_RING(ring
, sampler
->texsamp3
);
299 needs_border
|= sampler
->needs_border
;
303 if (tex
->num_textures
> 0) {
304 unsigned num_textures
= tex
->num_textures
;
306 /* emit texture state: */
307 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (12 * num_textures
));
308 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
309 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
310 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
311 CP_LOAD_STATE4_0_NUM_UNIT(num_textures
));
312 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
) |
313 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
314 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
315 for (i
= 0; i
< tex
->num_textures
; i
++) {
316 static const struct fd5_pipe_sampler_view dummy_view
= {};
317 const struct fd5_pipe_sampler_view
*view
= tex
->textures
[i
] ?
318 fd5_pipe_sampler_view(tex
->textures
[i
]) :
321 OUT_RING(ring
, view
->texconst0
);
322 OUT_RING(ring
, view
->texconst1
);
323 OUT_RING(ring
, view
->texconst2
);
324 OUT_RING(ring
, view
->texconst3
);
325 if (view
->base
.texture
) {
326 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
327 OUT_RELOC(ring
, rsc
->bo
, view
->offset
,
328 (uint64_t)view
->texconst5
<< 32, 0);
330 OUT_RING(ring
, 0x00000000);
331 OUT_RING(ring
, view
->texconst5
);
333 OUT_RING(ring
, view
->texconst6
);
334 OUT_RING(ring
, view
->texconst7
);
335 OUT_RING(ring
, view
->texconst8
);
336 OUT_RING(ring
, view
->texconst9
);
337 OUT_RING(ring
, view
->texconst10
);
338 OUT_RING(ring
, view
->texconst11
);
346 emit_ssbos(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
347 enum a4xx_state_block sb
, struct fd_shaderbuf_stateobj
*so
)
349 unsigned count
= util_last_bit(so
->enabled_mask
);
354 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (4 * count
));
355 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
356 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
357 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
358 CP_LOAD_STATE4_0_NUM_UNIT(count
));
359 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(0) |
360 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
361 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
362 for (unsigned i
= 0; i
< count
; i
++) {
363 struct pipe_shader_buffer
*buf
= &so
->sb
[i
];
365 struct fd_resource
*rsc
= fd_resource(buf
->buffer
);
366 OUT_RELOCW(ring
, rsc
->bo
, 0, 0, 0);
368 OUT_RING(ring
, 0x00000000);
369 OUT_RING(ring
, 0x00000000);
371 OUT_RING(ring
, 0x00000000);
372 OUT_RING(ring
, 0x00000000);
375 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (2 * count
));
376 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
377 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
378 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
379 CP_LOAD_STATE4_0_NUM_UNIT(count
));
380 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(1) |
381 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
382 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
383 for (unsigned i
= 0; i
< count
; i
++) {
384 struct pipe_shader_buffer
*buf
= &so
->sb
[i
];
386 // TODO maybe offset encoded somewhere here??
387 OUT_RING(ring
, (buf
->buffer_size
<< 16));
388 OUT_RING(ring
, 0x00000000);
391 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (2 * count
));
392 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
393 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
394 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
395 CP_LOAD_STATE4_0_NUM_UNIT(count
));
396 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(2) |
397 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
398 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
399 for (unsigned i
= 0; i
< count
; i
++) {
400 struct pipe_shader_buffer
*buf
= &so
->sb
[i
];
402 struct fd_resource
*rsc
= fd_resource(buf
->buffer
);
403 OUT_RELOCW(ring
, rsc
->bo
, 0, 0, 0);
405 OUT_RING(ring
, 0x00000000);
406 OUT_RING(ring
, 0x00000000);
412 fd5_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd5_emit
*emit
)
415 const struct fd_vertex_state
*vtx
= emit
->vtx
;
416 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
418 for (i
= 0, j
= 0; i
<= vp
->inputs_count
; i
++) {
419 if (vp
->inputs
[i
].sysval
)
421 if (vp
->inputs
[i
].compmask
) {
422 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
423 const struct pipe_vertex_buffer
*vb
=
424 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
425 struct fd_resource
*rsc
= fd_resource(vb
->buffer
.resource
);
426 enum pipe_format pfmt
= elem
->src_format
;
427 enum a5xx_vtx_fmt fmt
= fd5_pipe2vtx(pfmt
);
428 bool isint
= util_format_is_pure_integer(pfmt
);
429 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
430 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
431 debug_assert(fmt
!= ~0);
433 OUT_PKT4(ring
, REG_A5XX_VFD_FETCH(j
), 4);
434 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
435 OUT_RING(ring
, size
); /* VFD_FETCH[j].SIZE */
436 OUT_RING(ring
, vb
->stride
); /* VFD_FETCH[j].STRIDE */
438 OUT_PKT4(ring
, REG_A5XX_VFD_DECODE(j
), 2);
439 OUT_RING(ring
, A5XX_VFD_DECODE_INSTR_IDX(j
) |
440 A5XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
441 COND(elem
->instance_divisor
, A5XX_VFD_DECODE_INSTR_INSTANCED
) |
442 A5XX_VFD_DECODE_INSTR_UNK30
|
443 COND(!isint
, A5XX_VFD_DECODE_INSTR_FLOAT
));
444 OUT_RING(ring
, MAX2(1, elem
->instance_divisor
)); /* VFD_DECODE[j].STEP_RATE */
446 OUT_PKT4(ring
, REG_A5XX_VFD_DEST_CNTL(j
), 1);
447 OUT_RING(ring
, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
448 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp
->inputs
[i
].regid
));
454 OUT_PKT4(ring
, REG_A5XX_VFD_CONTROL_0
, 1);
455 OUT_RING(ring
, A5XX_VFD_CONTROL_0_VTXCNT(j
));
459 fd5_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
460 struct fd5_emit
*emit
)
462 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
463 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
464 const struct ir3_shader_variant
*fp
= fd5_emit_get_fp(emit
);
465 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
466 bool needs_border
= false;
468 emit_marker5(ring
, 5);
470 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->key
.binning_pass
) {
471 unsigned char mrt_comp
[A5XX_MAX_RENDER_TARGETS
] = {0};
473 for (unsigned i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
474 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
477 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_COMPONENTS
, 1);
478 OUT_RING(ring
, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
479 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
480 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
481 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
482 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
483 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
484 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
485 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
488 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
489 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
490 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
492 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
493 rb_alpha_control
&= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
495 OUT_PKT4(ring
, REG_A5XX_RB_ALPHA_CONTROL
, 1);
496 OUT_RING(ring
, rb_alpha_control
);
498 OUT_PKT4(ring
, REG_A5XX_RB_STENCIL_CONTROL
, 1);
499 OUT_RING(ring
, zsa
->rb_stencil_control
);
502 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_BLEND
| FD_DIRTY_PROG
)) {
503 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
504 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
507 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
508 uint32_t gras_lrz_cntl
= zsa
->gras_lrz_cntl
;
510 if (emit
->no_lrz_write
|| !rsc
->lrz
|| !rsc
->lrz_valid
)
512 else if (emit
->key
.binning_pass
&& blend
->lrz_write
&& zsa
->lrz_write
)
513 gras_lrz_cntl
|= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE
;
515 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_CNTL
, 1);
516 OUT_RING(ring
, gras_lrz_cntl
);
520 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
521 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
522 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
524 OUT_PKT4(ring
, REG_A5XX_RB_STENCILREFMASK
, 1);
525 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
526 A5XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
529 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
530 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
531 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
533 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_CNTL
, 1);
534 OUT_RING(ring
, zsa
->rb_depth_cntl
);
536 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_PLANE_CNTL
, 1);
537 OUT_RING(ring
, COND(fragz
, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
538 COND(fragz
&& fp
->frag_coord
, A5XX_RB_DEPTH_PLANE_CNTL_UNK1
));
540 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
541 OUT_RING(ring
, COND(fragz
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
542 COND(fragz
&& fp
->frag_coord
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1
));
545 if (dirty
& FD_DIRTY_SCISSOR
) {
546 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
548 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
549 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->minx
) |
550 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->miny
));
551 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
552 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
554 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
555 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->minx
) |
556 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->miny
));
557 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
558 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
560 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
561 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
562 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
563 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
566 if (dirty
& FD_DIRTY_VIEWPORT
) {
567 fd_wfi(ctx
->batch
, ring
);
568 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
569 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
570 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
571 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
572 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
573 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
574 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
577 if (dirty
& FD_DIRTY_PROG
)
578 fd5_program_emit(ctx
, ring
, emit
);
580 /* note: must come after program emit.. because there is some overlap
581 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
582 * values from fd5_program_emit() to avoid having to re-emit the prog
583 * every time rast state changes.
585 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_RASTERIZER
)) {
586 struct fd5_rasterizer_stateobj
*rasterizer
=
587 fd5_rasterizer_stateobj(ctx
->rasterizer
);
588 unsigned max_loc
= fd5_context(ctx
)->max_loc
;
590 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CNTL
, 1);
591 OUT_RING(ring
, rasterizer
->gras_su_cntl
);
593 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
594 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
595 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
597 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
598 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
599 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
600 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_clamp
);
602 OUT_PKT4(ring
, REG_A5XX_PC_PRIMITIVE_CNTL
, 1);
603 OUT_RING(ring
, rasterizer
->pc_primitive_cntl
|
604 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc
));
607 if (dirty
& (FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_RASTERIZER
)) {
608 uint32_t posz_regid
= ir3_find_output_regid(fp
, FRAG_RESULT_DEPTH
);
609 unsigned nr
= pfb
->nr_cbufs
;
611 if (emit
->key
.binning_pass
)
613 else if (ctx
->rasterizer
->rasterizer_discard
)
616 OUT_PKT4(ring
, REG_A5XX_RB_FS_OUTPUT_CNTL
, 1);
617 OUT_RING(ring
, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr
) |
618 COND(fp
->writes_pos
, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z
));
620 OUT_PKT4(ring
, REG_A5XX_SP_FS_OUTPUT_CNTL
, 1);
621 OUT_RING(ring
, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr
) |
622 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid
) |
623 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
626 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
627 ir3_emit_vs_consts(vp
, ring
, ctx
, emit
->info
);
628 if (!emit
->key
.binning_pass
)
629 ir3_emit_fs_consts(fp
, ring
, ctx
);
631 struct pipe_stream_output_info
*info
= &vp
->shader
->stream_output
;
632 if (info
->num_outputs
) {
633 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
635 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
636 struct pipe_stream_output_target
*target
= so
->targets
[i
];
641 unsigned offset
= (so
->offsets
[i
] * info
->stride
[i
] * 4) +
642 target
->buffer_offset
;
644 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i
), 3);
645 /* VPC_SO[i].BUFFER_BASE_LO: */
646 OUT_RELOCW(ring
, fd_resource(target
->buffer
)->bo
, 0, 0, 0);
647 OUT_RING(ring
, target
->buffer_size
+ offset
);
649 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(i
), 3);
650 OUT_RING(ring
, offset
);
651 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
652 // TODO just give hw a dummy addr for now.. we should
653 // be using this an then CP_MEM_TO_REG to set the
654 // VPC_SO[i].BUFFER_OFFSET for the next draw..
655 OUT_RELOCW(ring
, fd5_context(ctx
)->blit_mem
, 0x100, 0, 0);
657 emit
->streamout_mask
|= (1 << i
);
662 if ((dirty
& FD_DIRTY_BLEND
)) {
663 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
666 for (i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
667 enum pipe_format format
= pipe_surface_format(pfb
->cbufs
[i
]);
668 bool is_int
= util_format_is_pure_integer(format
);
669 bool has_alpha
= util_format_has_alpha(format
);
670 uint32_t control
= blend
->rb_mrt
[i
].control
;
671 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
674 control
&= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
675 // control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
679 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
681 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
682 control
&= ~A5XX_RB_MRT_CONTROL_BLEND2
;
685 OUT_PKT4(ring
, REG_A5XX_RB_MRT_CONTROL(i
), 1);
686 OUT_RING(ring
, control
);
688 OUT_PKT4(ring
, REG_A5XX_RB_MRT_BLEND_CONTROL(i
), 1);
689 OUT_RING(ring
, blend_control
);
692 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_CNTL
, 1);
693 OUT_RING(ring
, blend
->rb_blend_cntl
|
694 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
696 OUT_PKT4(ring
, REG_A5XX_SP_BLEND_CNTL
, 1);
697 OUT_RING(ring
, blend
->sp_blend_cntl
);
700 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
701 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
703 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_RED
, 8);
704 OUT_RING(ring
, A5XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
705 A5XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
706 A5XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
707 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
708 OUT_RING(ring
, A5XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
709 A5XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
710 A5XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
711 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
712 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
713 A5XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
714 A5XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
715 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
716 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
717 A5XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
718 A5XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
719 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
722 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
) {
723 needs_border
|= emit_textures(ctx
, ring
, SB4_VS_TEX
,
724 &ctx
->tex
[PIPE_SHADER_VERTEX
]);
725 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 1);
726 OUT_RING(ring
, ctx
->tex
[PIPE_SHADER_VERTEX
].num_textures
);
729 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
) {
730 needs_border
|= emit_textures(ctx
, ring
, SB4_FS_TEX
,
731 &ctx
->tex
[PIPE_SHADER_FRAGMENT
]);
732 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 1);
733 OUT_RING(ring
, ctx
->tex
[PIPE_SHADER_FRAGMENT
].num_textures
);
736 OUT_PKT4(ring
, REG_A5XX_TPL1_CS_TEX_COUNT
, 1);
740 emit_border_color(ctx
, ring
);
742 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_SSBO
)
743 emit_ssbos(ctx
, ring
, SB4_SSBO
, &ctx
->shaderbuf
[PIPE_SHADER_FRAGMENT
]);
747 fd5_emit_cs_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
748 struct ir3_shader_variant
*cp
)
750 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[PIPE_SHADER_COMPUTE
];
752 if (dirty
& FD_DIRTY_SHADER_TEX
) {
753 bool needs_border
= false;
754 needs_border
|= emit_textures(ctx
, ring
, SB4_CS_TEX
,
755 &ctx
->tex
[PIPE_SHADER_COMPUTE
]);
758 emit_border_color(ctx
, ring
);
760 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 1);
763 OUT_PKT4(ring
, REG_A5XX_TPL1_HS_TEX_COUNT
, 1);
766 OUT_PKT4(ring
, REG_A5XX_TPL1_DS_TEX_COUNT
, 1);
769 OUT_PKT4(ring
, REG_A5XX_TPL1_GS_TEX_COUNT
, 1);
772 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 1);
775 OUT_PKT4(ring
, REG_A5XX_TPL1_CS_TEX_COUNT
, 1);
776 OUT_RING(ring
, ctx
->tex
[PIPE_SHADER_COMPUTE
].num_textures
);
779 if (dirty
& FD_DIRTY_SHADER_SSBO
)
780 emit_ssbos(ctx
, ring
, SB4_CS_SSBO
, &ctx
->shaderbuf
[PIPE_SHADER_COMPUTE
]);
783 /* emit setup at begin of new cmdstream buffer (don't rely on previous
784 * state, there could have been a context switch between ioctls):
787 fd5_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
789 struct fd_context
*ctx
= batch
->ctx
;
791 fd5_set_render_mode(ctx
, ring
, BYPASS
);
792 fd5_cache_flush(batch
, ring
);
794 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
795 OUT_RING(ring
, 0xfffff);
798 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
799 0000000500024048: 70d08003 00000000 001c5000 00000005
800 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
801 0000000500024058: 70d08003 00000010 001c7000 00000005
803 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
804 0000000500024068: 70268000
807 OUT_PKT4(ring
, REG_A5XX_PC_RESTART_INDEX
, 1);
808 OUT_RING(ring
, 0xffffffff);
810 OUT_PKT4(ring
, REG_A5XX_PC_RASTER_CNTL
, 1);
811 OUT_RING(ring
, 0x00000012);
813 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
814 OUT_RING(ring
, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
815 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
816 OUT_RING(ring
, A5XX_GRAS_SU_POINT_SIZE(0.5));
818 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
819 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
821 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL
, 1);
822 OUT_RING(ring
, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
824 OUT_PKT4(ring
, REG_A5XX_SP_VS_CONFIG_MAX_CONST
, 1);
825 OUT_RING(ring
, 0); /* SP_VS_CONFIG_MAX_CONST */
827 OUT_PKT4(ring
, REG_A5XX_SP_FS_CONFIG_MAX_CONST
, 1);
828 OUT_RING(ring
, 0); /* SP_FS_CONFIG_MAX_CONST */
830 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E292
, 2);
831 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E292 */
832 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E293 */
834 OUT_PKT4(ring
, REG_A5XX_RB_MODE_CNTL
, 1);
835 OUT_RING(ring
, 0x00000044); /* RB_MODE_CNTL */
837 OUT_PKT4(ring
, REG_A5XX_RB_DBG_ECO_CNTL
, 1);
838 OUT_RING(ring
, 0x00100000); /* RB_DBG_ECO_CNTL */
840 OUT_PKT4(ring
, REG_A5XX_VFD_MODE_CNTL
, 1);
841 OUT_RING(ring
, 0x00000000); /* VFD_MODE_CNTL */
843 OUT_PKT4(ring
, REG_A5XX_PC_MODE_CNTL
, 1);
844 OUT_RING(ring
, 0x0000001f); /* PC_MODE_CNTL */
846 OUT_PKT4(ring
, REG_A5XX_SP_MODE_CNTL
, 1);
847 OUT_RING(ring
, 0x0000001e); /* SP_MODE_CNTL */
849 OUT_PKT4(ring
, REG_A5XX_SP_DBG_ECO_CNTL
, 1);
850 OUT_RING(ring
, 0x40000800); /* SP_DBG_ECO_CNTL */
852 OUT_PKT4(ring
, REG_A5XX_TPL1_MODE_CNTL
, 1);
853 OUT_RING(ring
, 0x00000544); /* TPL1_MODE_CNTL */
855 OUT_PKT4(ring
, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0
, 2);
856 OUT_RING(ring
, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
857 OUT_RING(ring
, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
859 OUT_PKT4(ring
, REG_A5XX_VPC_DBG_ECO_CNTL
, 1);
860 OUT_RING(ring
, 0x00000400); /* VPC_DBG_ECO_CNTL */
862 OUT_PKT4(ring
, REG_A5XX_HLSQ_MODE_CNTL
, 1);
863 OUT_RING(ring
, 0x00000001); /* HLSQ_MODE_CNTL */
865 OUT_PKT4(ring
, REG_A5XX_VPC_MODE_CNTL
, 1);
866 OUT_RING(ring
, 0x00000000); /* VPC_MODE_CNTL */
868 /* we don't use this yet.. probably best to disable.. */
869 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
870 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
871 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
872 CP_SET_DRAW_STATE__0_GROUP_ID(0));
873 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
874 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
876 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
877 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
879 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
880 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
882 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
883 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
885 OUT_PKT4(ring
, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL
, 1);
886 OUT_RING(ring
, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
888 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
889 OUT_RING(ring
, A5XX_VPC_SO_OVERRIDE_SO_DISABLE
);
891 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
892 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
893 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
894 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
896 OUT_PKT4(ring
, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
897 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
898 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
900 OUT_PKT4(ring
, REG_A5XX_PC_GS_PARAM
, 1);
901 OUT_RING(ring
, 0x00000000); /* PC_GS_PARAM */
903 OUT_PKT4(ring
, REG_A5XX_PC_HS_PARAM
, 1);
904 OUT_RING(ring
, 0x00000000); /* PC_HS_PARAM */
906 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL
, 1);
907 OUT_RING(ring
, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
909 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E001
, 1);
910 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E001 */
912 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E004
, 1);
913 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E004 */
915 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E093
, 1);
916 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E093 */
918 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E1C7
, 1);
919 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E1C7 */
921 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E29A
, 1);
922 OUT_RING(ring
, 0x00ffff00); /* UNKNOWN_E29A */
924 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUF_CNTL
, 1);
925 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUF_CNTL */
927 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
928 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E2AB */
930 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E389
, 1);
931 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E389 */
933 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E38D
, 1);
934 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E38D */
936 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5AB
, 1);
937 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5AB */
939 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5C2
, 1);
940 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5C2 */
942 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
943 OUT_RING(ring
, 0x00000000);
944 OUT_RING(ring
, 0x00000000);
945 OUT_RING(ring
, 0x00000000);
947 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
948 OUT_RING(ring
, 0x00000000);
949 OUT_RING(ring
, 0x00000000);
950 OUT_RING(ring
, 0x00000000);
951 OUT_RING(ring
, 0x00000000);
952 OUT_RING(ring
, 0x00000000);
953 OUT_RING(ring
, 0x00000000);
955 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
956 OUT_RING(ring
, 0x00000000);
957 OUT_RING(ring
, 0x00000000);
958 OUT_RING(ring
, 0x00000000);
959 OUT_RING(ring
, 0x00000000);
960 OUT_RING(ring
, 0x00000000);
961 OUT_RING(ring
, 0x00000000);
963 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
964 OUT_RING(ring
, 0x00000000);
965 OUT_RING(ring
, 0x00000000);
966 OUT_RING(ring
, 0x00000000);
968 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5DB
, 1);
969 OUT_RING(ring
, 0x00000000);
971 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E600
, 1);
972 OUT_RING(ring
, 0x00000000);
974 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E640
, 1);
975 OUT_RING(ring
, 0x00000000);
977 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 4);
978 OUT_RING(ring
, 0x00000000);
979 OUT_RING(ring
, 0x00000000);
980 OUT_RING(ring
, 0x00000000);
981 OUT_RING(ring
, 0x00000000);
983 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 2);
984 OUT_RING(ring
, 0x00000000);
985 OUT_RING(ring
, 0x00000000);
987 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C0
, 3);
988 OUT_RING(ring
, 0x00000000);
989 OUT_RING(ring
, 0x00000000);
990 OUT_RING(ring
, 0x00000000);
992 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C5
, 3);
993 OUT_RING(ring
, 0x00000000);
994 OUT_RING(ring
, 0x00000000);
995 OUT_RING(ring
, 0x00000000);
997 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CA
, 3);
998 OUT_RING(ring
, 0x00000000);
999 OUT_RING(ring
, 0x00000000);
1000 OUT_RING(ring
, 0x00000000);
1002 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CF
, 3);
1003 OUT_RING(ring
, 0x00000000);
1004 OUT_RING(ring
, 0x00000000);
1005 OUT_RING(ring
, 0x00000000);
1007 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D4
, 3);
1008 OUT_RING(ring
, 0x00000000);
1009 OUT_RING(ring
, 0x00000000);
1010 OUT_RING(ring
, 0x00000000);
1012 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D9
, 3);
1013 OUT_RING(ring
, 0x00000000);
1014 OUT_RING(ring
, 0x00000000);
1015 OUT_RING(ring
, 0x00000000);
1019 fd5_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
1021 __OUT_IB5(ring
, target
);
1025 fd5_emit_init(struct pipe_context
*pctx
)
1027 struct fd_context
*ctx
= fd_context(pctx
);
1028 ctx
->emit_const
= fd5_emit_const
;
1029 ctx
->emit_const_bo
= fd5_emit_const_bo
;
1030 ctx
->emit_ib
= fd5_emit_ib
;