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freedreno/ir3: add SSBO get_buffer_size() support
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
44 #include "fd5_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 static void
51 fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
52 uint32_t regid, uint32_t offset, uint32_t sizedwords,
53 const uint32_t *dwords, struct pipe_resource *prsc)
54 {
55 uint32_t i, sz;
56 enum a4xx_state_src src;
57
58 debug_assert((regid % 4) == 0);
59 debug_assert((sizedwords % 4) == 0);
60
61 if (prsc) {
62 sz = 0;
63 src = SS4_INDIRECT;
64 } else {
65 sz = sizedwords;
66 src = SS4_DIRECT;
67 }
68
69 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
70 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
71 CP_LOAD_STATE4_0_STATE_SRC(src) |
72 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
73 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
74 if (prsc) {
75 struct fd_bo *bo = fd_resource(prsc)->bo;
76 OUT_RELOC(ring, bo, offset,
77 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
78 } else {
79 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
81 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
82 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
83 }
84 for (i = 0; i < sz; i++) {
85 OUT_RING(ring, dwords[i]);
86 }
87 }
88
89 static void
90 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
91 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
92 {
93 uint32_t anum = align(num, 2);
94 uint32_t i;
95
96 debug_assert((regid % 4) == 0);
97
98 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
99 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
100 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
101 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
102 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
103 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
104 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
105 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
106
107 for (i = 0; i < num; i++) {
108 if (prscs[i]) {
109 if (write) {
110 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
111 } else {
112 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
113 }
114 } else {
115 OUT_RING(ring, 0xbad00000 | (i << 16));
116 OUT_RING(ring, 0xbad00000 | (i << 16));
117 }
118 }
119
120 for (; i < anum; i++) {
121 OUT_RING(ring, 0xffffffff);
122 OUT_RING(ring, 0xffffffff);
123 }
124 }
125
126 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
127 * the same as a6xx then move this somewhere common ;-)
128 *
129 * Entry layout looks like (total size, 0x60 bytes):
130 */
131
132 struct PACKED bcolor_entry {
133 uint32_t fp32[4];
134 uint16_t ui16[4];
135 int16_t si16[4];
136 uint16_t fp16[4];
137 uint16_t rgb565;
138 uint16_t rgb5a1;
139 uint16_t rgba4;
140 uint8_t __pad0[2];
141 uint8_t ui8[4];
142 int8_t si8[4];
143 uint32_t rgb10a2;
144 uint32_t z24; /* also s8? */
145 uint8_t __pad1[32];
146 };
147
148 #define FD5_BORDER_COLOR_SIZE 0x60
149 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
150
151 static void
152 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
153 {
154 unsigned i, j;
155 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
156
157 for (i = 0; i < tex->num_samplers; i++) {
158 struct bcolor_entry *e = &entries[i];
159 struct pipe_sampler_state *sampler = tex->samplers[i];
160 union pipe_color_union *bc;
161
162 if (!sampler)
163 continue;
164
165 bc = &sampler->border_color;
166
167 /*
168 * XXX HACK ALERT XXX
169 *
170 * The border colors need to be swizzled in a particular
171 * format-dependent order. Even though samplers don't know about
172 * formats, we can assume that with a GL state tracker, there's a
173 * 1:1 correspondence between sampler and texture. Take advantage
174 * of that knowledge.
175 */
176 if ((i >= tex->num_textures) || !tex->textures[i])
177 continue;
178
179 const struct util_format_description *desc =
180 util_format_description(tex->textures[i]->format);
181
182 e->rgb565 = 0;
183 e->rgb5a1 = 0;
184 e->rgba4 = 0;
185 e->rgb10a2 = 0;
186 e->z24 = 0;
187
188 for (j = 0; j < 4; j++) {
189 int c = desc->swizzle[j];
190
191 if (c >= 4)
192 continue;
193
194 if (desc->channel[c].pure_integer) {
195 uint16_t clamped;
196 switch (desc->channel[c].size) {
197 case 2:
198 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
199 clamped = CLAMP(bc->ui[j], 0, 0x3);
200 break;
201 case 8:
202 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
203 clamped = CLAMP(bc->i[j], -128, 127);
204 else
205 clamped = CLAMP(bc->ui[j], 0, 255);
206 break;
207 case 10:
208 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
209 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
210 break;
211 case 16:
212 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
213 clamped = CLAMP(bc->i[j], -32768, 32767);
214 else
215 clamped = CLAMP(bc->ui[j], 0, 65535);
216 break;
217 default:
218 assert(!"Unexpected bit size");
219 case 32:
220 clamped = 0;
221 break;
222 }
223 e->fp32[c] = bc->ui[j];
224 e->fp16[c] = clamped;
225 } else {
226 float f = bc->f[j];
227 float f_u = CLAMP(f, 0, 1);
228 float f_s = CLAMP(f, -1, 1);
229
230 e->fp32[c] = fui(f);
231 e->fp16[c] = util_float_to_half(f);
232 e->ui16[c] = f_u * 0xffff;
233 e->si16[c] = f_s * 0x7fff;
234 e->ui8[c] = f_u * 0xff;
235 e->si8[c] = f_s * 0x7f;
236 if (c == 1)
237 e->rgb565 |= (int)(f_u * 0x3f) << 5;
238 else if (c < 3)
239 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
240 if (c == 3)
241 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
242 else
243 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
244 if (c == 3)
245 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
246 else
247 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
248 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
249 if (c == 0)
250 e->z24 = f_u * 0xffffff;
251 }
252 }
253
254 #ifdef DEBUG
255 memset(&e->__pad0, 0, sizeof(e->__pad0));
256 memset(&e->__pad1, 0, sizeof(e->__pad1));
257 #endif
258 }
259 }
260
261 static void
262 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
263 {
264 struct fd5_context *fd5_ctx = fd5_context(ctx);
265 struct bcolor_entry *entries;
266 unsigned off;
267 void *ptr;
268
269 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
270
271 u_upload_alloc(fd5_ctx->border_color_uploader,
272 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
273 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
274 &fd5_ctx->border_color_buf,
275 &ptr);
276
277 entries = ptr;
278
279 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
280 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
281 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
282
283 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
284 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
285
286 u_upload_unmap(fd5_ctx->border_color_uploader);
287 }
288
289 static bool
290 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
291 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
292 {
293 bool needs_border = false;
294 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
295 unsigned i;
296
297 if (tex->num_samplers > 0) {
298 /* output sampler state: */
299 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
300 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
301 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
302 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
303 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
304 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
305 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
306 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
307 for (i = 0; i < tex->num_samplers; i++) {
308 static const struct fd5_sampler_stateobj dummy_sampler = {};
309 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
310 fd5_sampler_stateobj(tex->samplers[i]) :
311 &dummy_sampler;
312 OUT_RING(ring, sampler->texsamp0);
313 OUT_RING(ring, sampler->texsamp1);
314 OUT_RING(ring, sampler->texsamp2 |
315 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
316 OUT_RING(ring, sampler->texsamp3);
317
318 needs_border |= sampler->needs_border;
319 }
320 }
321
322 if (tex->num_textures > 0) {
323 unsigned num_textures = tex->num_textures;
324
325 /* emit texture state: */
326 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
327 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
328 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
329 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
330 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
331 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
332 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
333 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
334 for (i = 0; i < tex->num_textures; i++) {
335 static const struct fd5_pipe_sampler_view dummy_view = {};
336 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
337 fd5_pipe_sampler_view(tex->textures[i]) :
338 &dummy_view;
339
340 OUT_RING(ring, view->texconst0);
341 OUT_RING(ring, view->texconst1);
342 OUT_RING(ring, view->texconst2);
343 OUT_RING(ring, view->texconst3);
344 if (view->base.texture) {
345 struct fd_resource *rsc = fd_resource(view->base.texture);
346 OUT_RELOC(ring, rsc->bo, view->offset,
347 (uint64_t)view->texconst5 << 32, 0);
348 } else {
349 OUT_RING(ring, 0x00000000);
350 OUT_RING(ring, view->texconst5);
351 }
352 OUT_RING(ring, view->texconst6);
353 OUT_RING(ring, view->texconst7);
354 OUT_RING(ring, view->texconst8);
355 OUT_RING(ring, view->texconst9);
356 OUT_RING(ring, view->texconst10);
357 OUT_RING(ring, view->texconst11);
358 }
359 }
360
361 return needs_border;
362 }
363
364 static void
365 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
366 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so)
367 {
368 unsigned count = util_last_bit(so->enabled_mask);
369
370 if (count == 0)
371 return;
372
373 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * count));
374 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
375 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
376 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
377 CP_LOAD_STATE4_0_NUM_UNIT(count));
378 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(0) |
379 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
380 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
381 for (unsigned i = 0; i < count; i++) {
382 OUT_RING(ring, 0x00000000);
383 OUT_RING(ring, 0x00000000);
384 OUT_RING(ring, 0x00000000);
385 OUT_RING(ring, 0x00000000);
386 }
387
388 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
389 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
390 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
391 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
392 CP_LOAD_STATE4_0_NUM_UNIT(count));
393 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
394 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
395 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
396 for (unsigned i = 0; i < count; i++) {
397 struct pipe_shader_buffer *buf = &so->sb[i];
398 unsigned sz = buf->buffer_size;
399
400 /* width is in dwords, overflows into height: */
401 sz /= 4;
402
403 OUT_RING(ring, A5XX_SSBO_1_0_WIDTH(sz));
404 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(sz >> 16));
405 }
406
407 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * count));
408 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
409 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
410 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
411 CP_LOAD_STATE4_0_NUM_UNIT(count));
412 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
413 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
414 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
415 for (unsigned i = 0; i < count; i++) {
416 struct pipe_shader_buffer *buf = &so->sb[i];
417 if (buf->buffer) {
418 struct fd_resource *rsc = fd_resource(buf->buffer);
419 OUT_RELOCW(ring, rsc->bo, 0, 0, 0);
420 } else {
421 OUT_RING(ring, 0x00000000);
422 OUT_RING(ring, 0x00000000);
423 }
424 }
425 }
426
427 void
428 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
429 {
430 int32_t i, j;
431 const struct fd_vertex_state *vtx = emit->vtx;
432 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
433
434 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
435 if (vp->inputs[i].sysval)
436 continue;
437 if (vp->inputs[i].compmask) {
438 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
439 const struct pipe_vertex_buffer *vb =
440 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
441 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
442 enum pipe_format pfmt = elem->src_format;
443 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
444 bool isint = util_format_is_pure_integer(pfmt);
445 uint32_t off = vb->buffer_offset + elem->src_offset;
446 uint32_t size = fd_bo_size(rsc->bo) - off;
447 debug_assert(fmt != ~0);
448
449 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
450 OUT_RELOC(ring, rsc->bo, off, 0, 0);
451 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
452 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
453
454 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
455 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
456 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
457 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
458 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)) |
459 A5XX_VFD_DECODE_INSTR_UNK30 |
460 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
461 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
462
463 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
464 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
465 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
466
467 j++;
468 }
469 }
470
471 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
472 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
473 }
474
475 void
476 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
477 struct fd5_emit *emit)
478 {
479 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
480 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
481 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
482 const enum fd_dirty_3d_state dirty = emit->dirty;
483 bool needs_border = false;
484
485 emit_marker5(ring, 5);
486
487 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
488 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
489
490 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
491 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
492 }
493
494 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
495 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
496 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
497 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
498 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
499 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
500 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
501 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
502 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
503 }
504
505 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
506 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
507 uint32_t rb_alpha_control = zsa->rb_alpha_control;
508
509 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
510 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
511
512 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
513 OUT_RING(ring, rb_alpha_control);
514
515 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
516 OUT_RING(ring, zsa->rb_stencil_control);
517 }
518
519 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
520 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
521 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
522
523 if (pfb->zsbuf) {
524 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
525 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
526
527 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
528 gras_lrz_cntl = 0;
529 else if (emit->key.binning_pass && blend->lrz_write && zsa->lrz_write)
530 gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE;
531
532 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
533 OUT_RING(ring, gras_lrz_cntl);
534 }
535 }
536
537 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
538 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
539 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
540
541 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2);
542 OUT_RING(ring, zsa->rb_stencilrefmask |
543 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
544 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
545 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
546 }
547
548 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
549 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
550 bool fragz = fp->has_kill | fp->writes_pos;
551
552 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
553 OUT_RING(ring, zsa->rb_depth_cntl);
554
555 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
556 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
557 COND(fragz && fp->frag_coord, A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
558
559 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
560 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
561 COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
562 }
563
564 if (dirty & FD_DIRTY_SCISSOR) {
565 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
566
567 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
568 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
569 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
570 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
571 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
572
573 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
574 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
575 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
576 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
577 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
578
579 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
580 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
581 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
582 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
583 }
584
585 if (dirty & FD_DIRTY_VIEWPORT) {
586 fd_wfi(ctx->batch, ring);
587 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
588 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
589 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
590 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
591 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
592 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
593 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
594 }
595
596 if (dirty & FD_DIRTY_PROG)
597 fd5_program_emit(ctx, ring, emit);
598
599 if (dirty & FD_DIRTY_RASTERIZER) {
600 struct fd5_rasterizer_stateobj *rasterizer =
601 fd5_rasterizer_stateobj(ctx->rasterizer);
602
603 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
604 OUT_RING(ring, rasterizer->gras_su_cntl);
605
606 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
607 OUT_RING(ring, rasterizer->gras_su_point_minmax);
608 OUT_RING(ring, rasterizer->gras_su_point_size);
609
610 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
611 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
612 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
613 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
614
615 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
616 OUT_RING(ring, rasterizer->pc_raster_cntl);
617
618 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
619 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
620 }
621
622 /* note: must come after program emit.. because there is some overlap
623 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
624 * values from fd5_program_emit() to avoid having to re-emit the prog
625 * every time rast state changes.
626 *
627 * Since the primitive restart state is not part of a tracked object, we
628 * re-emit this register every time.
629 */
630 if (emit->info && ctx->rasterizer) {
631 struct fd5_rasterizer_stateobj *rasterizer =
632 fd5_rasterizer_stateobj(ctx->rasterizer);
633 unsigned max_loc = fd5_context(ctx)->max_loc;
634
635 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
636 OUT_RING(ring, rasterizer->pc_primitive_cntl |
637 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc) |
638 COND(emit->info->primitive_restart && emit->info->index_size,
639 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART));
640 }
641
642 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
643 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
644 unsigned nr = pfb->nr_cbufs;
645
646 if (emit->key.binning_pass)
647 nr = 0;
648 else if (ctx->rasterizer->rasterizer_discard)
649 nr = 0;
650
651 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
652 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
653 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
654
655 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
656 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
657 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
658 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
659 }
660
661 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
662 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
663 if (!emit->key.binning_pass)
664 ir3_emit_fs_consts(fp, ring, ctx);
665
666 struct pipe_stream_output_info *info = &vp->shader->stream_output;
667 if (info->num_outputs) {
668 struct fd_streamout_stateobj *so = &ctx->streamout;
669
670 for (unsigned i = 0; i < so->num_targets; i++) {
671 struct pipe_stream_output_target *target = so->targets[i];
672
673 if (!target)
674 continue;
675
676 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
677 target->buffer_offset;
678
679 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
680 /* VPC_SO[i].BUFFER_BASE_LO: */
681 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
682 OUT_RING(ring, target->buffer_size + offset);
683
684 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
685 OUT_RING(ring, offset);
686 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
687 // TODO just give hw a dummy addr for now.. we should
688 // be using this an then CP_MEM_TO_REG to set the
689 // VPC_SO[i].BUFFER_OFFSET for the next draw..
690 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
691
692 emit->streamout_mask |= (1 << i);
693 }
694 }
695 }
696
697 if ((dirty & FD_DIRTY_BLEND)) {
698 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
699 uint32_t i;
700
701 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
702 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
703 bool is_int = util_format_is_pure_integer(format);
704 bool has_alpha = util_format_has_alpha(format);
705 uint32_t control = blend->rb_mrt[i].control;
706 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
707
708 if (is_int) {
709 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
710 control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
711 }
712
713 if (has_alpha) {
714 blend_control |= blend->rb_mrt[i].blend_control_rgb;
715 } else {
716 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
717 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
718 }
719
720 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
721 OUT_RING(ring, control);
722
723 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
724 OUT_RING(ring, blend_control);
725 }
726
727 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
728 OUT_RING(ring, blend->rb_blend_cntl |
729 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
730
731 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
732 OUT_RING(ring, blend->sp_blend_cntl);
733 }
734
735 if (dirty & FD_DIRTY_BLEND_COLOR) {
736 struct pipe_blend_color *bcolor = &ctx->blend_color;
737
738 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
739 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
740 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
741 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
742 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
743 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
744 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
745 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
746 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
747 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
748 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
749 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
750 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
751 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
752 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
753 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
754 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
755 }
756
757 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
758 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX,
759 &ctx->tex[PIPE_SHADER_VERTEX]);
760 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
761 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
762 }
763
764 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
765 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX,
766 &ctx->tex[PIPE_SHADER_FRAGMENT]);
767 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
768 OUT_RING(ring, ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
769 }
770
771 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
772 OUT_RING(ring, 0);
773
774 if (needs_border)
775 emit_border_color(ctx, ring);
776
777 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
778 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT]);
779 }
780
781 void
782 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
783 struct ir3_shader_variant *cp)
784 {
785 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
786
787 if (dirty & FD_DIRTY_SHADER_TEX) {
788 bool needs_border = false;
789 needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
790 &ctx->tex[PIPE_SHADER_COMPUTE]);
791
792 if (needs_border)
793 emit_border_color(ctx, ring);
794
795 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
796 OUT_RING(ring, 0);
797
798 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
799 OUT_RING(ring, 0);
800
801 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
802 OUT_RING(ring, 0);
803
804 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
805 OUT_RING(ring, 0);
806
807 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
808 OUT_RING(ring, 0);
809
810 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
811 OUT_RING(ring, ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
812 }
813
814 if (dirty & FD_DIRTY_SHADER_SSBO)
815 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE]);
816 }
817
818 /* emit setup at begin of new cmdstream buffer (don't rely on previous
819 * state, there could have been a context switch between ioctls):
820 */
821 void
822 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
823 {
824 struct fd_context *ctx = batch->ctx;
825
826 fd5_set_render_mode(ctx, ring, BYPASS);
827 fd5_cache_flush(batch, ring);
828
829 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
830 OUT_RING(ring, 0xfffff);
831
832 /*
833 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
834 0000000500024048: 70d08003 00000000 001c5000 00000005
835 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
836 0000000500024058: 70d08003 00000010 001c7000 00000005
837
838 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
839 0000000500024068: 70268000
840 */
841
842 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
843 OUT_RING(ring, 0xffffffff);
844
845 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
846 OUT_RING(ring, 0x00000012);
847
848 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
849 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
850 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
851 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
852
853 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
854 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
855
856 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
857 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
858
859 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
860 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
861
862 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
863 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
864
865 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
866 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
867 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
868
869 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
870 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
871
872 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
873 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
874
875 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
876 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
877
878 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
879 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
880
881 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
882 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
883
884 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
885 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
886
887 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
888 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
889
890 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
891 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
892 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
893
894 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
895 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
896
897 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
898 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
899
900 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
901 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
902
903 /* we don't use this yet.. probably best to disable.. */
904 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
905 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
906 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
907 CP_SET_DRAW_STATE__0_GROUP_ID(0));
908 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
909 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
910
911 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
912 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
913
914 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
915 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
916
917 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
918 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
919
920 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
921 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
922
923 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
924 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
925
926 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
927 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
928 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
929 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
930
931 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
932 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
933 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
934
935 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
936 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
937
938 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
939 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
940
941 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
942 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
943
944 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
945 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
946
947 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
948 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
949
950 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1);
951 OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */
952
953 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
954 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
955
956 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
957 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
958
959 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
960 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
961
962 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
963 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
964
965 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E38D, 1);
966 OUT_RING(ring, 0x00000000); /* UNKNOWN_E38D */
967
968 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
969 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
970
971 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
972 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
973
974 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
975 OUT_RING(ring, 0x00000000);
976 OUT_RING(ring, 0x00000000);
977 OUT_RING(ring, 0x00000000);
978
979 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
980 OUT_RING(ring, 0x00000000);
981 OUT_RING(ring, 0x00000000);
982 OUT_RING(ring, 0x00000000);
983 OUT_RING(ring, 0x00000000);
984 OUT_RING(ring, 0x00000000);
985 OUT_RING(ring, 0x00000000);
986
987 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
988 OUT_RING(ring, 0x00000000);
989 OUT_RING(ring, 0x00000000);
990 OUT_RING(ring, 0x00000000);
991 OUT_RING(ring, 0x00000000);
992 OUT_RING(ring, 0x00000000);
993 OUT_RING(ring, 0x00000000);
994
995 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
996 OUT_RING(ring, 0x00000000);
997 OUT_RING(ring, 0x00000000);
998 OUT_RING(ring, 0x00000000);
999
1000 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
1001 OUT_RING(ring, 0x00000000);
1002
1003 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E600, 1);
1004 OUT_RING(ring, 0x00000000);
1005
1006 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E640, 1);
1007 OUT_RING(ring, 0x00000000);
1008
1009 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
1010 OUT_RING(ring, 0x00000000);
1011 OUT_RING(ring, 0x00000000);
1012 OUT_RING(ring, 0x00000000);
1013 OUT_RING(ring, 0x00000000);
1014
1015 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
1016 OUT_RING(ring, 0x00000000);
1017 OUT_RING(ring, 0x00000000);
1018
1019 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
1020 OUT_RING(ring, 0x00000000);
1021 OUT_RING(ring, 0x00000000);
1022 OUT_RING(ring, 0x00000000);
1023
1024 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
1025 OUT_RING(ring, 0x00000000);
1026 OUT_RING(ring, 0x00000000);
1027 OUT_RING(ring, 0x00000000);
1028
1029 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
1030 OUT_RING(ring, 0x00000000);
1031 OUT_RING(ring, 0x00000000);
1032 OUT_RING(ring, 0x00000000);
1033
1034 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
1035 OUT_RING(ring, 0x00000000);
1036 OUT_RING(ring, 0x00000000);
1037 OUT_RING(ring, 0x00000000);
1038
1039 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1040 OUT_RING(ring, 0x00000000);
1041 OUT_RING(ring, 0x00000000);
1042 OUT_RING(ring, 0x00000000);
1043
1044 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1045 OUT_RING(ring, 0x00000000);
1046 OUT_RING(ring, 0x00000000);
1047 OUT_RING(ring, 0x00000000);
1048
1049 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
1050 OUT_RING(ring, 0x00000000);
1051 }
1052
1053 static void
1054 fd5_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
1055 {
1056 __OUT_IB5(ring, target);
1057 }
1058
1059 void
1060 fd5_emit_init(struct pipe_context *pctx)
1061 {
1062 struct fd_context *ctx = fd_context(pctx);
1063 ctx->emit_const = fd5_emit_const;
1064 ctx->emit_const_bo = fd5_emit_const_bo;
1065 ctx->emit_ib = fd5_emit_ib;
1066 }