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freedreno: extract helper for stage->sb for a4xx+
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_context.h"
40 #include "fd5_program.h"
41 #include "fd5_rasterizer.h"
42 #include "fd5_texture.h"
43 #include "fd5_format.h"
44 #include "fd5_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 static void
51 fd5_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
52 uint32_t regid, uint32_t offset, uint32_t sizedwords,
53 const uint32_t *dwords, struct pipe_resource *prsc)
54 {
55 uint32_t i, sz;
56 enum a4xx_state_src src;
57
58 debug_assert((regid % 4) == 0);
59 debug_assert((sizedwords % 4) == 0);
60
61 if (prsc) {
62 sz = 0;
63 src = SS4_INDIRECT;
64 } else {
65 sz = sizedwords;
66 src = SS4_DIRECT;
67 }
68
69 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
70 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
71 CP_LOAD_STATE4_0_STATE_SRC(src) |
72 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
73 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
74 if (prsc) {
75 struct fd_bo *bo = fd_resource(prsc)->bo;
76 OUT_RELOC(ring, bo, offset,
77 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
78 } else {
79 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
81 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
82 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
83 }
84 for (i = 0; i < sz; i++) {
85 OUT_RING(ring, dwords[i]);
86 }
87 }
88
89 static void
90 fd5_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
91 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
92 {
93 uint32_t anum = align(num, 2);
94 uint32_t i;
95
96 debug_assert((regid % 4) == 0);
97
98 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
99 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
100 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
101 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
102 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
103 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
104 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
105 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
106
107 for (i = 0; i < num; i++) {
108 if (prscs[i]) {
109 if (write) {
110 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
111 } else {
112 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
113 }
114 } else {
115 OUT_RING(ring, 0xbad00000 | (i << 16));
116 OUT_RING(ring, 0xbad00000 | (i << 16));
117 }
118 }
119
120 for (; i < anum; i++) {
121 OUT_RING(ring, 0xffffffff);
122 OUT_RING(ring, 0xffffffff);
123 }
124 }
125
126 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
127 * the same as a6xx then move this somewhere common ;-)
128 *
129 * Entry layout looks like (total size, 0x60 bytes):
130 *
131 * offset | description
132 * -------+-------------
133 * 0x00 | fp32[0]
134 * | fp32[1]
135 * | fp32[2]
136 * | fp32[3]
137 * 0x10 | uint16[0]
138 * | uint16[1]
139 * | uint16[2]
140 * | uint16[3]
141 * 0x18 | int16[0]
142 * | int16[1]
143 * | int16[2]
144 * | int16[3]
145 * 0x20 | fp16[0]
146 * | fp16[1]
147 * | fp16[2]
148 * | fp16[3]
149 * 0x28 | ?? maybe padding ??
150 * 0x30 | uint8[0]
151 * | uint8[1]
152 * | uint8[2]
153 * | uint8[3]
154 * 0x34 | int8[0]
155 * | int8[1]
156 * | int8[2]
157 * | int8[3]
158 * 0x38 | ?? maybe padding ??
159 *
160 * Some uncertainty, because not clear that this actually works properly
161 * with blob, so who knows..
162 */
163
164 struct PACKED bcolor_entry {
165 uint32_t fp32[4];
166 uint16_t ui16[4];
167 int16_t si16[4];
168 uint16_t fp16[4];
169 uint8_t __pad0[8];
170 uint8_t ui8[4];
171 int8_t si8[4];
172 uint8_t __pad1[40];
173 };
174
175 #define FD5_BORDER_COLOR_SIZE 0x60
176 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
177 #define FD5_BORDER_COLOR_OFFSET 8 /* TODO probably should be dynamic */
178
179 static void
180 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
181 {
182 unsigned i, j;
183
184 debug_assert(tex->num_samplers < FD5_BORDER_COLOR_OFFSET); // TODO
185
186 for (i = 0; i < tex->num_samplers; i++) {
187 struct bcolor_entry *e = &entries[i];
188 struct pipe_sampler_state *sampler = tex->samplers[i];
189 union pipe_color_union *bc;
190
191 if (!sampler)
192 continue;
193
194 bc = &sampler->border_color;
195
196 /*
197 * XXX HACK ALERT XXX
198 *
199 * The border colors need to be swizzled in a particular
200 * format-dependent order. Even though samplers don't know about
201 * formats, we can assume that with a GL state tracker, there's a
202 * 1:1 correspondence between sampler and texture. Take advantage
203 * of that knowledge.
204 */
205 if ((i >= tex->num_textures) || !tex->textures[i])
206 continue;
207
208 const struct util_format_description *desc =
209 util_format_description(tex->textures[i]->format);
210
211 for (j = 0; j < 4; j++) {
212 int c = desc->swizzle[j];
213
214 if (c >= 4)
215 continue;
216
217 if (desc->channel[c].pure_integer) {
218 float f = bc->i[c];
219
220 e->fp32[j] = fui(f);
221 e->fp16[j] = util_float_to_half(f);
222 e->ui16[j] = bc->ui[c];
223 e->si16[j] = bc->i[c];
224 e->ui8[j] = bc->ui[c];
225 e->si8[j] = bc->i[c];
226 } else {
227 float f = bc->f[c];
228
229 e->fp32[j] = fui(f);
230 e->fp16[j] = util_float_to_half(f);
231 e->ui16[j] = f * 65535.0;
232 e->si16[j] = f * 32767.5;
233 e->ui8[j] = f * 255.0;
234 e->si8[j] = f * 128.0;
235 }
236 }
237
238 #ifdef DEBUG
239 memset(&e->__pad0, 0, sizeof(e->__pad0));
240 memset(&e->__pad1, 0, sizeof(e->__pad1));
241 #endif
242 }
243 }
244
245 static void
246 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
247 {
248 struct fd5_context *fd5_ctx = fd5_context(ctx);
249 struct bcolor_entry *entries;
250 unsigned off;
251 void *ptr;
252
253 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
254
255 u_upload_alloc(fd5_ctx->border_color_uploader,
256 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
257 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
258 &fd5_ctx->border_color_buf,
259 &ptr);
260
261 entries = ptr;
262
263 setup_border_colors(&ctx->verttex, &entries[0]);
264 setup_border_colors(&ctx->fragtex, &entries[ctx->verttex.num_samplers]);
265
266 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
267 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
268
269 u_upload_unmap(fd5_ctx->border_color_uploader);
270 }
271
272 static bool
273 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
274 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
275 {
276 bool needs_border = false;
277 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->verttex.num_samplers : 0;
278 unsigned i;
279
280 if (tex->num_samplers > 0) {
281 /* output sampler state: */
282 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
283 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
284 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
285 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
286 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
287 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
288 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
289 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
290 for (i = 0; i < tex->num_samplers; i++) {
291 static const struct fd5_sampler_stateobj dummy_sampler = {};
292 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
293 fd5_sampler_stateobj(tex->samplers[i]) :
294 &dummy_sampler;
295 OUT_RING(ring, sampler->texsamp0);
296 OUT_RING(ring, sampler->texsamp1);
297 OUT_RING(ring, sampler->texsamp2 |
298 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
299 OUT_RING(ring, sampler->texsamp3);
300
301 needs_border |= sampler->needs_border;
302 }
303 }
304
305 if (tex->num_textures > 0) {
306 unsigned num_textures = tex->num_textures;
307
308 /* emit texture state: */
309 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
310 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
311 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
312 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
313 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
314 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
315 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
316 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
317 for (i = 0; i < tex->num_textures; i++) {
318 static const struct fd5_pipe_sampler_view dummy_view = {};
319 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
320 fd5_pipe_sampler_view(tex->textures[i]) :
321 &dummy_view;
322
323 OUT_RING(ring, view->texconst0);
324 OUT_RING(ring, view->texconst1);
325 OUT_RING(ring, view->texconst2);
326 OUT_RING(ring, view->texconst3);
327 if (view->base.texture) {
328 struct fd_resource *rsc = fd_resource(view->base.texture);
329 OUT_RELOC(ring, rsc->bo, view->offset,
330 (uint64_t)view->texconst5 << 32, 0);
331 } else {
332 OUT_RING(ring, 0x00000000);
333 OUT_RING(ring, view->texconst5);
334 }
335 OUT_RING(ring, view->texconst6);
336 OUT_RING(ring, view->texconst7);
337 OUT_RING(ring, view->texconst8);
338 OUT_RING(ring, view->texconst9);
339 OUT_RING(ring, view->texconst10);
340 OUT_RING(ring, view->texconst11);
341 }
342 }
343
344 return needs_border;
345 }
346
347 void
348 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
349 {
350 int32_t i, j;
351 const struct fd_vertex_state *vtx = emit->vtx;
352 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
353
354 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
355 if (vp->inputs[i].sysval)
356 continue;
357 if (vp->inputs[i].compmask) {
358 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
359 const struct pipe_vertex_buffer *vb =
360 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
361 struct fd_resource *rsc = fd_resource(vb->buffer);
362 enum pipe_format pfmt = elem->src_format;
363 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
364 bool isint = util_format_is_pure_integer(pfmt);
365 uint32_t off = vb->buffer_offset + elem->src_offset;
366 uint32_t size = fd_bo_size(rsc->bo) - off;
367 debug_assert(fmt != ~0);
368
369 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
370 OUT_RELOC(ring, rsc->bo, off, 0, 0);
371 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
372 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
373
374 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
375 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
376 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
377 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
378 A5XX_VFD_DECODE_INSTR_UNK30 |
379 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
380 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
381
382 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
383 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
384 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
385
386 j++;
387 }
388 }
389
390 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
391 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
392 }
393
394 void
395 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
396 struct fd5_emit *emit)
397 {
398 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
399 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
400 uint32_t dirty = emit->dirty;
401 bool needs_border = false;
402
403 emit_marker5(ring, 5);
404
405 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
406 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
407 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
408
409 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
410 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
411 }
412
413 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
414 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
415 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
416 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
417 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
418 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
419 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
420 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
421 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
422 }
423
424 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
425 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
426 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
427 uint32_t rb_alpha_control = zsa->rb_alpha_control;
428
429 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
430 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
431
432 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
433 OUT_RING(ring, rb_alpha_control);
434
435 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
436 OUT_RING(ring, zsa->rb_stencil_control);
437 }
438
439 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
440 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
441 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
442
443 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 1);
444 OUT_RING(ring, zsa->rb_stencilrefmask |
445 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
446 }
447
448 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
449 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
450 bool fragz = fp->has_kill | fp->writes_pos;
451
452 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
453 OUT_RING(ring, zsa->rb_depth_cntl);
454
455 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
456 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
457 COND(fragz && fp->frag_coord, A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
458
459 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
460 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
461 COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
462 }
463
464 if (dirty & FD_DIRTY_RASTERIZER) {
465 struct fd5_rasterizer_stateobj *rasterizer =
466 fd5_rasterizer_stateobj(ctx->rasterizer);
467
468 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
469 OUT_RING(ring, rasterizer->gras_su_cntl);
470
471 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
472 OUT_RING(ring, rasterizer->gras_su_point_minmax);
473 OUT_RING(ring, rasterizer->gras_su_point_size);
474
475 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
476 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
477 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
478 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
479 }
480
481 /* NOTE: since primitive_restart is not actually part of any
482 * state object, we need to make sure that we always emit
483 * PRIM_VTX_CNTL.. either that or be more clever and detect
484 * when it changes.
485 */
486 if (emit->info) {
487 struct fd5_rasterizer_stateobj *rast =
488 fd5_rasterizer_stateobj(ctx->rasterizer);
489 uint32_t val = rast->pc_prim_vtx_cntl;
490
491 val |= COND(vp->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE);
492
493 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
494 OUT_RING(ring, val);
495 }
496
497 if (dirty & FD_DIRTY_SCISSOR) {
498 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
499
500 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
501 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
502 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
503 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
504 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
505
506 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
507 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
508 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
509 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
510 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
511
512 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
513 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
514 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
515 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
516 }
517
518 if (dirty & FD_DIRTY_VIEWPORT) {
519 fd_wfi(ctx->batch, ring);
520 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
521 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
522 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
523 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
524 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
525 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
526 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
527 }
528
529 if (dirty & FD_DIRTY_PROG)
530 fd5_program_emit(ring, emit);
531
532 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER)) {
533 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
534 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
535 unsigned nr = pfb->nr_cbufs;
536
537 if (emit->key.binning_pass)
538 nr = 0;
539 else if (ctx->rasterizer->rasterizer_discard)
540 nr = 0;
541
542 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
543 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
544 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
545
546 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
547 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
548 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
549 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
550 }
551
552 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
553 ir3_emit_consts(vp, ring, ctx, emit->info, dirty);
554 if (!emit->key.binning_pass)
555 ir3_emit_consts(fp, ring, ctx, emit->info, dirty);
556
557 struct pipe_stream_output_info *info = &vp->shader->stream_output;
558 if (info->num_outputs) {
559 struct fd_streamout_stateobj *so = &ctx->streamout;
560
561 for (unsigned i = 0; i < so->num_targets; i++) {
562 struct pipe_stream_output_target *target = so->targets[i];
563
564 if (!target)
565 continue;
566
567 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
568 target->buffer_offset;
569
570 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
571 /* VPC_SO[i].BUFFER_BASE_LO: */
572 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
573 OUT_RING(ring, target->buffer_size + offset);
574
575 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
576 OUT_RING(ring, offset);
577 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
578 // TODO just give hw a dummy addr for now.. we should
579 // be using this an then CP_MEM_TO_REG to set the
580 // VPC_SO[i].BUFFER_OFFSET for the next draw..
581 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
582
583 emit->streamout_mask |= (1 << i);
584 }
585 }
586 }
587
588 if ((dirty & FD_DIRTY_BLEND)) {
589 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
590 uint32_t i;
591
592 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
593 enum pipe_format format = pipe_surface_format(
594 ctx->batch->framebuffer.cbufs[i]);
595 bool is_int = util_format_is_pure_integer(format);
596 bool has_alpha = util_format_has_alpha(format);
597 uint32_t control = blend->rb_mrt[i].control;
598 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
599
600 if (is_int) {
601 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
602 // control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
603 }
604
605 if (has_alpha) {
606 blend_control |= blend->rb_mrt[i].blend_control_rgb;
607 } else {
608 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
609 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
610 }
611
612 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
613 OUT_RING(ring, control);
614
615 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
616 OUT_RING(ring, blend_control);
617 }
618
619 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
620 OUT_RING(ring, blend->rb_blend_cntl |
621 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(0xffff));
622
623 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
624 OUT_RING(ring, 0x00000100);
625 }
626
627 if (dirty & FD_DIRTY_BLEND_COLOR) {
628 struct pipe_blend_color *bcolor = &ctx->blend_color;
629
630 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
631 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
632 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
633 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
634 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
635 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
636 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
637 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
638 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
639 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
640 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
641 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
642 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
643 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
644 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
645 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
646 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
647 }
648
649 if (dirty & FD_DIRTY_VERTTEX) {
650 if (vp->has_samp) {
651 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX, &ctx->verttex);
652 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
653 OUT_RING(ring, ctx->verttex.num_textures);
654 } else {
655 dirty &= ~FD_DIRTY_VERTTEX;
656 }
657 }
658
659 if (dirty & FD_DIRTY_FRAGTEX) {
660 if (fp->has_samp) {
661 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX, &ctx->fragtex);
662 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
663 OUT_RING(ring, ctx->fragtex.num_textures);
664 } else {
665 dirty &= ~FD_DIRTY_FRAGTEX;
666 }
667 }
668
669 if (needs_border)
670 emit_border_color(ctx, ring);
671
672 ctx->dirty &= ~dirty;
673 }
674
675 /* emit setup at begin of new cmdstream buffer (don't rely on previous
676 * state, there could have been a context switch between ioctls):
677 */
678 void
679 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
680 {
681 struct fd_context *ctx = batch->ctx;
682
683 fd5_set_render_mode(ctx, ring, BYPASS);
684 fd5_cache_flush(batch, ring);
685
686 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
687 OUT_RING(ring, 0xfffff);
688
689 /*
690 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
691 0000000500024048: 70d08003 00000000 001c5000 00000005
692 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
693 0000000500024058: 70d08003 00000010 001c7000 00000005
694
695 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
696 0000000500024068: 70268000
697 */
698
699 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
700 OUT_RING(ring, 0xffffffff);
701
702 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
703 OUT_RING(ring, 0x00000012);
704
705 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
706 OUT_RING(ring, 0x00000000);
707
708 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
709 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
710 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
711 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
712
713 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
714 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
715
716 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
717 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
718
719 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
720 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
721
722 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
723 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
724
725 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
726 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
727 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
728
729 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
730 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
731
732 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
733 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
734
735 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
736 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
737
738 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
739 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
740
741 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
742 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
743
744 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
745 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
746
747 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
748 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
749
750 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
751 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
752 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
753
754 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
755 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
756
757 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
758 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
759
760 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
761 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
762
763 /* we don't use this yet.. probably best to disable.. */
764 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
765 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
766 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
767 CP_SET_DRAW_STATE__0_GROUP_ID(0));
768 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
769 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
770
771 /* other regs not used (yet?) and always seem to have same value: */
772 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
773 OUT_RING(ring, 0x00000080); /* GRAS_CL_CNTL */
774
775 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
776 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
777
778 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
779 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
780
781 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
782 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
783
784 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
785 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
786
787 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
788 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
789
790 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
791 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
792 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
793 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
794
795 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
796 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
797 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
798
799 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
800 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
801
802 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
803 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
804
805 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
806 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
807
808 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
809 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
810
811 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
812 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
813
814 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E093, 1);
815 OUT_RING(ring, 0x00000000); /* UNKNOWN_E093 */
816
817 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E1C7, 1);
818 OUT_RING(ring, 0x00000000); /* UNKNOWN_E1C7 */
819
820 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
821 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
822
823 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
824 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
825
826 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
827 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
828
829 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
830 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
831
832 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E38D, 1);
833 OUT_RING(ring, 0x00000000); /* UNKNOWN_E38D */
834
835 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
836 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
837
838 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
839 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
840
841 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
842 OUT_RING(ring, 0x00000000);
843 OUT_RING(ring, 0x00000000);
844 OUT_RING(ring, 0x00000000);
845
846 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
847 OUT_RING(ring, 0x00000000);
848 OUT_RING(ring, 0x00000000);
849 OUT_RING(ring, 0x00000000);
850 OUT_RING(ring, 0x00000000);
851 OUT_RING(ring, 0x00000000);
852 OUT_RING(ring, 0x00000000);
853
854 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
855 OUT_RING(ring, 0x00000000);
856 OUT_RING(ring, 0x00000000);
857 OUT_RING(ring, 0x00000000);
858 OUT_RING(ring, 0x00000000);
859 OUT_RING(ring, 0x00000000);
860 OUT_RING(ring, 0x00000000);
861
862 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
863 OUT_RING(ring, 0x00000000);
864 OUT_RING(ring, 0x00000000);
865 OUT_RING(ring, 0x00000000);
866
867 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
868 OUT_RING(ring, 0x00000000);
869
870 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E600, 1);
871 OUT_RING(ring, 0x00000000);
872
873 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E640, 1);
874 OUT_RING(ring, 0x00000000);
875
876 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
877 OUT_RING(ring, 0x00000000);
878 OUT_RING(ring, 0x00000000);
879 OUT_RING(ring, 0x00000000);
880 OUT_RING(ring, 0x00000000);
881
882 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
883 OUT_RING(ring, 0x00000000);
884 OUT_RING(ring, 0x00000000);
885
886 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
887 OUT_RING(ring, 0x00000000);
888 OUT_RING(ring, 0x00000000);
889 OUT_RING(ring, 0x00000000);
890
891 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
892 OUT_RING(ring, 0x00000000);
893 OUT_RING(ring, 0x00000000);
894 OUT_RING(ring, 0x00000000);
895
896 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
897 OUT_RING(ring, 0x00000000);
898 OUT_RING(ring, 0x00000000);
899 OUT_RING(ring, 0x00000000);
900
901 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
902 OUT_RING(ring, 0x00000000);
903 OUT_RING(ring, 0x00000000);
904 OUT_RING(ring, 0x00000000);
905
906 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
907 OUT_RING(ring, 0x00000000);
908 OUT_RING(ring, 0x00000000);
909 OUT_RING(ring, 0x00000000);
910
911 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
912 OUT_RING(ring, 0x00000000);
913 OUT_RING(ring, 0x00000000);
914 OUT_RING(ring, 0x00000000);
915
916 // TODO hacks.. these should not be hardcoded:
917 OUT_PKT4(ring, REG_A5XX_GRAS_SC_CNTL, 1);
918 OUT_RING(ring, 0x00000008); /* GRAS_SC_CNTL */
919
920 fd_hw_query_enable(batch, ring);
921 }
922
923 static void
924 fd5_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
925 {
926 __OUT_IB5(ring, target);
927 }
928
929 void
930 fd5_emit_init(struct pipe_context *pctx)
931 {
932 struct fd_context *ctx = fd_context(pctx);
933 ctx->emit_const = fd5_emit_const;
934 ctx->emit_const_bo = fd5_emit_const_bo;
935 ctx->emit_ib = fd5_emit_ib;
936 }